2 // Register Declarations for Microchip 16C63A Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define PIR2_ADDR 0x000D
40 #define TMR1L_ADDR 0x000E
41 #define TMR1H_ADDR 0x000F
42 #define T1CON_ADDR 0x0010
43 #define TMR2_ADDR 0x0011
44 #define T2CON_ADDR 0x0012
45 #define SSPBUF_ADDR 0x0013
46 #define SSPCON_ADDR 0x0014
47 #define CCPR1L_ADDR 0x0015
48 #define CCPR1H_ADDR 0x0016
49 #define CCP1CON_ADDR 0x0017
50 #define RCSTA_ADDR 0x0018
51 #define TXREG_ADDR 0x0019
52 #define RCREG_ADDR 0x001A
53 #define CCPR2L_ADDR 0x001B
54 #define CCPR2H_ADDR 0x001C
55 #define CCP2CON_ADDR 0x001D
56 #define OPTION_REG_ADDR 0x0081
57 #define TRISA_ADDR 0x0085
58 #define TRISB_ADDR 0x0086
59 #define TRISC_ADDR 0x0087
60 #define PIE1_ADDR 0x008C
61 #define PIE2_ADDR 0x008D
62 #define PCON_ADDR 0x008E
63 #define PR2_ADDR 0x0092
64 #define SSPADD_ADDR 0x0093
65 #define SSPSTAT_ADDR 0x0094
66 #define TXSTA_ADDR 0x0098
67 #define SPBRG_ADDR 0x0099
70 // Memory organization.
76 // P16C63A.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
79 // This header file defines configurations, registers, and other useful bits of
80 // information for the PIC16C63A microcontroller. These names are taken to match
81 // the data sheets as closely as possible.
83 // Note that the processor must be selected before this file is
84 // included. The processor may be selected the following ways:
86 // 1. Command line switch:
87 // C:\ MPASM MYFILE.ASM /PIC16C63A
88 // 2. LIST directive in the source file
90 // 3. Processor Type entry in the MPASM full-screen interface
92 //==========================================================================
96 //==========================================================================
100 //1.00 12/17/97 Initial Release
102 //==========================================================================
106 //==========================================================================
109 // MESSG "Processor-header file mismatch. Verify selected processor."
112 //==========================================================================
114 // Register Definitions
116 //==========================================================================
121 //----- Register Files------------------------------------------------------
123 extern __data __at (INDF_ADDR) volatile char INDF;
124 extern __sfr __at (TMR0_ADDR) TMR0;
125 extern __data __at (PCL_ADDR) volatile char PCL;
126 extern __sfr __at (STATUS_ADDR) STATUS;
127 extern __sfr __at (FSR_ADDR) FSR;
128 extern __sfr __at (PORTA_ADDR) PORTA;
129 extern __sfr __at (PORTB_ADDR) PORTB;
130 extern __sfr __at (PORTC_ADDR) PORTC;
131 extern __sfr __at (PCLATH_ADDR) PCLATH;
132 extern __sfr __at (INTCON_ADDR) INTCON;
133 extern __sfr __at (PIR1_ADDR) PIR1;
134 extern __sfr __at (PIR2_ADDR) PIR2;
135 extern __sfr __at (TMR1L_ADDR) TMR1L;
136 extern __sfr __at (TMR1H_ADDR) TMR1H;
137 extern __sfr __at (T1CON_ADDR) T1CON;
138 extern __sfr __at (TMR2_ADDR) TMR2;
139 extern __sfr __at (T2CON_ADDR) T2CON;
140 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
141 extern __sfr __at (SSPCON_ADDR) SSPCON;
142 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
143 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
144 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
145 extern __sfr __at (RCSTA_ADDR) RCSTA;
146 extern __sfr __at (TXREG_ADDR) TXREG;
147 extern __sfr __at (RCREG_ADDR) RCREG;
148 extern __sfr __at (CCPR2L_ADDR) CCPR2L;
149 extern __sfr __at (CCPR2H_ADDR) CCPR2H;
150 extern __sfr __at (CCP2CON_ADDR) CCP2CON;
152 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
153 extern __sfr __at (TRISA_ADDR) TRISA;
154 extern __sfr __at (TRISB_ADDR) TRISB;
155 extern __sfr __at (TRISC_ADDR) TRISC;
156 extern __sfr __at (PIE1_ADDR) PIE1;
157 extern __sfr __at (PIE2_ADDR) PIE2;
158 extern __sfr __at (PCON_ADDR) PCON;
159 extern __sfr __at (PR2_ADDR) PR2;
160 extern __sfr __at (SSPADD_ADDR) SSPADD;
161 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
162 extern __sfr __at (TXSTA_ADDR) TXSTA;
163 extern __sfr __at (SPBRG_ADDR) SPBRG;
165 //----- STATUS Bits --------------------------------------------------------
168 //----- INTCON Bits --------------------------------------------------------
171 //----- PIR1 Bits ----------------------------------------------------------
174 //----- PIR2 Bits ----------------------------------------------------------
177 //----- T1CON Bits ---------------------------------------------------------
180 //----- T2CON Bits ---------------------------------------------------------
183 //----- SSPCON Bits --------------------------------------------------------
186 //----- CCP1CON Bits -------------------------------------------------------
189 //----- RCSTA Bits ---------------------------------------------------------
192 //----- CCP2CON Bits -------------------------------------------------------
195 //----- OPTION Bits --------------------------------------------------------
198 //----- PIE1 Bits ----------------------------------------------------------
201 //----- PIE2 Bits ----------------------------------------------------------
204 //----- PCON Bits ----------------------------------------------------------
207 //----- SSPSTAT Bits -------------------------------------------------------
210 //----- TXSTA Bits ---------------------------------------------------------
213 //==========================================================================
217 //==========================================================================
220 // __BADRAM H'08'-H'09', H'1E'-H'1F'
221 // __BADRAM H'88'-H'89', H'8F'-H'91', H'95'-H'97', H'9A'-H'9F'
223 //==========================================================================
225 // Configuration Bits
227 //==========================================================================
229 #define _BODEN_ON 0x3FFF
230 #define _BODEN_OFF 0x3FBF
231 #define _CP_ALL 0x00CF
232 #define _CP_75 0x15DF
233 #define _CP_50 0x2AEF
234 #define _CP_OFF 0x3FFF
235 #define _PWRTE_OFF 0x3FFF
236 #define _PWRTE_ON 0x3FF7
237 #define _WDT_ON 0x3FFF
238 #define _WDT_OFF 0x3FFB
239 #define _LP_OSC 0x3FFC
240 #define _XT_OSC 0x3FFD
241 #define _HS_OSC 0x3FFE
242 #define _RC_OSC 0x3FFF
246 // ----- CCP1CON bits --------------------
249 unsigned char CCP1M0:1;
250 unsigned char CCP1M1:1;
251 unsigned char CCP1M2:1;
252 unsigned char CCP1M3:1;
253 unsigned char CCP1Y:1;
254 unsigned char CCP1X:1;
259 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
261 #define CCP1M0 CCP1CON_bits.CCP1M0
262 #define CCP1M1 CCP1CON_bits.CCP1M1
263 #define CCP1M2 CCP1CON_bits.CCP1M2
264 #define CCP1M3 CCP1CON_bits.CCP1M3
265 #define CCP1Y CCP1CON_bits.CCP1Y
266 #define CCP1X CCP1CON_bits.CCP1X
268 // ----- CCP2CON bits --------------------
271 unsigned char CCP2M0:1;
272 unsigned char CCP2M1:1;
273 unsigned char CCP2M2:1;
274 unsigned char CCP2M3:1;
275 unsigned char CCP2Y:1;
276 unsigned char CCP2X:1;
281 extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;
283 #define CCP2M0 CCP2CON_bits.CCP2M0
284 #define CCP2M1 CCP2CON_bits.CCP2M1
285 #define CCP2M2 CCP2CON_bits.CCP2M2
286 #define CCP2M3 CCP2CON_bits.CCP2M3
287 #define CCP2Y CCP2CON_bits.CCP2Y
288 #define CCP2X CCP2CON_bits.CCP2X
290 // ----- INTCON bits --------------------
293 unsigned char RBIF:1;
294 unsigned char INTF:1;
295 unsigned char T0IF:1;
296 unsigned char RBIE:1;
297 unsigned char INTE:1;
298 unsigned char T0IE:1;
299 unsigned char PEIE:1;
303 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
305 #define RBIF INTCON_bits.RBIF
306 #define INTF INTCON_bits.INTF
307 #define T0IF INTCON_bits.T0IF
308 #define RBIE INTCON_bits.RBIE
309 #define INTE INTCON_bits.INTE
310 #define T0IE INTCON_bits.T0IE
311 #define PEIE INTCON_bits.PEIE
312 #define GIE INTCON_bits.GIE
314 // ----- OPTION_REG bits --------------------
321 unsigned char T0SE:1;
322 unsigned char T0CS:1;
323 unsigned char INTEDG:1;
324 unsigned char NOT_RBPU:1;
326 } __OPTION_REG_bits_t;
327 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
329 #define PS0 OPTION_REG_bits.PS0
330 #define PS1 OPTION_REG_bits.PS1
331 #define PS2 OPTION_REG_bits.PS2
332 #define PSA OPTION_REG_bits.PSA
333 #define T0SE OPTION_REG_bits.T0SE
334 #define T0CS OPTION_REG_bits.T0CS
335 #define INTEDG OPTION_REG_bits.INTEDG
336 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
338 // ----- PCON bits --------------------
341 unsigned char NOT_BO:1;
342 unsigned char NOT_POR:1;
351 unsigned char NOT_BOR:1;
361 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
363 #define NOT_BO PCON_bits.NOT_BO
364 #define NOT_BOR PCON_bits.NOT_BOR
365 #define NOT_POR PCON_bits.NOT_POR
367 // ----- PIE1 bits --------------------
370 unsigned char TMR1IE:1;
371 unsigned char TMR2IE:1;
372 unsigned char CCP1IE:1;
373 unsigned char SSPIE:1;
374 unsigned char TXIE:1;
375 unsigned char RCIE:1;
380 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
382 #define TMR1IE PIE1_bits.TMR1IE
383 #define TMR2IE PIE1_bits.TMR2IE
384 #define CCP1IE PIE1_bits.CCP1IE
385 #define SSPIE PIE1_bits.SSPIE
386 #define TXIE PIE1_bits.TXIE
387 #define RCIE PIE1_bits.RCIE
389 // ----- PIE2 bits --------------------
392 unsigned char CCP2IE:1;
402 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
404 #define CCP2IE PIE2_bits.CCP2IE
406 // ----- PIR1 bits --------------------
409 unsigned char TMR1IF:1;
410 unsigned char TMR2IF:1;
411 unsigned char CCP1IF:1;
412 unsigned char SSPIF:1;
413 unsigned char TXIF:1;
414 unsigned char RCIF:1;
419 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
421 #define TMR1IF PIR1_bits.TMR1IF
422 #define TMR2IF PIR1_bits.TMR2IF
423 #define CCP1IF PIR1_bits.CCP1IF
424 #define SSPIF PIR1_bits.SSPIF
425 #define TXIF PIR1_bits.TXIF
426 #define RCIF PIR1_bits.RCIF
428 // ----- PIR2 bits --------------------
431 unsigned char CCP2IF:1;
441 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
443 #define CCP2IF PIR2_bits.CCP2IF
445 // ----- RCSTA bits --------------------
448 unsigned char RX9D:1;
449 unsigned char OERR:1;
450 unsigned char FERR:1;
452 unsigned char CREN:1;
453 unsigned char SREN:1;
455 unsigned char SPEN:1;
458 unsigned char RCD8:1;
474 unsigned char NOT_RC8:1;
484 unsigned char RC8_9:1;
488 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
490 #define RX9D RCSTA_bits.RX9D
491 #define RCD8 RCSTA_bits.RCD8
492 #define OERR RCSTA_bits.OERR
493 #define FERR RCSTA_bits.FERR
494 #define CREN RCSTA_bits.CREN
495 #define SREN RCSTA_bits.SREN
496 #define RX9 RCSTA_bits.RX9
497 #define RC9 RCSTA_bits.RC9
498 #define NOT_RC8 RCSTA_bits.NOT_RC8
499 #define RC8_9 RCSTA_bits.RC8_9
500 #define SPEN RCSTA_bits.SPEN
502 // ----- SSPCON bits --------------------
505 unsigned char SSPM0:1;
506 unsigned char SSPM1:1;
507 unsigned char SSPM2:1;
508 unsigned char SSPM3:1;
510 unsigned char SSPEN:1;
511 unsigned char SSPOV:1;
512 unsigned char WCOL:1;
515 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
517 #define SSPM0 SSPCON_bits.SSPM0
518 #define SSPM1 SSPCON_bits.SSPM1
519 #define SSPM2 SSPCON_bits.SSPM2
520 #define SSPM3 SSPCON_bits.SSPM3
521 #define CKP SSPCON_bits.CKP
522 #define SSPEN SSPCON_bits.SSPEN
523 #define SSPOV SSPCON_bits.SSPOV
524 #define WCOL SSPCON_bits.WCOL
526 // ----- SSPSTAT bits --------------------
541 unsigned char I2C_READ:1;
542 unsigned char I2C_START:1;
543 unsigned char I2C_STOP:1;
544 unsigned char I2C_DATA:1;
551 unsigned char NOT_W:1;
554 unsigned char NOT_A:1;
561 unsigned char NOT_WRITE:1;
564 unsigned char NOT_ADDRESS:1;
581 unsigned char READ_WRITE:1;
584 unsigned char DATA_ADDRESS:1;
589 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
591 #define BF SSPSTAT_bits.BF
592 #define UA SSPSTAT_bits.UA
593 #define R SSPSTAT_bits.R
594 #define I2C_READ SSPSTAT_bits.I2C_READ
595 #define NOT_W SSPSTAT_bits.NOT_W
596 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
597 #define R_W SSPSTAT_bits.R_W
598 #define READ_WRITE SSPSTAT_bits.READ_WRITE
599 #define S SSPSTAT_bits.S
600 #define I2C_START SSPSTAT_bits.I2C_START
601 #define P SSPSTAT_bits.P
602 #define I2C_STOP SSPSTAT_bits.I2C_STOP
603 #define D SSPSTAT_bits.D
604 #define I2C_DATA SSPSTAT_bits.I2C_DATA
605 #define NOT_A SSPSTAT_bits.NOT_A
606 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
607 #define D_A SSPSTAT_bits.D_A
608 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
609 #define CKE SSPSTAT_bits.CKE
610 #define SMP SSPSTAT_bits.SMP
612 // ----- STATUS bits --------------------
618 unsigned char NOT_PD:1;
619 unsigned char NOT_TO:1;
625 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
627 #define C STATUS_bits.C
628 #define DC STATUS_bits.DC
629 #define Z STATUS_bits.Z
630 #define NOT_PD STATUS_bits.NOT_PD
631 #define NOT_TO STATUS_bits.NOT_TO
632 #define RP0 STATUS_bits.RP0
633 #define RP1 STATUS_bits.RP1
634 #define IRP STATUS_bits.IRP
636 // ----- T1CON bits --------------------
639 unsigned char TMR1ON:1;
640 unsigned char TMR1CS:1;
641 unsigned char NOT_T1SYNC:1;
642 unsigned char T1OSCEN:1;
643 unsigned char T1CKPS0:1;
644 unsigned char T1CKPS1:1;
651 unsigned char T1INSYNC:1;
659 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
661 #define TMR1ON T1CON_bits.TMR1ON
662 #define TMR1CS T1CON_bits.TMR1CS
663 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
664 #define T1INSYNC T1CON_bits.T1INSYNC
665 #define T1OSCEN T1CON_bits.T1OSCEN
666 #define T1CKPS0 T1CON_bits.T1CKPS0
667 #define T1CKPS1 T1CON_bits.T1CKPS1
669 // ----- T2CON bits --------------------
672 unsigned char T2CKPS0:1;
673 unsigned char T2CKPS1:1;
674 unsigned char TMR2ON:1;
675 unsigned char TOUTPS0:1;
676 unsigned char TOUTPS1:1;
677 unsigned char TOUTPS2:1;
678 unsigned char TOUTPS3:1;
682 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
684 #define T2CKPS0 T2CON_bits.T2CKPS0
685 #define T2CKPS1 T2CON_bits.T2CKPS1
686 #define TMR2ON T2CON_bits.TMR2ON
687 #define TOUTPS0 T2CON_bits.TOUTPS0
688 #define TOUTPS1 T2CON_bits.TOUTPS1
689 #define TOUTPS2 T2CON_bits.TOUTPS2
690 #define TOUTPS3 T2CON_bits.TOUTPS3
692 // ----- TXSTA bits --------------------
695 unsigned char TX9D:1;
696 unsigned char TRMT:1;
697 unsigned char BRGH:1;
699 unsigned char SYNC:1;
700 unsigned char TXEN:1;
702 unsigned char CSRC:1;
705 unsigned char TXD8:1;
711 unsigned char NOT_TX8:1;
721 unsigned char TX8_9:1;
725 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
727 #define TX9D TXSTA_bits.TX9D
728 #define TXD8 TXSTA_bits.TXD8
729 #define TRMT TXSTA_bits.TRMT
730 #define BRGH TXSTA_bits.BRGH
731 #define SYNC TXSTA_bits.SYNC
732 #define TXEN TXSTA_bits.TXEN
733 #define TX9 TXSTA_bits.TX9
734 #define NOT_TX8 TXSTA_bits.NOT_TX8
735 #define TX8_9 TXSTA_bits.TX8_9
736 #define CSRC TXSTA_bits.CSRC