2 // Register Declarations for Microchip 16C622A Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PCLATH_ADDR 0x000A
36 #define INTCON_ADDR 0x000B
37 #define PIR1_ADDR 0x000C
38 #define CMCON_ADDR 0x001F
39 #define OPTION_REG_ADDR 0x0081
40 #define TRISA_ADDR 0x0085
41 #define TRISB_ADDR 0x0086
42 #define PIE1_ADDR 0x008C
43 #define PCON_ADDR 0x008E
44 #define VRCON_ADDR 0x009F
47 // Memory organization.
53 // P16C622A.INC Standard Header File, Version 1.10 Microchip Technology, Inc.
56 // This header file defines configurations, registers, and other useful bits of
57 // information for the PIC16C622A microcontroller. These names are taken to match
58 // the data sheets as closely as possible.
60 // Note that the processor must be selected before this file is
61 // included. The processor may be selected the following ways:
63 // 1. Command line switch:
64 // C:\ MPASM MYFILE.ASM /PIC16C622A
65 // 2. LIST directive in the source file
67 // 3. Processor Type entry in the MPASM full-screen interface
69 //==========================================================================
73 //==========================================================================
77 //1.00 05/28/97 Initial Release
78 //1.10 16/08/99 Added unbanked RAM at 70-7F
80 //==========================================================================
84 //==========================================================================
87 // MESSG "Processor-header file mismatch. Verify selected processor."
90 //==========================================================================
92 // Register Definitions
94 //==========================================================================
99 //----- Register Files------------------------------------------------------
101 extern __data __at (INDF_ADDR) volatile char INDF;
102 extern __sfr __at (TMR0_ADDR) TMR0;
103 extern __data __at (PCL_ADDR) volatile char PCL;
104 extern __sfr __at (STATUS_ADDR) STATUS;
105 extern __sfr __at (FSR_ADDR) FSR;
106 extern __sfr __at (PORTA_ADDR) PORTA;
107 extern __sfr __at (PORTB_ADDR) PORTB;
108 extern __sfr __at (PCLATH_ADDR) PCLATH;
109 extern __sfr __at (INTCON_ADDR) INTCON;
110 extern __sfr __at (PIR1_ADDR) PIR1;
111 extern __sfr __at (CMCON_ADDR) CMCON;
113 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
114 extern __sfr __at (TRISA_ADDR) TRISA;
115 extern __sfr __at (TRISB_ADDR) TRISB;
116 extern __sfr __at (PIE1_ADDR) PIE1;
117 extern __sfr __at (PCON_ADDR) PCON;
118 extern __sfr __at (VRCON_ADDR) VRCON;
120 //----- STATUS Bits --------------------------------------------------------
123 //----- INTCON Bits --------------------------------------------------------
126 //----- PIR1 Bits ----------------------------------------------------------
129 //----- CMCON Bits ---------------------------------------------------------
132 //----- OPTION Bits --------------------------------------------------------
135 //----- PIE1 Bits ----------------------------------------------------------
138 //----- PCON Bits ----------------------------------------------------------
141 //----- VRCON Bits ---------------------------------------------------------
144 //==========================================================================
148 //==========================================================================
151 // __BADRAM H'07'-H'09', H'0D'-H'1E', H'87'-H'89', H'8D', H'8F'-H'9E'
152 // __BADRAM H'C0'-H'EF'
154 //==========================================================================
156 // Configuration Bits
158 //==========================================================================
160 #define _BODEN_ON 0x3FFF
161 #define _BODEN_OFF 0x3FBF
162 #define _CP_ALL 0x00CF
163 #define _CP_75 0x15DF
164 #define _CP_50 0x2AEF
165 #define _CP_OFF 0x3FFF
166 #define _PWRTE_OFF 0x3FFF
167 #define _PWRTE_ON 0x3FF7
168 #define _WDT_ON 0x3FFF
169 #define _WDT_OFF 0x3FFB
170 #define _LP_OSC 0x3FFC
171 #define _XT_OSC 0x3FFD
172 #define _HS_OSC 0x3FFE
173 #define _RC_OSC 0x3FFF
177 // ----- CMCON bits --------------------
186 unsigned char C1OUT:1;
187 unsigned char C2OUT:1;
190 extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;
192 #define CM0 CMCON_bits.CM0
193 #define CM1 CMCON_bits.CM1
194 #define CM2 CMCON_bits.CM2
195 #define CIS CMCON_bits.CIS
196 #define C1OUT CMCON_bits.C1OUT
197 #define C2OUT CMCON_bits.C2OUT
199 // ----- INTCON bits --------------------
202 unsigned char RBIF:1;
203 unsigned char INTF:1;
204 unsigned char T0IF:1;
205 unsigned char RBIE:1;
206 unsigned char INTE:1;
207 unsigned char T0IE:1;
208 unsigned char PEIE:1;
212 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
214 #define RBIF INTCON_bits.RBIF
215 #define INTF INTCON_bits.INTF
216 #define T0IF INTCON_bits.T0IF
217 #define RBIE INTCON_bits.RBIE
218 #define INTE INTCON_bits.INTE
219 #define T0IE INTCON_bits.T0IE
220 #define PEIE INTCON_bits.PEIE
221 #define GIE INTCON_bits.GIE
223 // ----- OPTION_REG bits --------------------
230 unsigned char T0SE:1;
231 unsigned char T0CS:1;
232 unsigned char INTEDG:1;
233 unsigned char NOT_RBPU:1;
235 } __OPTION_REG_bits_t;
236 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
238 #define PS0 OPTION_REG_bits.PS0
239 #define PS1 OPTION_REG_bits.PS1
240 #define PS2 OPTION_REG_bits.PS2
241 #define PSA OPTION_REG_bits.PSA
242 #define T0SE OPTION_REG_bits.T0SE
243 #define T0CS OPTION_REG_bits.T0CS
244 #define INTEDG OPTION_REG_bits.INTEDG
245 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
247 // ----- PCON bits --------------------
250 unsigned char NOT_BO:1;
251 unsigned char NOT_POR:1;
260 unsigned char NOT_BOR:1;
270 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
272 #define NOT_BO PCON_bits.NOT_BO
273 #define NOT_BOR PCON_bits.NOT_BOR
274 #define NOT_POR PCON_bits.NOT_POR
276 // ----- PIE1 bits --------------------
285 unsigned char CMIE:1;
289 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
291 #define CMIE PIE1_bits.CMIE
293 // ----- PIR1 bits --------------------
302 unsigned char CMIF:1;
306 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
308 #define CMIF PIR1_bits.CMIF
310 // ----- PORTA bits --------------------
323 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
325 #define RA0 PORTA_bits.RA0
326 #define RA1 PORTA_bits.RA1
327 #define RA2 PORTA_bits.RA2
328 #define RA3 PORTA_bits.RA3
329 #define RA4 PORTA_bits.RA4
330 #define RA5 PORTA_bits.RA5
332 // ----- PORTB bits --------------------
345 extern volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
347 #define RB0 PORTB_bits.RB0
348 #define RB1 PORTB_bits.RB1
349 #define RB2 PORTB_bits.RB2
350 #define RB3 PORTB_bits.RB3
351 #define RB4 PORTB_bits.RB4
352 #define RB5 PORTB_bits.RB5
353 #define RB6 PORTB_bits.RB6
354 #define RB7 PORTB_bits.RB7
356 // ----- STATUS bits --------------------
362 unsigned char NOT_PD:1;
363 unsigned char NOT_TO:1;
369 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
371 #define C STATUS_bits.C
372 #define DC STATUS_bits.DC
373 #define Z STATUS_bits.Z
374 #define NOT_PD STATUS_bits.NOT_PD
375 #define NOT_TO STATUS_bits.NOT_TO
376 #define RP0 STATUS_bits.RP0
377 #define RP1 STATUS_bits.RP1
378 #define IRP STATUS_bits.IRP
380 // ----- TRISA bits --------------------
383 unsigned char TRISA0:1;
384 unsigned char TRISA1:1;
385 unsigned char TRISA2:1;
386 unsigned char TRISA3:1;
387 unsigned char TRISA4:1;
388 unsigned char TRISA5:1;
393 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
395 #define TRISA0 TRISA_bits.TRISA0
396 #define TRISA1 TRISA_bits.TRISA1
397 #define TRISA2 TRISA_bits.TRISA2
398 #define TRISA3 TRISA_bits.TRISA3
399 #define TRISA4 TRISA_bits.TRISA4
400 #define TRISA5 TRISA_bits.TRISA5
402 // ----- TRISB bits --------------------
405 unsigned char TRISB0:1;
406 unsigned char TRISB1:1;
407 unsigned char TRISB2:1;
408 unsigned char TRISB3:1;
409 unsigned char TRISB4:1;
410 unsigned char TRISB5:1;
411 unsigned char TRISB6:1;
412 unsigned char TRISB7:1;
415 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
417 #define TRISB0 TRISB_bits.TRISB0
418 #define TRISB1 TRISB_bits.TRISB1
419 #define TRISB2 TRISB_bits.TRISB2
420 #define TRISB3 TRISB_bits.TRISB3
421 #define TRISB4 TRISB_bits.TRISB4
422 #define TRISB5 TRISB_bits.TRISB5
423 #define TRISB6 TRISB_bits.TRISB6
424 #define TRISB7 TRISB_bits.TRISB7
426 // ----- VRCON bits --------------------
435 unsigned char VROE:1;
436 unsigned char VREN:1;
439 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
441 #define VR0 VRCON_bits.VR0
442 #define VR1 VRCON_bits.VR1
443 #define VR2 VRCON_bits.VR2
444 #define VR3 VRCON_bits.VR3
445 #define VRR VRCON_bits.VRR
446 #define VROE VRCON_bits.VROE
447 #define VREN VRCON_bits.VREN