2 // Register Declarations for Microchip 16CR620A Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PCLATH_ADDR 0x000A
36 #define INTCON_ADDR 0x000B
37 #define PIR1_ADDR 0x000C
38 #define CMCON_ADDR 0x001F
39 #define OPTION_REG_ADDR 0x0081
40 #define TRISA_ADDR 0x0085
41 #define TRISB_ADDR 0x0086
42 #define PIE1_ADDR 0x008C
43 #define PCON_ADDR 0x008E
44 #define VRCON_ADDR 0x009F
47 // Memory organization.
53 // P16C620A.INC Standard Header File, Version 1.10 Microchip Technology, Inc.
56 // This header file defines configurations, registers, and other useful bits of
57 // information for the PIC16C620A and PIC16CR620A microcontrollers. These names are taken to match
58 // the data sheets as closely as possible.
60 // Note that the processor must be selected before this file is
61 // included. The processor may be selected the following ways:
63 // 1. Command line switch:
64 // C:\ MPASM MYFILE.ASM /PIC16C620A or
65 // C:\ MPASM MYFILE.ASM /PIC16CR620A
66 // 2. LIST directive in the source file
67 // LIST P=PIC16C620A or
69 // 3. Processor Type entry in the MPASM full-screen interface
71 //==========================================================================
75 //==========================================================================
79 //1.00 05/28/97 Initial Release
80 //1.10 16/08/99 Added unbanked RAM at 70-7F
81 //1.20 06/12/02 Verification now includes the PIC16CR620A (pas)
83 //==========================================================================
87 //==========================================================================
91 // MESSG "Processor-header file mismatch. Verify selected processor."
95 //==========================================================================
97 // Register Definitions
99 //==========================================================================
104 //----- Register Files------------------------------------------------------
106 extern __data __at (INDF_ADDR) volatile char INDF;
107 extern __sfr __at (TMR0_ADDR) TMR0;
108 extern __data __at (PCL_ADDR) volatile char PCL;
109 extern __sfr __at (STATUS_ADDR) STATUS;
110 extern __sfr __at (FSR_ADDR) FSR;
111 extern __sfr __at (PORTA_ADDR) PORTA;
112 extern __sfr __at (PORTB_ADDR) PORTB;
113 extern __sfr __at (PCLATH_ADDR) PCLATH;
114 extern __sfr __at (INTCON_ADDR) INTCON;
115 extern __sfr __at (PIR1_ADDR) PIR1;
116 extern __sfr __at (CMCON_ADDR) CMCON;
118 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
119 extern __sfr __at (TRISA_ADDR) TRISA;
120 extern __sfr __at (TRISB_ADDR) TRISB;
121 extern __sfr __at (PIE1_ADDR) PIE1;
122 extern __sfr __at (PCON_ADDR) PCON;
123 extern __sfr __at (VRCON_ADDR) VRCON;
125 //----- STATUS Bits --------------------------------------------------------
128 //----- INTCON Bits --------------------------------------------------------
131 //----- PIR1 Bits ----------------------------------------------------------
134 //----- CMCON Bits ---------------------------------------------------------
137 //----- OPTION Bits --------------------------------------------------------
140 //----- PIE1 Bits ----------------------------------------------------------
143 //----- PCON Bits ----------------------------------------------------------
146 //----- VRCON Bits ---------------------------------------------------------
149 //==========================================================================
153 //==========================================================================
156 // __BADRAM H'07'-H'09', H'0D'-H'1E'
157 // __BADRAM H'87'-H'89', H'8D', H'8F'-H'9E'
158 // __BADRAM H'A0'-H'EF'
160 //==========================================================================
162 // Configuration Bits
164 //==========================================================================
166 #define _BODEN_ON 0x3FFF
167 #define _BODEN_OFF 0x3FBF
168 #define _CP_ON 0x00CF
169 #define _CP_OFF 0x3FFF
170 #define _PWRTE_OFF 0x3FFF
171 #define _PWRTE_ON 0x3FF7
172 #define _WDT_ON 0x3FFF
173 #define _WDT_OFF 0x3FFB
174 #define _LP_OSC 0x3FFC
175 #define _XT_OSC 0x3FFD
176 #define _HS_OSC 0x3FFE
177 #define _RC_OSC 0x3FFF
181 // ----- CMCON bits --------------------
190 unsigned char C1OUT:1;
191 unsigned char C2OUT:1;
194 extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;
196 #define CM0 CMCON_bits.CM0
197 #define CM1 CMCON_bits.CM1
198 #define CM2 CMCON_bits.CM2
199 #define CIS CMCON_bits.CIS
200 #define C1OUT CMCON_bits.C1OUT
201 #define C2OUT CMCON_bits.C2OUT
203 // ----- INTCON bits --------------------
206 unsigned char RBIF:1;
207 unsigned char INTF:1;
208 unsigned char T0IF:1;
209 unsigned char RBIE:1;
210 unsigned char INTE:1;
211 unsigned char T0IE:1;
212 unsigned char PEIE:1;
216 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
218 #define RBIF INTCON_bits.RBIF
219 #define INTF INTCON_bits.INTF
220 #define T0IF INTCON_bits.T0IF
221 #define RBIE INTCON_bits.RBIE
222 #define INTE INTCON_bits.INTE
223 #define T0IE INTCON_bits.T0IE
224 #define PEIE INTCON_bits.PEIE
225 #define GIE INTCON_bits.GIE
227 // ----- OPTION_REG bits --------------------
234 unsigned char T0SE:1;
235 unsigned char T0CS:1;
236 unsigned char INTEDG:1;
237 unsigned char NOT_RBPU:1;
239 } __OPTION_REG_bits_t;
240 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
242 #define PS0 OPTION_REG_bits.PS0
243 #define PS1 OPTION_REG_bits.PS1
244 #define PS2 OPTION_REG_bits.PS2
245 #define PSA OPTION_REG_bits.PSA
246 #define T0SE OPTION_REG_bits.T0SE
247 #define T0CS OPTION_REG_bits.T0CS
248 #define INTEDG OPTION_REG_bits.INTEDG
249 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
251 // ----- PCON bits --------------------
254 unsigned char NOT_BO:1;
255 unsigned char NOT_POR:1;
264 unsigned char NOT_BOR:1;
274 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
276 #define NOT_BO PCON_bits.NOT_BO
277 #define NOT_BOR PCON_bits.NOT_BOR
278 #define NOT_POR PCON_bits.NOT_POR
280 // ----- PIE1 bits --------------------
289 unsigned char CMIE:1;
293 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
295 #define CMIE PIE1_bits.CMIE
297 // ----- PIR1 bits --------------------
306 unsigned char CMIF:1;
310 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
312 #define CMIF PIR1_bits.CMIF
314 // ----- STATUS bits --------------------
320 unsigned char NOT_PD:1;
321 unsigned char NOT_TO:1;
327 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
329 #define C STATUS_bits.C
330 #define DC STATUS_bits.DC
331 #define Z STATUS_bits.Z
332 #define NOT_PD STATUS_bits.NOT_PD
333 #define NOT_TO STATUS_bits.NOT_TO
334 #define RP0 STATUS_bits.RP0
335 #define RP1 STATUS_bits.RP1
336 #define IRP STATUS_bits.IRP
338 // ----- VRCON bits --------------------
347 unsigned char VROE:1;
348 unsigned char VREN:1;
351 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
353 #define VR0 VRCON_bits.VR0
354 #define VR1 VRCON_bits.VR1
355 #define VR2 VRCON_bits.VR2
356 #define VR3 VRCON_bits.VR3
357 #define VRR VRCON_bits.VRR
358 #define VROE VRCON_bits.VROE
359 #define VREN VRCON_bits.VREN