2 // Register Declarations for Microchip 16C620 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PCLATH_ADDR 0x000A
36 #define INTCON_ADDR 0x000B
37 #define PIR1_ADDR 0x000C
38 #define CMCON_ADDR 0x001F
39 #define OPTION_REG_ADDR 0x0081
40 #define TRISA_ADDR 0x0085
41 #define TRISB_ADDR 0x0086
42 #define PIE1_ADDR 0x008C
43 #define PCON_ADDR 0x008E
44 #define VRCON_ADDR 0x009F
47 // Memory organization.
53 // P16C620.INC Standard Header File, Version 1.01 Microchip Technology, Inc.
56 // This header file defines configurations, registers, and other useful bits of
57 // information for the PIC16C620 microcontroller. These names are taken to match
58 // the data sheets as closely as possible.
60 // Note that the processor must be selected before this file is
61 // included. The processor may be selected the following ways:
63 // 1. Command line switch:
64 // C:\ MPASM MYFILE.ASM /PIC16C620
65 // 2. LIST directive in the source file
67 // 3. Processor Type entry in the MPASM full-screen interface
69 //==========================================================================
73 //==========================================================================
77 //1.01 11/28/95 Added NOT_BOR to match revised datasheet
78 //1.00 10/31/95 Initial Release
80 //==========================================================================
84 //==========================================================================
87 // MESSG "Processor-header file mismatch. Verify selected processor."
90 //==========================================================================
92 // Register Definitions
94 //==========================================================================
99 //----- Register Files------------------------------------------------------
101 extern __data __at (INDF_ADDR) volatile char INDF;
102 extern __sfr __at (TMR0_ADDR) TMR0;
103 extern __data __at (PCL_ADDR) volatile char PCL;
104 extern __sfr __at (STATUS_ADDR) STATUS;
105 extern __sfr __at (FSR_ADDR) FSR;
106 extern __sfr __at (PORTA_ADDR) PORTA;
107 extern __sfr __at (PORTB_ADDR) PORTB;
108 extern __sfr __at (PCLATH_ADDR) PCLATH;
109 extern __sfr __at (INTCON_ADDR) INTCON;
110 extern __sfr __at (PIR1_ADDR) PIR1;
111 extern __sfr __at (CMCON_ADDR) CMCON;
113 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
114 extern __sfr __at (TRISA_ADDR) TRISA;
115 extern __sfr __at (TRISB_ADDR) TRISB;
116 extern __sfr __at (PIE1_ADDR) PIE1;
117 extern __sfr __at (PCON_ADDR) PCON;
118 extern __sfr __at (VRCON_ADDR) VRCON;
120 //----- STATUS Bits --------------------------------------------------------
123 //----- INTCON Bits --------------------------------------------------------
126 //----- PIR1 Bits ----------------------------------------------------------
129 //----- CMCON Bits ---------------------------------------------------------
132 //----- OPTION Bits --------------------------------------------------------
135 //----- PIE1 Bits ----------------------------------------------------------
138 //----- PCON Bits ----------------------------------------------------------
141 //----- VRCON Bits ---------------------------------------------------------
144 //==========================================================================
148 //==========================================================================
151 // __BADRAM H'07'-H'09', H'0D'-H'1E', H'70'-H'7F'
152 // __BADRAM H'87'-H'89', H'8D', H'8F'-H'9E'
154 //==========================================================================
156 // Configuration Bits
158 //==========================================================================
160 #define _BODEN_ON 0x3FFF
161 #define _BODEN_OFF 0x3FBF
162 #define _CP_ON 0x00CF
163 #define _CP_OFF 0x3FFF
164 #define _PWRTE_OFF 0x3FFF
165 #define _PWRTE_ON 0x3FF7
166 #define _WDT_ON 0x3FFF
167 #define _WDT_OFF 0x3FFB
168 #define _LP_OSC 0x3FFC
169 #define _XT_OSC 0x3FFD
170 #define _HS_OSC 0x3FFE
171 #define _RC_OSC 0x3FFF
175 // ----- CMCON bits --------------------
184 unsigned char C1OUT:1;
185 unsigned char C2OUT:1;
188 extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;
190 #define CM0 CMCON_bits.CM0
191 #define CM1 CMCON_bits.CM1
192 #define CM2 CMCON_bits.CM2
193 #define CIS CMCON_bits.CIS
194 #define C1OUT CMCON_bits.C1OUT
195 #define C2OUT CMCON_bits.C2OUT
197 // ----- INTCON bits --------------------
200 unsigned char RBIF:1;
201 unsigned char INTF:1;
202 unsigned char T0IF:1;
203 unsigned char RBIE:1;
204 unsigned char INTE:1;
205 unsigned char T0IE:1;
206 unsigned char PEIE:1;
210 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
212 #define RBIF INTCON_bits.RBIF
213 #define INTF INTCON_bits.INTF
214 #define T0IF INTCON_bits.T0IF
215 #define RBIE INTCON_bits.RBIE
216 #define INTE INTCON_bits.INTE
217 #define T0IE INTCON_bits.T0IE
218 #define PEIE INTCON_bits.PEIE
219 #define GIE INTCON_bits.GIE
221 // ----- OPTION_REG bits --------------------
228 unsigned char T0SE:1;
229 unsigned char T0CS:1;
230 unsigned char INTEDG:1;
231 unsigned char NOT_RBPU:1;
233 } __OPTION_REG_bits_t;
234 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
236 #define PS0 OPTION_REG_bits.PS0
237 #define PS1 OPTION_REG_bits.PS1
238 #define PS2 OPTION_REG_bits.PS2
239 #define PSA OPTION_REG_bits.PSA
240 #define T0SE OPTION_REG_bits.T0SE
241 #define T0CS OPTION_REG_bits.T0CS
242 #define INTEDG OPTION_REG_bits.INTEDG
243 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
245 // ----- PCON bits --------------------
248 unsigned char NOT_BO:1;
249 unsigned char NOT_POR:1;
258 unsigned char NOT_BOR:1;
268 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
270 #define NOT_BO PCON_bits.NOT_BO
271 #define NOT_BOR PCON_bits.NOT_BOR
272 #define NOT_POR PCON_bits.NOT_POR
274 // ----- PIE1 bits --------------------
283 unsigned char CMIE:1;
287 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
289 #define CMIE PIE1_bits.CMIE
291 // ----- PIR1 bits --------------------
300 unsigned char CMIF:1;
304 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
306 #define CMIF PIR1_bits.CMIF
308 // ----- STATUS bits --------------------
314 unsigned char NOT_PD:1;
315 unsigned char NOT_TO:1;
321 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
323 #define C STATUS_bits.C
324 #define DC STATUS_bits.DC
325 #define Z STATUS_bits.Z
326 #define NOT_PD STATUS_bits.NOT_PD
327 #define NOT_TO STATUS_bits.NOT_TO
328 #define RP0 STATUS_bits.RP0
329 #define RP1 STATUS_bits.RP1
330 #define IRP STATUS_bits.IRP
332 // ----- VRCON bits --------------------
341 unsigned char VROE:1;
342 unsigned char VREN:1;
345 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
347 #define VR0 VRCON_bits.VR0
348 #define VR1 VRCON_bits.VR1
349 #define VR2 VRCON_bits.VR2
350 #define VR3 VRCON_bits.VR3
351 #define VRR VRCON_bits.VRR
352 #define VROE VRCON_bits.VROE
353 #define VREN VRCON_bits.VREN