2 // Register Declarations for Microchip 16C620 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PCLATH_ADDR 0x000A
36 #define INTCON_ADDR 0x000B
37 #define PIR1_ADDR 0x000C
38 #define CMCON_ADDR 0x001F
39 #define OPTION_REG_ADDR 0x0081
40 #define TRISA_ADDR 0x0085
41 #define TRISB_ADDR 0x0086
42 #define PIE1_ADDR 0x008C
43 #define PCON_ADDR 0x008E
44 #define VRCON_ADDR 0x009F
47 // Memory organization.
50 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
51 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
52 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
53 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
54 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
55 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
56 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
57 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
58 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
59 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
60 #pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000 // CMCON
61 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
62 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
63 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
64 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
65 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
66 #pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON
70 // P16C620.INC Standard Header File, Version 1.01 Microchip Technology, Inc.
73 // This header file defines configurations, registers, and other useful bits of
74 // information for the PIC16C620 microcontroller. These names are taken to match
75 // the data sheets as closely as possible.
77 // Note that the processor must be selected before this file is
78 // included. The processor may be selected the following ways:
80 // 1. Command line switch:
81 // C:\ MPASM MYFILE.ASM /PIC16C620
82 // 2. LIST directive in the source file
84 // 3. Processor Type entry in the MPASM full-screen interface
86 //==========================================================================
90 //==========================================================================
94 //1.01 11/28/95 Added NOT_BOR to match revised datasheet
95 //1.00 10/31/95 Initial Release
97 //==========================================================================
101 //==========================================================================
104 // MESSG "Processor-header file mismatch. Verify selected processor."
107 //==========================================================================
109 // Register Definitions
111 //==========================================================================
116 //----- Register Files------------------------------------------------------
118 extern __data __at (INDF_ADDR) volatile char INDF;
119 extern __sfr __at (TMR0_ADDR) TMR0;
120 extern __data __at (PCL_ADDR) volatile char PCL;
121 extern __sfr __at (STATUS_ADDR) STATUS;
122 extern __sfr __at (FSR_ADDR) FSR;
123 extern __sfr __at (PORTA_ADDR) PORTA;
124 extern __sfr __at (PORTB_ADDR) PORTB;
125 extern __sfr __at (PCLATH_ADDR) PCLATH;
126 extern __sfr __at (INTCON_ADDR) INTCON;
127 extern __sfr __at (PIR1_ADDR) PIR1;
128 extern __sfr __at (CMCON_ADDR) CMCON;
130 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
131 extern __sfr __at (TRISA_ADDR) TRISA;
132 extern __sfr __at (TRISB_ADDR) TRISB;
133 extern __sfr __at (PIE1_ADDR) PIE1;
134 extern __sfr __at (PCON_ADDR) PCON;
135 extern __sfr __at (VRCON_ADDR) VRCON;
137 //----- STATUS Bits --------------------------------------------------------
140 //----- INTCON Bits --------------------------------------------------------
143 //----- PIR1 Bits ----------------------------------------------------------
146 //----- CMCON Bits ---------------------------------------------------------
149 //----- OPTION Bits --------------------------------------------------------
152 //----- PIE1 Bits ----------------------------------------------------------
155 //----- PCON Bits ----------------------------------------------------------
158 //----- VRCON Bits ---------------------------------------------------------
161 //==========================================================================
165 //==========================================================================
168 // __BADRAM H'07'-H'09', H'0D'-H'1E', H'70'-H'7F'
169 // __BADRAM H'87'-H'89', H'8D', H'8F'-H'9E'
171 //==========================================================================
173 // Configuration Bits
175 //==========================================================================
177 #define _BODEN_ON 0x3FFF
178 #define _BODEN_OFF 0x3FBF
179 #define _CP_ON 0x00CF
180 #define _CP_OFF 0x3FFF
181 #define _PWRTE_OFF 0x3FFF
182 #define _PWRTE_ON 0x3FF7
183 #define _WDT_ON 0x3FFF
184 #define _WDT_OFF 0x3FFB
185 #define _LP_OSC 0x3FFC
186 #define _XT_OSC 0x3FFD
187 #define _HS_OSC 0x3FFE
188 #define _RC_OSC 0x3FFF
192 // ----- CMCON bits --------------------
201 unsigned char C1OUT:1;
202 unsigned char C2OUT:1;
205 extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;
207 #define CM0 CMCON_bits.CM0
208 #define CM1 CMCON_bits.CM1
209 #define CM2 CMCON_bits.CM2
210 #define CIS CMCON_bits.CIS
211 #define C1OUT CMCON_bits.C1OUT
212 #define C2OUT CMCON_bits.C2OUT
214 // ----- INTCON bits --------------------
217 unsigned char RBIF:1;
218 unsigned char INTF:1;
219 unsigned char T0IF:1;
220 unsigned char RBIE:1;
221 unsigned char INTE:1;
222 unsigned char T0IE:1;
223 unsigned char PEIE:1;
227 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
229 #define RBIF INTCON_bits.RBIF
230 #define INTF INTCON_bits.INTF
231 #define T0IF INTCON_bits.T0IF
232 #define RBIE INTCON_bits.RBIE
233 #define INTE INTCON_bits.INTE
234 #define T0IE INTCON_bits.T0IE
235 #define PEIE INTCON_bits.PEIE
236 #define GIE INTCON_bits.GIE
238 // ----- OPTION_REG bits --------------------
245 unsigned char T0SE:1;
246 unsigned char T0CS:1;
247 unsigned char INTEDG:1;
248 unsigned char NOT_RBPU:1;
250 } __OPTION_REG_bits_t;
251 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
253 #define PS0 OPTION_REG_bits.PS0
254 #define PS1 OPTION_REG_bits.PS1
255 #define PS2 OPTION_REG_bits.PS2
256 #define PSA OPTION_REG_bits.PSA
257 #define T0SE OPTION_REG_bits.T0SE
258 #define T0CS OPTION_REG_bits.T0CS
259 #define INTEDG OPTION_REG_bits.INTEDG
260 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
262 // ----- PCON bits --------------------
265 unsigned char NOT_BO:1;
266 unsigned char NOT_POR:1;
275 unsigned char NOT_BOR:1;
285 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
287 #define NOT_BO PCON_bits.NOT_BO
288 #define NOT_BOR PCON_bits.NOT_BOR
289 #define NOT_POR PCON_bits.NOT_POR
291 // ----- PIE1 bits --------------------
300 unsigned char CMIE:1;
304 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
306 #define CMIE PIE1_bits.CMIE
308 // ----- PIR1 bits --------------------
317 unsigned char CMIF:1;
321 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
323 #define CMIF PIR1_bits.CMIF
325 // ----- STATUS bits --------------------
331 unsigned char NOT_PD:1;
332 unsigned char NOT_TO:1;
338 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
340 #define C STATUS_bits.C
341 #define DC STATUS_bits.DC
342 #define Z STATUS_bits.Z
343 #define NOT_PD STATUS_bits.NOT_PD
344 #define NOT_TO STATUS_bits.NOT_TO
345 #define RP0 STATUS_bits.RP0
346 #define RP1 STATUS_bits.RP1
347 #define IRP STATUS_bits.IRP
349 // ----- VRCON bits --------------------
358 unsigned char VROE:1;
359 unsigned char VREN:1;
362 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
364 #define VR0 VRCON_bits.VR0
365 #define VR1 VRCON_bits.VR1
366 #define VR2 VRCON_bits.VR2
367 #define VR3 VRCON_bits.VR3
368 #define VRR VRCON_bits.VRR
369 #define VROE VRCON_bits.VROE
370 #define VREN VRCON_bits.VREN