2 // Register Declarations for Microchip 16C62 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define TMR1L_ADDR 0x000E
40 #define TMR1H_ADDR 0x000F
41 #define T1CON_ADDR 0x0010
42 #define TMR2_ADDR 0x0011
43 #define T2CON_ADDR 0x0012
44 #define SSPBUF_ADDR 0x0013
45 #define SSPCON_ADDR 0x0014
46 #define CCPR1L_ADDR 0x0015
47 #define CCPR1H_ADDR 0x0016
48 #define CCP1CON_ADDR 0x0017
49 #define OPTION_REG_ADDR 0x0081
50 #define TRISA_ADDR 0x0085
51 #define TRISB_ADDR 0x0086
52 #define TRISC_ADDR 0x0087
53 #define PIE1_ADDR 0x008C
54 #define PCON_ADDR 0x008E
55 #define PR2_ADDR 0x0092
56 #define SSPADD_ADDR 0x0093
57 #define SSPSTAT_ADDR 0x0094
60 // Memory organization.
66 // P16C62.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
69 // This header file defines configurations, registers, and other useful bits of
70 // information for the PIC16C62 microcontroller. These names are taken to match
71 // the data sheets as closely as possible.
73 // Note that the processor must be selected before this file is
74 // included. The processor may be selected the following ways:
76 // 1. Command line switch:
77 // C:\ MPASM MYFILE.ASM /PIC16C62
78 // 2. LIST directive in the source file
80 // 3. Processor Type entry in the MPASM full-screen interface
82 //==========================================================================
86 //==========================================================================
90 //1.00 10/31/95 Initial Release
92 //==========================================================================
96 //==========================================================================
99 // MESSG "Processor-header file mismatch. Verify selected processor."
102 //==========================================================================
104 // Register Definitions
106 //==========================================================================
111 //----- Register Files------------------------------------------------------
113 extern __data __at (INDF_ADDR) volatile char INDF;
114 extern __sfr __at (TMR0_ADDR) TMR0;
115 extern __data __at (PCL_ADDR) volatile char PCL;
116 extern __sfr __at (STATUS_ADDR) STATUS;
117 extern __sfr __at (FSR_ADDR) FSR;
118 extern __sfr __at (PORTA_ADDR) PORTA;
119 extern __sfr __at (PORTB_ADDR) PORTB;
120 extern __sfr __at (PORTC_ADDR) PORTC;
121 extern __sfr __at (PCLATH_ADDR) PCLATH;
122 extern __sfr __at (INTCON_ADDR) INTCON;
123 extern __sfr __at (PIR1_ADDR) PIR1;
124 extern __sfr __at (TMR1L_ADDR) TMR1L;
125 extern __sfr __at (TMR1H_ADDR) TMR1H;
126 extern __sfr __at (T1CON_ADDR) T1CON;
127 extern __sfr __at (TMR2_ADDR) TMR2;
128 extern __sfr __at (T2CON_ADDR) T2CON;
129 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
130 extern __sfr __at (SSPCON_ADDR) SSPCON;
131 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
132 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
133 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
135 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
136 extern __sfr __at (TRISA_ADDR) TRISA;
137 extern __sfr __at (TRISB_ADDR) TRISB;
138 extern __sfr __at (TRISC_ADDR) TRISC;
139 extern __sfr __at (PIE1_ADDR) PIE1;
140 extern __sfr __at (PCON_ADDR) PCON;
141 extern __sfr __at (PR2_ADDR) PR2;
142 extern __sfr __at (SSPADD_ADDR) SSPADD;
143 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
145 //----- STATUS Bits --------------------------------------------------------
148 //----- INTCON Bits --------------------------------------------------------
151 //----- PIR1 Bits ----------------------------------------------------------
154 //----- T1CON Bits ---------------------------------------------------------
157 //----- T2CON Bits ---------------------------------------------------------
160 //----- SSPCON Bits --------------------------------------------------------
163 //----- CCP1CON Bits -------------------------------------------------------
166 //----- OPTION Bits --------------------------------------------------------
169 //----- PIE1 Bits ----------------------------------------------------------
172 //----- PCON Bits ----------------------------------------------------------
175 //----- SSPSTAT Bits -------------------------------------------------------
178 //==========================================================================
182 //==========================================================================
185 // __BADRAM H'08'-H'09', H'0D', H'18'-H'1F'
186 // __BADRAM H'88'-H'89', H'8D', H'8F'-H'91',H'95'-H'9F'
188 //==========================================================================
190 // Configuration Bits
192 //==========================================================================
194 #define _CP_ALL 0x3F8F
195 #define _CP_75 0x3F9F
196 #define _CP_50 0x3FAF
197 #define _CP_OFF 0x3FBF
198 #define _PWRTE_ON 0x3FBF
199 #define _PWRTE_OFF 0x3FB7
200 #define _WDT_ON 0x3FBF
201 #define _WDT_OFF 0x3FBB
202 #define _LP_OSC 0x3FBC
203 #define _XT_OSC 0x3FBD
204 #define _HS_OSC 0x3FBE
205 #define _RC_OSC 0x3FBF
209 // ----- CCP1CON bits --------------------
212 unsigned char CCP1M0:1;
213 unsigned char CCP1M1:1;
214 unsigned char CCP1M2:1;
215 unsigned char CCP1M3:1;
216 unsigned char CCP1Y:1;
217 unsigned char CCP1X:1;
222 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
224 #define CCP1M0 CCP1CON_bits.CCP1M0
225 #define CCP1M1 CCP1CON_bits.CCP1M1
226 #define CCP1M2 CCP1CON_bits.CCP1M2
227 #define CCP1M3 CCP1CON_bits.CCP1M3
228 #define CCP1Y CCP1CON_bits.CCP1Y
229 #define CCP1X CCP1CON_bits.CCP1X
231 // ----- INTCON bits --------------------
234 unsigned char RBIF:1;
235 unsigned char INTF:1;
236 unsigned char T0IF:1;
237 unsigned char RBIE:1;
238 unsigned char INTE:1;
239 unsigned char T0IE:1;
240 unsigned char PEIE:1;
244 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
246 #define RBIF INTCON_bits.RBIF
247 #define INTF INTCON_bits.INTF
248 #define T0IF INTCON_bits.T0IF
249 #define RBIE INTCON_bits.RBIE
250 #define INTE INTCON_bits.INTE
251 #define T0IE INTCON_bits.T0IE
252 #define PEIE INTCON_bits.PEIE
253 #define GIE INTCON_bits.GIE
255 // ----- OPTION_REG bits --------------------
262 unsigned char T0SE:1;
263 unsigned char T0CS:1;
264 unsigned char INTEDG:1;
265 unsigned char NOT_RBPU:1;
267 } __OPTION_REG_bits_t;
268 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
270 #define PS0 OPTION_REG_bits.PS0
271 #define PS1 OPTION_REG_bits.PS1
272 #define PS2 OPTION_REG_bits.PS2
273 #define PSA OPTION_REG_bits.PSA
274 #define T0SE OPTION_REG_bits.T0SE
275 #define T0CS OPTION_REG_bits.T0CS
276 #define INTEDG OPTION_REG_bits.INTEDG
277 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
279 // ----- PCON bits --------------------
283 unsigned char NOT_POR:1;
292 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
294 #define NOT_POR PCON_bits.NOT_POR
296 // ----- PIE1 bits --------------------
299 unsigned char TMR1IE:1;
300 unsigned char TMR2IE:1;
301 unsigned char CCP1IE:1;
302 unsigned char SSPIE:1;
309 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
311 #define TMR1IE PIE1_bits.TMR1IE
312 #define TMR2IE PIE1_bits.TMR2IE
313 #define CCP1IE PIE1_bits.CCP1IE
314 #define SSPIE PIE1_bits.SSPIE
316 // ----- PIR1 bits --------------------
319 unsigned char TMR1IF:1;
320 unsigned char TMR2IF:1;
321 unsigned char CCP1IF:1;
322 unsigned char SSPIF:1;
329 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
331 #define TMR1IF PIR1_bits.TMR1IF
332 #define TMR2IF PIR1_bits.TMR2IF
333 #define CCP1IF PIR1_bits.CCP1IF
334 #define SSPIF PIR1_bits.SSPIF
336 // ----- SSPCON bits --------------------
339 unsigned char SSPM0:1;
340 unsigned char SSPM1:1;
341 unsigned char SSPM2:1;
342 unsigned char SSPM3:1;
344 unsigned char SSPEN:1;
345 unsigned char SSPOV:1;
346 unsigned char WCOL:1;
349 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
351 #define SSPM0 SSPCON_bits.SSPM0
352 #define SSPM1 SSPCON_bits.SSPM1
353 #define SSPM2 SSPCON_bits.SSPM2
354 #define SSPM3 SSPCON_bits.SSPM3
355 #define CKP SSPCON_bits.CKP
356 #define SSPEN SSPCON_bits.SSPEN
357 #define SSPOV SSPCON_bits.SSPOV
358 #define WCOL SSPCON_bits.WCOL
360 // ----- SSPSTAT bits --------------------
375 unsigned char I2C_READ:1;
376 unsigned char I2C_START:1;
377 unsigned char I2C_STOP:1;
378 unsigned char I2C_DATA:1;
385 unsigned char NOT_W:1;
388 unsigned char NOT_A:1;
395 unsigned char NOT_WRITE:1;
398 unsigned char NOT_ADDRESS:1;
415 unsigned char READ_WRITE:1;
418 unsigned char DATA_ADDRESS:1;
423 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
425 #define BF SSPSTAT_bits.BF
426 #define UA SSPSTAT_bits.UA
427 #define R SSPSTAT_bits.R
428 #define I2C_READ SSPSTAT_bits.I2C_READ
429 #define NOT_W SSPSTAT_bits.NOT_W
430 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
431 #define R_W SSPSTAT_bits.R_W
432 #define READ_WRITE SSPSTAT_bits.READ_WRITE
433 #define S SSPSTAT_bits.S
434 #define I2C_START SSPSTAT_bits.I2C_START
435 #define P SSPSTAT_bits.P
436 #define I2C_STOP SSPSTAT_bits.I2C_STOP
437 #define D SSPSTAT_bits.D
438 #define I2C_DATA SSPSTAT_bits.I2C_DATA
439 #define NOT_A SSPSTAT_bits.NOT_A
440 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
441 #define D_A SSPSTAT_bits.D_A
442 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
444 // ----- STATUS bits --------------------
450 unsigned char NOT_PD:1;
451 unsigned char NOT_TO:1;
457 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
459 #define C STATUS_bits.C
460 #define DC STATUS_bits.DC
461 #define Z STATUS_bits.Z
462 #define NOT_PD STATUS_bits.NOT_PD
463 #define NOT_TO STATUS_bits.NOT_TO
464 #define RP0 STATUS_bits.RP0
465 #define RP1 STATUS_bits.RP1
466 #define IRP STATUS_bits.IRP
468 // ----- T1CON bits --------------------
471 unsigned char TMR1ON:1;
472 unsigned char TMR1CS:1;
473 unsigned char NOT_T1SYNC:1;
474 unsigned char T1OSCEN:1;
475 unsigned char T1CKPS0:1;
476 unsigned char T1CKPS1:1;
483 unsigned char T1INSYNC:1;
491 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
493 #define TMR1ON T1CON_bits.TMR1ON
494 #define TMR1CS T1CON_bits.TMR1CS
495 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
496 #define T1INSYNC T1CON_bits.T1INSYNC
497 #define T1OSCEN T1CON_bits.T1OSCEN
498 #define T1CKPS0 T1CON_bits.T1CKPS0
499 #define T1CKPS1 T1CON_bits.T1CKPS1
501 // ----- T2CON bits --------------------
504 unsigned char T2CKPS0:1;
505 unsigned char T2CKPS1:1;
506 unsigned char TMR2ON:1;
507 unsigned char TOUTPS0:1;
508 unsigned char TOUTPS1:1;
509 unsigned char TOUTPS2:1;
510 unsigned char TOUTPS3:1;
514 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
516 #define T2CKPS0 T2CON_bits.T2CKPS0
517 #define T2CKPS1 T2CON_bits.T2CKPS1
518 #define TMR2ON T2CON_bits.TMR2ON
519 #define TOUTPS0 T2CON_bits.TOUTPS0
520 #define TOUTPS1 T2CON_bits.TOUTPS1
521 #define TOUTPS2 T2CON_bits.TOUTPS2
522 #define TOUTPS3 T2CON_bits.TOUTPS3