2 // Register Declarations for Microchip 16C62 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define TMR1L_ADDR 0x000E
40 #define TMR1H_ADDR 0x000F
41 #define T1CON_ADDR 0x0010
42 #define TMR2_ADDR 0x0011
43 #define T2CON_ADDR 0x0012
44 #define SSPBUF_ADDR 0x0013
45 #define SSPCON_ADDR 0x0014
46 #define CCPR1L_ADDR 0x0015
47 #define CCPR1H_ADDR 0x0016
48 #define CCP1CON_ADDR 0x0017
49 #define OPTION_REG_ADDR 0x0081
50 #define TRISA_ADDR 0x0085
51 #define TRISB_ADDR 0x0086
52 #define TRISC_ADDR 0x0087
53 #define PIE1_ADDR 0x008C
54 #define PCON_ADDR 0x008E
55 #define PR2_ADDR 0x0092
56 #define SSPADD_ADDR 0x0093
57 #define SSPSTAT_ADDR 0x0094
60 // Memory organization.
63 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
64 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
65 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
66 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
67 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
68 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
69 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
70 #pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
71 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
72 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
73 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
74 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
75 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
76 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
77 #pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
78 #pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
79 #pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF
80 #pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON
81 #pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
82 #pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
83 #pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
84 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
85 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
86 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
87 #pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
88 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
89 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
90 #pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
91 #pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD
92 #pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT
96 // P16C62.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
99 // This header file defines configurations, registers, and other useful bits of
100 // information for the PIC16C62 microcontroller. These names are taken to match
101 // the data sheets as closely as possible.
103 // Note that the processor must be selected before this file is
104 // included. The processor may be selected the following ways:
106 // 1. Command line switch:
107 // C:\ MPASM MYFILE.ASM /PIC16C62
108 // 2. LIST directive in the source file
110 // 3. Processor Type entry in the MPASM full-screen interface
112 //==========================================================================
116 //==========================================================================
120 //1.00 10/31/95 Initial Release
122 //==========================================================================
126 //==========================================================================
129 // MESSG "Processor-header file mismatch. Verify selected processor."
132 //==========================================================================
134 // Register Definitions
136 //==========================================================================
141 //----- Register Files------------------------------------------------------
143 extern data __at (INDF_ADDR) volatile char INDF;
144 extern sfr __at (TMR0_ADDR) TMR0;
145 extern data __at (PCL_ADDR) volatile char PCL;
146 extern sfr __at (STATUS_ADDR) STATUS;
147 extern sfr __at (FSR_ADDR) FSR;
148 extern sfr __at (PORTA_ADDR) PORTA;
149 extern sfr __at (PORTB_ADDR) PORTB;
150 extern sfr __at (PORTC_ADDR) PORTC;
151 extern sfr __at (PCLATH_ADDR) PCLATH;
152 extern sfr __at (INTCON_ADDR) INTCON;
153 extern sfr __at (PIR1_ADDR) PIR1;
154 extern sfr __at (TMR1L_ADDR) TMR1L;
155 extern sfr __at (TMR1H_ADDR) TMR1H;
156 extern sfr __at (T1CON_ADDR) T1CON;
157 extern sfr __at (TMR2_ADDR) TMR2;
158 extern sfr __at (T2CON_ADDR) T2CON;
159 extern sfr __at (SSPBUF_ADDR) SSPBUF;
160 extern sfr __at (SSPCON_ADDR) SSPCON;
161 extern sfr __at (CCPR1L_ADDR) CCPR1L;
162 extern sfr __at (CCPR1H_ADDR) CCPR1H;
163 extern sfr __at (CCP1CON_ADDR) CCP1CON;
165 extern sfr __at (OPTION_REG_ADDR) OPTION_REG;
166 extern sfr __at (TRISA_ADDR) TRISA;
167 extern sfr __at (TRISB_ADDR) TRISB;
168 extern sfr __at (TRISC_ADDR) TRISC;
169 extern sfr __at (PIE1_ADDR) PIE1;
170 extern sfr __at (PCON_ADDR) PCON;
171 extern sfr __at (PR2_ADDR) PR2;
172 extern sfr __at (SSPADD_ADDR) SSPADD;
173 extern sfr __at (SSPSTAT_ADDR) SSPSTAT;
175 //----- STATUS Bits --------------------------------------------------------
178 //----- INTCON Bits --------------------------------------------------------
181 //----- PIR1 Bits ----------------------------------------------------------
184 //----- T1CON Bits ---------------------------------------------------------
187 //----- T2CON Bits ---------------------------------------------------------
190 //----- SSPCON Bits --------------------------------------------------------
193 //----- CCP1CON Bits -------------------------------------------------------
196 //----- OPTION Bits --------------------------------------------------------
199 //----- PIE1 Bits ----------------------------------------------------------
202 //----- PCON Bits ----------------------------------------------------------
205 //----- SSPSTAT Bits -------------------------------------------------------
208 //==========================================================================
212 //==========================================================================
215 // __BADRAM H'08'-H'09', H'0D', H'18'-H'1F'
216 // __BADRAM H'88'-H'89', H'8D', H'8F'-H'91',H'95'-H'9F'
218 //==========================================================================
220 // Configuration Bits
222 //==========================================================================
224 #define _CP_ALL 0x3F8F
225 #define _CP_75 0x3F9F
226 #define _CP_50 0x3FAF
227 #define _CP_OFF 0x3FBF
228 #define _PWRTE_ON 0x3FBF
229 #define _PWRTE_OFF 0x3FB7
230 #define _WDT_ON 0x3FBF
231 #define _WDT_OFF 0x3FBB
232 #define _LP_OSC 0x3FBC
233 #define _XT_OSC 0x3FBD
234 #define _HS_OSC 0x3FBE
235 #define _RC_OSC 0x3FBF
239 // ----- CCP1CON bits --------------------
242 unsigned char CCP1M0:1;
243 unsigned char CCP1M1:1;
244 unsigned char CCP1M2:1;
245 unsigned char CCP1M3:1;
246 unsigned char CCP1Y:1;
247 unsigned char CCP1X:1;
252 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
254 #define CCP1M0 CCP1CON_bits.CCP1M0
255 #define CCP1M1 CCP1CON_bits.CCP1M1
256 #define CCP1M2 CCP1CON_bits.CCP1M2
257 #define CCP1M3 CCP1CON_bits.CCP1M3
258 #define CCP1Y CCP1CON_bits.CCP1Y
259 #define CCP1X CCP1CON_bits.CCP1X
261 // ----- INTCON bits --------------------
264 unsigned char RBIF:1;
265 unsigned char INTF:1;
266 unsigned char T0IF:1;
267 unsigned char RBIE:1;
268 unsigned char INTE:1;
269 unsigned char T0IE:1;
270 unsigned char PEIE:1;
274 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
276 #define RBIF INTCON_bits.RBIF
277 #define INTF INTCON_bits.INTF
278 #define T0IF INTCON_bits.T0IF
279 #define RBIE INTCON_bits.RBIE
280 #define INTE INTCON_bits.INTE
281 #define T0IE INTCON_bits.T0IE
282 #define PEIE INTCON_bits.PEIE
283 #define GIE INTCON_bits.GIE
285 // ----- OPTION_REG bits --------------------
292 unsigned char T0SE:1;
293 unsigned char T0CS:1;
294 unsigned char INTEDG:1;
295 unsigned char NOT_RBPU:1;
297 } __OPTION_REG_bits_t;
298 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
300 #define PS0 OPTION_REG_bits.PS0
301 #define PS1 OPTION_REG_bits.PS1
302 #define PS2 OPTION_REG_bits.PS2
303 #define PSA OPTION_REG_bits.PSA
304 #define T0SE OPTION_REG_bits.T0SE
305 #define T0CS OPTION_REG_bits.T0CS
306 #define INTEDG OPTION_REG_bits.INTEDG
307 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
309 // ----- PCON bits --------------------
313 unsigned char NOT_POR:1;
322 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
324 #define NOT_POR PCON_bits.NOT_POR
326 // ----- PIE1 bits --------------------
329 unsigned char TMR1IE:1;
330 unsigned char TMR2IE:1;
331 unsigned char CCP1IE:1;
332 unsigned char SSPIE:1;
339 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
341 #define TMR1IE PIE1_bits.TMR1IE
342 #define TMR2IE PIE1_bits.TMR2IE
343 #define CCP1IE PIE1_bits.CCP1IE
344 #define SSPIE PIE1_bits.SSPIE
346 // ----- PIR1 bits --------------------
349 unsigned char TMR1IF:1;
350 unsigned char TMR2IF:1;
351 unsigned char CCP1IF:1;
352 unsigned char SSPIF:1;
359 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
361 #define TMR1IF PIR1_bits.TMR1IF
362 #define TMR2IF PIR1_bits.TMR2IF
363 #define CCP1IF PIR1_bits.CCP1IF
364 #define SSPIF PIR1_bits.SSPIF
366 // ----- SSPCON bits --------------------
369 unsigned char SSPM0:1;
370 unsigned char SSPM1:1;
371 unsigned char SSPM2:1;
372 unsigned char SSPM3:1;
374 unsigned char SSPEN:1;
375 unsigned char SSPOV:1;
376 unsigned char WCOL:1;
379 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
381 #define SSPM0 SSPCON_bits.SSPM0
382 #define SSPM1 SSPCON_bits.SSPM1
383 #define SSPM2 SSPCON_bits.SSPM2
384 #define SSPM3 SSPCON_bits.SSPM3
385 #define CKP SSPCON_bits.CKP
386 #define SSPEN SSPCON_bits.SSPEN
387 #define SSPOV SSPCON_bits.SSPOV
388 #define WCOL SSPCON_bits.WCOL
390 // ----- SSPSTAT bits --------------------
405 unsigned char I2C_READ:1;
406 unsigned char I2C_START:1;
407 unsigned char I2C_STOP:1;
408 unsigned char I2C_DATA:1;
415 unsigned char NOT_W:1;
418 unsigned char NOT_A:1;
425 unsigned char NOT_WRITE:1;
428 unsigned char NOT_ADDRESS:1;
445 unsigned char READ_WRITE:1;
448 unsigned char DATA_ADDRESS:1;
453 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
455 #define BF SSPSTAT_bits.BF
456 #define UA SSPSTAT_bits.UA
457 #define R SSPSTAT_bits.R
458 #define I2C_READ SSPSTAT_bits.I2C_READ
459 #define NOT_W SSPSTAT_bits.NOT_W
460 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
461 #define R_W SSPSTAT_bits.R_W
462 #define READ_WRITE SSPSTAT_bits.READ_WRITE
463 #define S SSPSTAT_bits.S
464 #define I2C_START SSPSTAT_bits.I2C_START
465 #define P SSPSTAT_bits.P
466 #define I2C_STOP SSPSTAT_bits.I2C_STOP
467 #define D SSPSTAT_bits.D
468 #define I2C_DATA SSPSTAT_bits.I2C_DATA
469 #define NOT_A SSPSTAT_bits.NOT_A
470 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
471 #define D_A SSPSTAT_bits.D_A
472 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
474 // ----- STATUS bits --------------------
480 unsigned char NOT_PD:1;
481 unsigned char NOT_TO:1;
487 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
489 #define C STATUS_bits.C
490 #define DC STATUS_bits.DC
491 #define Z STATUS_bits.Z
492 #define NOT_PD STATUS_bits.NOT_PD
493 #define NOT_TO STATUS_bits.NOT_TO
494 #define RP0 STATUS_bits.RP0
495 #define RP1 STATUS_bits.RP1
496 #define IRP STATUS_bits.IRP
498 // ----- T1CON bits --------------------
501 unsigned char TMR1ON:1;
502 unsigned char TMR1CS:1;
503 unsigned char NOT_T1SYNC:1;
504 unsigned char T1OSCEN:1;
505 unsigned char T1CKPS0:1;
506 unsigned char T1CKPS1:1;
513 unsigned char T1INSYNC:1;
521 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
523 #define TMR1ON T1CON_bits.TMR1ON
524 #define TMR1CS T1CON_bits.TMR1CS
525 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
526 #define T1INSYNC T1CON_bits.T1INSYNC
527 #define T1OSCEN T1CON_bits.T1OSCEN
528 #define T1CKPS0 T1CON_bits.T1CKPS0
529 #define T1CKPS1 T1CON_bits.T1CKPS1
531 // ----- T2CON bits --------------------
534 unsigned char T2CKPS0:1;
535 unsigned char T2CKPS1:1;
536 unsigned char TMR2ON:1;
537 unsigned char TOUTPS0:1;
538 unsigned char TOUTPS1:1;
539 unsigned char TOUTPS2:1;
540 unsigned char TOUTPS3:1;
544 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
546 #define T2CKPS0 T2CON_bits.T2CKPS0
547 #define T2CKPS1 T2CON_bits.T2CKPS1
548 #define TMR2ON T2CON_bits.TMR2ON
549 #define TOUTPS0 T2CON_bits.TOUTPS0
550 #define TOUTPS1 T2CON_bits.TOUTPS1
551 #define TOUTPS2 T2CON_bits.TOUTPS2
552 #define TOUTPS3 T2CON_bits.TOUTPS3