2 // Register Declarations for Microchip 16C558 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PCLATH_ADDR 0x000A
36 #define INTCON_ADDR 0x000B
37 #define OPTION_REG_ADDR 0x0081
38 #define TRISA_ADDR 0x0085
39 #define TRISB_ADDR 0x0086
40 #define PCON_ADDR 0x008E
43 // Memory organization.
49 // P16C558.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
52 // This header file defines configurations, registers, and other useful bits of
53 // information for the PIC16C558 microcontroller. These names are taken to match
54 // the data sheets as closely as possible.
56 // Note that the processor must be selected before this file is
57 // included. The processor may be selected the following ways:
59 // 1. Command line switch:
60 // C:\ MPASM MYFILE.ASM /PIC16C558
61 // 2. LIST directive in the source file
63 // 3. Processor Type entry in the MPASM full-screen interface
65 //==========================================================================
69 //==========================================================================
73 //1.00 04/22/96 Initial Creation
75 //==========================================================================
79 //==========================================================================
82 // MESSG "Processor-header file mismatch. Verify selected processor."
85 //==========================================================================
87 // Register Definitions
89 //==========================================================================
94 //----- Register Files------------------------------------------------------
96 extern __data __at (INDF_ADDR) volatile char INDF;
97 extern __sfr __at (TMR0_ADDR) TMR0;
98 extern __data __at (PCL_ADDR) volatile char PCL;
99 extern __sfr __at (STATUS_ADDR) STATUS;
100 extern __sfr __at (FSR_ADDR) FSR;
101 extern __sfr __at (PORTA_ADDR) PORTA;
102 extern __sfr __at (PORTB_ADDR) PORTB;
103 extern __sfr __at (PCLATH_ADDR) PCLATH;
104 extern __sfr __at (INTCON_ADDR) INTCON;
106 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
107 extern __sfr __at (TRISA_ADDR) TRISA;
108 extern __sfr __at (TRISB_ADDR) TRISB;
109 extern __sfr __at (PCON_ADDR) PCON;
111 //----- STATUS Bits --------------------------------------------------------
114 //----- INTCON Bits --------------------------------------------------------
117 //----- OPTION Bits --------------------------------------------------------
120 //----- PCON Bits ----------------------------------------------------------
123 //==========================================================================
127 //==========================================================================
130 // __BADRAM H'07'-H'09', H'0C'-H'1F'
131 // __BADRAM H'87'-H'89', H'8C'-H'8D', H'8F'-H'9F'
133 //==========================================================================
135 // Configuration Bits
137 //==========================================================================
139 #define _CP_ALL 0x00CF
140 #define _CP_75 0x15DF
141 #define _CP_50 0x2AEF
142 #define _CP_OFF 0x3FFF
143 #define _PWRTE_OFF 0x3FFF
144 #define _PWRTE_ON 0x3FF7
145 #define _WDT_ON 0x3FFF
146 #define _WDT_OFF 0x3FFB
147 #define _LP_OSC 0x3FFC
148 #define _XT_OSC 0x3FFD
149 #define _HS_OSC 0x3FFE
150 #define _RC_OSC 0x3FFF
154 // ----- INTCON bits --------------------
157 unsigned char RBIF:1;
158 unsigned char INTF:1;
159 unsigned char T0IF:1;
160 unsigned char RBIE:1;
161 unsigned char INTE:1;
162 unsigned char T0IE:1;
167 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
169 #define RBIF INTCON_bits.RBIF
170 #define INTF INTCON_bits.INTF
171 #define T0IF INTCON_bits.T0IF
172 #define RBIE INTCON_bits.RBIE
173 #define INTE INTCON_bits.INTE
174 #define T0IE INTCON_bits.T0IE
175 #define GIE INTCON_bits.GIE
177 // ----- OPTION_REG bits --------------------
184 unsigned char T0SE:1;
185 unsigned char T0CS:1;
186 unsigned char INTEDG:1;
187 unsigned char NOT_RBPU:1;
189 } __OPTION_REG_bits_t;
190 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
192 #define PS0 OPTION_REG_bits.PS0
193 #define PS1 OPTION_REG_bits.PS1
194 #define PS2 OPTION_REG_bits.PS2
195 #define PSA OPTION_REG_bits.PSA
196 #define T0SE OPTION_REG_bits.T0SE
197 #define T0CS OPTION_REG_bits.T0CS
198 #define INTEDG OPTION_REG_bits.INTEDG
199 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
201 // ----- PCON bits --------------------
205 unsigned char NOT_POR:1;
214 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
216 #define NOT_POR PCON_bits.NOT_POR
218 // ----- PORTA bits --------------------
231 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
233 #define RA0 PORTA_bits.RA0
234 #define RA1 PORTA_bits.RA1
235 #define RA2 PORTA_bits.RA2
236 #define RA3 PORTA_bits.RA3
237 #define RA4 PORTA_bits.RA4
238 #define RA5 PORTA_bits.RA5
240 // ----- PORTB bits --------------------
253 extern volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
255 #define RB0 PORTB_bits.RB0
256 #define RB1 PORTB_bits.RB1
257 #define RB2 PORTB_bits.RB2
258 #define RB3 PORTB_bits.RB3
259 #define RB4 PORTB_bits.RB4
260 #define RB5 PORTB_bits.RB5
261 #define RB6 PORTB_bits.RB6
262 #define RB7 PORTB_bits.RB7
264 // ----- STATUS bits --------------------
270 unsigned char NOT_PD:1;
271 unsigned char NOT_TO:1;
277 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
279 #define C STATUS_bits.C
280 #define DC STATUS_bits.DC
281 #define Z STATUS_bits.Z
282 #define NOT_PD STATUS_bits.NOT_PD
283 #define NOT_TO STATUS_bits.NOT_TO
284 #define RP0 STATUS_bits.RP0
285 #define RP1 STATUS_bits.RP1
286 #define IRP STATUS_bits.IRP
288 // ----- TRISA bits --------------------
291 unsigned char TRISA0:1;
292 unsigned char TRISA1:1;
293 unsigned char TRISA2:1;
294 unsigned char TRISA3:1;
295 unsigned char TRISA4:1;
296 unsigned char TRISA5:1;
301 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
303 #define TRISA0 TRISA_bits.TRISA0
304 #define TRISA1 TRISA_bits.TRISA1
305 #define TRISA2 TRISA_bits.TRISA2
306 #define TRISA3 TRISA_bits.TRISA3
307 #define TRISA4 TRISA_bits.TRISA4
308 #define TRISA5 TRISA_bits.TRISA5
310 // ----- TRISB bits --------------------
313 unsigned char TRISB0:1;
314 unsigned char TRISB1:1;
315 unsigned char TRISB2:1;
316 unsigned char TRISB3:1;
317 unsigned char TRISB4:1;
318 unsigned char TRISB5:1;
319 unsigned char TRISB6:1;
320 unsigned char TRISB7:1;
323 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
325 #define TRISB0 TRISB_bits.TRISB0
326 #define TRISB1 TRISB_bits.TRISB1
327 #define TRISB2 TRISB_bits.TRISB2
328 #define TRISB3 TRISB_bits.TRISB3
329 #define TRISB4 TRISB_bits.TRISB4
330 #define TRISB5 TRISB_bits.TRISB5
331 #define TRISB6 TRISB_bits.TRISB6
332 #define TRISB7 TRISB_bits.TRISB7