2 // Register Declarations for Microchip 16C557 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define OPTION_REG_ADDR 0x0081
39 #define TRISA_ADDR 0x0085
40 #define TRISB_ADDR 0x0086
41 #define TRISC_ADDR 0x0087
42 #define PCON_ADDR 0x008E
45 // Memory organization.
51 // P16C557.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
54 // This header file defines configurations, registers, and other useful bits of
55 // information for the PIC16C557 microcontroller. These names are taken to match
56 // the data sheets as closely as possible.
58 // Note that the processor must be selected before this file is
59 // included. The processor may be selected the following ways:
61 // 1. Command line switch:
62 // C:\ MPASM MYFILE.ASM /p=16C557
63 // 2. LIST directive in the source file
65 // 3. Processor Type entry in the MPASM full-screen interface
67 //==========================================================================
71 //==========================================================================
75 //1.00 08/29/01 Initial Release
77 //==========================================================================
81 //==========================================================================
84 // MESSG "Processor-header file mismatch. Verify selected processor."
87 //==========================================================================
89 // Register Definitions
91 //==========================================================================
96 //----- Register Files------------------------------------------------------
98 extern __data __at (INDF_ADDR) volatile char INDF;
99 extern __sfr __at (TMR0_ADDR) TMR0;
100 extern __data __at (PCL_ADDR) volatile char PCL;
101 extern __sfr __at (STATUS_ADDR) STATUS;
102 extern __sfr __at (FSR_ADDR) FSR;
103 extern __sfr __at (PORTA_ADDR) PORTA;
104 extern __sfr __at (PORTB_ADDR) PORTB;
105 extern __sfr __at (PORTC_ADDR) PORTC;
106 extern __sfr __at (PCLATH_ADDR) PCLATH;
107 extern __sfr __at (INTCON_ADDR) INTCON;
109 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
110 extern __sfr __at (TRISA_ADDR) TRISA;
111 extern __sfr __at (TRISB_ADDR) TRISB;
112 extern __sfr __at (TRISC_ADDR) TRISC;
113 extern __sfr __at (PCON_ADDR) PCON;
115 //----- STATUS Bits --------------------------------------------------------
118 //----- INTCON Bits --------------------------------------------------------
121 //----- OPTION Bits --------------------------------------------------------
124 //----- PCON Bits ----------------------------------------------------------
127 //==========================================================================
131 //==========================================================================
134 // __BADRAM H'08'-H'09', H'0C'-H'1F'
135 // __BADRAM H'88'-H'89', H'8C'-H'8D', H'8F'-H'9F', H'C0'-H'EF'
137 //==========================================================================
139 // Configuration Bits
141 //==========================================================================
143 #define _CP_ALL 0x00CF
144 #define _CP_75 0x15DF
145 #define _CP_50 0x2AEF
146 #define _CP_OFF 0x3FFF
147 #define _PWRTE_OFF 0x3FFF
148 #define _PWRTE_ON 0x3FF7
149 #define _WDT_ON 0x3FFF
150 #define _WDT_OFF 0x3FFB
151 #define _LP_OSC 0x3FFC
152 #define _XT_OSC 0x3FFD
153 #define _HS_OSC 0x3FFE
154 #define _RC_OSC 0x3FFF
158 // ----- INTCON bits --------------------
161 unsigned char RBIF:1;
162 unsigned char INTF:1;
163 unsigned char T0IF:1;
164 unsigned char RBIE:1;
165 unsigned char INTE:1;
166 unsigned char T0IE:1;
171 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
173 #define RBIF INTCON_bits.RBIF
174 #define INTF INTCON_bits.INTF
175 #define T0IF INTCON_bits.T0IF
176 #define RBIE INTCON_bits.RBIE
177 #define INTE INTCON_bits.INTE
178 #define T0IE INTCON_bits.T0IE
179 #define GIE INTCON_bits.GIE
181 // ----- OPTION_REG bits --------------------
188 unsigned char T0SE:1;
189 unsigned char T0CS:1;
190 unsigned char INTEDG:1;
191 unsigned char NOT_RBPU:1;
193 } __OPTION_REG_bits_t;
194 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
196 #define PS0 OPTION_REG_bits.PS0
197 #define PS1 OPTION_REG_bits.PS1
198 #define PS2 OPTION_REG_bits.PS2
199 #define PSA OPTION_REG_bits.PSA
200 #define T0SE OPTION_REG_bits.T0SE
201 #define T0CS OPTION_REG_bits.T0CS
202 #define INTEDG OPTION_REG_bits.INTEDG
203 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
205 // ----- PCON bits --------------------
209 unsigned char NOT_POR:1;
218 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
220 #define NOT_POR PCON_bits.NOT_POR
222 // ----- STATUS bits --------------------
228 unsigned char NOT_PD:1;
229 unsigned char NOT_TO:1;
235 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
237 #define C STATUS_bits.C
238 #define DC STATUS_bits.DC
239 #define Z STATUS_bits.Z
240 #define NOT_PD STATUS_bits.NOT_PD
241 #define NOT_TO STATUS_bits.NOT_TO
242 #define RP0 STATUS_bits.RP0
243 #define RP1 STATUS_bits.RP1
244 #define IRP STATUS_bits.IRP