2 // Register Declarations for Microchip 16C557 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define OPTION_REG_ADDR 0x0081
39 #define TRISA_ADDR 0x0085
40 #define TRISB_ADDR 0x0086
41 #define TRISC_ADDR 0x0087
42 #define PCON_ADDR 0x008E
45 // Memory organization.
48 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
49 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
50 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
51 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
52 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
53 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
54 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
55 #pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
56 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
57 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
58 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
59 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
60 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
61 #pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
62 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
66 // P16C557.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
69 // This header file defines configurations, registers, and other useful bits of
70 // information for the PIC16C557 microcontroller. These names are taken to match
71 // the data sheets as closely as possible.
73 // Note that the processor must be selected before this file is
74 // included. The processor may be selected the following ways:
76 // 1. Command line switch:
77 // C:\ MPASM MYFILE.ASM /p=16C557
78 // 2. LIST directive in the source file
80 // 3. Processor Type entry in the MPASM full-screen interface
82 //==========================================================================
86 //==========================================================================
90 //1.00 08/29/01 Initial Release
92 //==========================================================================
96 //==========================================================================
99 // MESSG "Processor-header file mismatch. Verify selected processor."
102 //==========================================================================
104 // Register Definitions
106 //==========================================================================
111 //----- Register Files------------------------------------------------------
113 extern data __at (INDF_ADDR) volatile char INDF;
114 extern sfr __at (TMR0_ADDR) TMR0;
115 extern data __at (PCL_ADDR) volatile char PCL;
116 extern sfr __at (STATUS_ADDR) STATUS;
117 extern sfr __at (FSR_ADDR) FSR;
118 extern sfr __at (PORTA_ADDR) PORTA;
119 extern sfr __at (PORTB_ADDR) PORTB;
120 extern sfr __at (PORTC_ADDR) PORTC;
121 extern sfr __at (PCLATH_ADDR) PCLATH;
122 extern sfr __at (INTCON_ADDR) INTCON;
124 extern sfr __at (OPTION_REG_ADDR) OPTION_REG;
125 extern sfr __at (TRISA_ADDR) TRISA;
126 extern sfr __at (TRISB_ADDR) TRISB;
127 extern sfr __at (TRISC_ADDR) TRISC;
128 extern sfr __at (PCON_ADDR) PCON;
130 //----- STATUS Bits --------------------------------------------------------
133 //----- INTCON Bits --------------------------------------------------------
136 //----- OPTION Bits --------------------------------------------------------
139 //----- PCON Bits ----------------------------------------------------------
142 //==========================================================================
146 //==========================================================================
149 // __BADRAM H'08'-H'09', H'0C'-H'1F'
150 // __BADRAM H'88'-H'89', H'8C'-H'8D', H'8F'-H'9F', H'C0'-H'EF'
152 //==========================================================================
154 // Configuration Bits
156 //==========================================================================
158 #define _CP_ALL 0x00CF
159 #define _CP_75 0x15DF
160 #define _CP_50 0x2AEF
161 #define _CP_OFF 0x3FFF
162 #define _PWRTE_OFF 0x3FFF
163 #define _PWRTE_ON 0x3FF7
164 #define _WDT_ON 0x3FFF
165 #define _WDT_OFF 0x3FFB
166 #define _LP_OSC 0x3FFC
167 #define _XT_OSC 0x3FFD
168 #define _HS_OSC 0x3FFE
169 #define _RC_OSC 0x3FFF
173 // ----- INTCON bits --------------------
176 unsigned char RBIF:1;
177 unsigned char INTF:1;
178 unsigned char T0IF:1;
179 unsigned char RBIE:1;
180 unsigned char INTE:1;
181 unsigned char T0IE:1;
186 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
188 #define RBIF INTCON_bits.RBIF
189 #define INTF INTCON_bits.INTF
190 #define T0IF INTCON_bits.T0IF
191 #define RBIE INTCON_bits.RBIE
192 #define INTE INTCON_bits.INTE
193 #define T0IE INTCON_bits.T0IE
194 #define GIE INTCON_bits.GIE
196 // ----- OPTION_REG bits --------------------
203 unsigned char T0SE:1;
204 unsigned char T0CS:1;
205 unsigned char INTEDG:1;
206 unsigned char NOT_RBPU:1;
208 } __OPTION_REG_bits_t;
209 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
211 #define PS0 OPTION_REG_bits.PS0
212 #define PS1 OPTION_REG_bits.PS1
213 #define PS2 OPTION_REG_bits.PS2
214 #define PSA OPTION_REG_bits.PSA
215 #define T0SE OPTION_REG_bits.T0SE
216 #define T0CS OPTION_REG_bits.T0CS
217 #define INTEDG OPTION_REG_bits.INTEDG
218 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
220 // ----- PCON bits --------------------
224 unsigned char NOT_POR:1;
233 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
235 #define NOT_POR PCON_bits.NOT_POR
237 // ----- STATUS bits --------------------
243 unsigned char NOT_PD:1;
244 unsigned char NOT_TO:1;
250 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
252 #define C STATUS_bits.C
253 #define DC STATUS_bits.DC
254 #define Z STATUS_bits.Z
255 #define NOT_PD STATUS_bits.NOT_PD
256 #define NOT_TO STATUS_bits.NOT_TO
257 #define RP0 STATUS_bits.RP0
258 #define RP1 STATUS_bits.RP1
259 #define IRP STATUS_bits.IRP