2 // Register Declarations for Microchip 16C557 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define OPTION_REG_ADDR 0x0081
39 #define TRISA_ADDR 0x0085
40 #define TRISB_ADDR 0x0086
41 #define TRISC_ADDR 0x0087
42 #define PCON_ADDR 0x008E
45 // Memory organization.
51 // P16C557.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
54 // This header file defines configurations, registers, and other useful bits of
55 // information for the PIC16C557 microcontroller. These names are taken to match
56 // the data sheets as closely as possible.
58 // Note that the processor must be selected before this file is
59 // included. The processor may be selected the following ways:
61 // 1. Command line switch:
62 // C:\ MPASM MYFILE.ASM /p=16C557
63 // 2. LIST directive in the source file
65 // 3. Processor Type entry in the MPASM full-screen interface
67 //==========================================================================
71 //==========================================================================
75 //1.00 08/29/01 Initial Release
77 //==========================================================================
81 //==========================================================================
84 // MESSG "Processor-header file mismatch. Verify selected processor."
87 //==========================================================================
89 // Register Definitions
91 //==========================================================================
96 //----- Register Files------------------------------------------------------
98 extern __data __at (INDF_ADDR) volatile char INDF;
99 extern __sfr __at (TMR0_ADDR) TMR0;
100 extern __data __at (PCL_ADDR) volatile char PCL;
101 extern __sfr __at (STATUS_ADDR) STATUS;
102 extern __sfr __at (FSR_ADDR) FSR;
103 extern __sfr __at (PORTA_ADDR) PORTA;
104 extern __sfr __at (PORTB_ADDR) PORTB;
105 extern __sfr __at (PORTC_ADDR) PORTC;
106 extern __sfr __at (PCLATH_ADDR) PCLATH;
107 extern __sfr __at (INTCON_ADDR) INTCON;
109 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
110 extern __sfr __at (TRISA_ADDR) TRISA;
111 extern __sfr __at (TRISB_ADDR) TRISB;
112 extern __sfr __at (TRISC_ADDR) TRISC;
113 extern __sfr __at (PCON_ADDR) PCON;
115 //----- STATUS Bits --------------------------------------------------------
118 //----- INTCON Bits --------------------------------------------------------
121 //----- OPTION Bits --------------------------------------------------------
124 //----- PCON Bits ----------------------------------------------------------
127 //==========================================================================
131 //==========================================================================
134 // __BADRAM H'08'-H'09', H'0C'-H'1F'
135 // __BADRAM H'88'-H'89', H'8C'-H'8D', H'8F'-H'9F', H'C0'-H'EF'
137 //==========================================================================
139 // Configuration Bits
141 //==========================================================================
143 #define _CP_ALL 0x00CF
144 #define _CP_75 0x15DF
145 #define _CP_50 0x2AEF
146 #define _CP_OFF 0x3FFF
147 #define _PWRTE_OFF 0x3FFF
148 #define _PWRTE_ON 0x3FF7
149 #define _WDT_ON 0x3FFF
150 #define _WDT_OFF 0x3FFB
151 #define _LP_OSC 0x3FFC
152 #define _XT_OSC 0x3FFD
153 #define _HS_OSC 0x3FFE
154 #define _RC_OSC 0x3FFF
158 // ----- INTCON bits --------------------
161 unsigned char RBIF:1;
162 unsigned char INTF:1;
163 unsigned char T0IF:1;
164 unsigned char RBIE:1;
165 unsigned char INTE:1;
166 unsigned char T0IE:1;
171 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
173 #define RBIF INTCON_bits.RBIF
174 #define INTF INTCON_bits.INTF
175 #define T0IF INTCON_bits.T0IF
176 #define RBIE INTCON_bits.RBIE
177 #define INTE INTCON_bits.INTE
178 #define T0IE INTCON_bits.T0IE
179 #define GIE INTCON_bits.GIE
181 // ----- OPTION_REG bits --------------------
188 unsigned char T0SE:1;
189 unsigned char T0CS:1;
190 unsigned char INTEDG:1;
191 unsigned char NOT_RBPU:1;
193 } __OPTION_REG_bits_t;
194 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
196 #define PS0 OPTION_REG_bits.PS0
197 #define PS1 OPTION_REG_bits.PS1
198 #define PS2 OPTION_REG_bits.PS2
199 #define PSA OPTION_REG_bits.PSA
200 #define T0SE OPTION_REG_bits.T0SE
201 #define T0CS OPTION_REG_bits.T0CS
202 #define INTEDG OPTION_REG_bits.INTEDG
203 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
205 // ----- PCON bits --------------------
209 unsigned char NOT_POR:1;
218 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
220 #define NOT_POR PCON_bits.NOT_POR
222 // ----- PORTA bits --------------------
235 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
237 #define RA0 PORTA_bits.RA0
238 #define RA1 PORTA_bits.RA1
239 #define RA2 PORTA_bits.RA2
240 #define RA3 PORTA_bits.RA3
241 #define RA4 PORTA_bits.RA4
242 #define RA5 PORTA_bits.RA5
244 // ----- PORTB bits --------------------
257 extern volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
259 #define RB0 PORTB_bits.RB0
260 #define RB1 PORTB_bits.RB1
261 #define RB2 PORTB_bits.RB2
262 #define RB3 PORTB_bits.RB3
263 #define RB4 PORTB_bits.RB4
264 #define RB5 PORTB_bits.RB5
265 #define RB6 PORTB_bits.RB6
266 #define RB7 PORTB_bits.RB7
268 // ----- PORTC bits --------------------
281 extern volatile __PORTC_bits_t __at(PORTC_ADDR) PORTC_bits;
283 #define RC0 PORTC_bits.RC0
284 #define RC1 PORTC_bits.RC1
285 #define RC2 PORTC_bits.RC2
286 #define RC3 PORTC_bits.RC3
287 #define RC4 PORTC_bits.RC4
288 #define RC5 PORTC_bits.RC5
289 #define RC6 PORTC_bits.RC6
290 #define RC7 PORTC_bits.RC7
292 // ----- STATUS bits --------------------
298 unsigned char NOT_PD:1;
299 unsigned char NOT_TO:1;
305 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
307 #define C STATUS_bits.C
308 #define DC STATUS_bits.DC
309 #define Z STATUS_bits.Z
310 #define NOT_PD STATUS_bits.NOT_PD
311 #define NOT_TO STATUS_bits.NOT_TO
312 #define RP0 STATUS_bits.RP0
313 #define RP1 STATUS_bits.RP1
314 #define IRP STATUS_bits.IRP
316 // ----- TRISA bits --------------------
319 unsigned char TRISA0:1;
320 unsigned char TRISA1:1;
321 unsigned char TRISA2:1;
322 unsigned char TRISA3:1;
323 unsigned char TRISA4:1;
324 unsigned char TRISA5:1;
329 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
331 #define TRISA0 TRISA_bits.TRISA0
332 #define TRISA1 TRISA_bits.TRISA1
333 #define TRISA2 TRISA_bits.TRISA2
334 #define TRISA3 TRISA_bits.TRISA3
335 #define TRISA4 TRISA_bits.TRISA4
336 #define TRISA5 TRISA_bits.TRISA5
338 // ----- TRISB bits --------------------
341 unsigned char TRISB0:1;
342 unsigned char TRISB1:1;
343 unsigned char TRISB2:1;
344 unsigned char TRISB3:1;
345 unsigned char TRISB4:1;
346 unsigned char TRISB5:1;
347 unsigned char TRISB6:1;
348 unsigned char TRISB7:1;
351 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
353 #define TRISB0 TRISB_bits.TRISB0
354 #define TRISB1 TRISB_bits.TRISB1
355 #define TRISB2 TRISB_bits.TRISB2
356 #define TRISB3 TRISB_bits.TRISB3
357 #define TRISB4 TRISB_bits.TRISB4
358 #define TRISB5 TRISB_bits.TRISB5
359 #define TRISB6 TRISB_bits.TRISB6
360 #define TRISB7 TRISB_bits.TRISB7
362 // ----- TRISC bits --------------------
365 unsigned char TRISC0:1;
366 unsigned char TRISC1:1;
367 unsigned char TRISC2:1;
368 unsigned char TRISC3:1;
369 unsigned char TRISC4:1;
370 unsigned char TRISC5:1;
371 unsigned char TRISC6:1;
372 unsigned char TRISC7:1;
375 extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits;
377 #define TRISC0 TRISC_bits.TRISC0
378 #define TRISC1 TRISC_bits.TRISC1
379 #define TRISC2 TRISC_bits.TRISC2
380 #define TRISC3 TRISC_bits.TRISC3
381 #define TRISC4 TRISC_bits.TRISC4
382 #define TRISC5 TRISC_bits.TRISC5
383 #define TRISC6 TRISC_bits.TRISC6
384 #define TRISC7 TRISC_bits.TRISC7