2 // Register Declarations for Microchip 16C554 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PCLATH_ADDR 0x000A
36 #define INTCON_ADDR 0x000B
37 #define OPTION_REG_ADDR 0x0081
38 #define TRISA_ADDR 0x0085
39 #define TRISB_ADDR 0x0086
40 #define PCON_ADDR 0x008E
43 // Memory organization.
46 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
47 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
48 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
49 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
50 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
51 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
52 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
53 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
54 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
55 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
56 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
57 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
58 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
62 // P16C554.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
65 // This header file defines configurations, registers, and other useful bits of
66 // information for the PIC16C554 microcontroller. These names are taken to match
67 // the data sheets as closely as possible.
69 // Note that the processor must be selected before this file is
70 // included. The processor may be selected the following ways:
72 // 1. Command line switch:
73 // C:\ MPASM MYFILE.ASM /PIC16C554
74 // 2. LIST directive in the source file
76 // 3. Processor Type entry in the MPASM full-screen interface
78 //==========================================================================
82 //==========================================================================
86 //1.00 04/22/96 Initial Creation
88 //==========================================================================
92 //==========================================================================
95 // MESSG "Processor-header file mismatch. Verify selected processor."
98 //==========================================================================
100 // Register Definitions
102 //==========================================================================
107 //----- Register Files------------------------------------------------------
109 extern __data __at (INDF_ADDR) volatile char INDF;
110 extern __sfr __at (TMR0_ADDR) TMR0;
111 extern __data __at (PCL_ADDR) volatile char PCL;
112 extern __sfr __at (STATUS_ADDR) STATUS;
113 extern __sfr __at (FSR_ADDR) FSR;
114 extern __sfr __at (PORTA_ADDR) PORTA;
115 extern __sfr __at (PORTB_ADDR) PORTB;
116 extern __sfr __at (PCLATH_ADDR) PCLATH;
117 extern __sfr __at (INTCON_ADDR) INTCON;
119 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
120 extern __sfr __at (TRISA_ADDR) TRISA;
121 extern __sfr __at (TRISB_ADDR) TRISB;
122 extern __sfr __at (PCON_ADDR) PCON;
124 //----- STATUS Bits --------------------------------------------------------
127 //----- INTCON Bits --------------------------------------------------------
130 //----- OPTION Bits --------------------------------------------------------
133 //----- PCON Bits ----------------------------------------------------------
136 //==========================================================================
140 //==========================================================================
143 // __BADRAM H'07'-H'09', H'0C'-H'1F', H'70'-H'7F'
144 // __BADRAM H'87'-H'89', H'8C'-H'8D', H'8F'-H'9F'
146 //==========================================================================
148 // Configuration Bits
150 //==========================================================================
152 #define _CP_ON 0x00CF
153 #define _CP_OFF 0x3FFF
154 #define _PWRTE_OFF 0x3FFF
155 #define _PWRTE_ON 0x3FF7
156 #define _WDT_ON 0x3FFF
157 #define _WDT_OFF 0x3FFB
158 #define _LP_OSC 0x3FFC
159 #define _XT_OSC 0x3FFD
160 #define _HS_OSC 0x3FFE
161 #define _RC_OSC 0x3FFF
165 // ----- INTCON bits --------------------
168 unsigned char RBIF:1;
169 unsigned char INTF:1;
170 unsigned char T0IF:1;
171 unsigned char RBIE:1;
172 unsigned char INTE:1;
173 unsigned char T0IE:1;
178 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
180 #define RBIF INTCON_bits.RBIF
181 #define INTF INTCON_bits.INTF
182 #define T0IF INTCON_bits.T0IF
183 #define RBIE INTCON_bits.RBIE
184 #define INTE INTCON_bits.INTE
185 #define T0IE INTCON_bits.T0IE
186 #define GIE INTCON_bits.GIE
188 // ----- OPTION_REG bits --------------------
195 unsigned char T0SE:1;
196 unsigned char T0CS:1;
197 unsigned char INTEDG:1;
198 unsigned char NOT_RBPU:1;
200 } __OPTION_REG_bits_t;
201 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
203 #define PS0 OPTION_REG_bits.PS0
204 #define PS1 OPTION_REG_bits.PS1
205 #define PS2 OPTION_REG_bits.PS2
206 #define PSA OPTION_REG_bits.PSA
207 #define T0SE OPTION_REG_bits.T0SE
208 #define T0CS OPTION_REG_bits.T0CS
209 #define INTEDG OPTION_REG_bits.INTEDG
210 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
212 // ----- PCON bits --------------------
216 unsigned char NOT_POR:1;
225 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
227 #define NOT_POR PCON_bits.NOT_POR
229 // ----- STATUS bits --------------------
235 unsigned char NOT_PD:1;
236 unsigned char NOT_TO:1;
242 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
244 #define C STATUS_bits.C
245 #define DC STATUS_bits.DC
246 #define Z STATUS_bits.Z
247 #define NOT_PD STATUS_bits.NOT_PD
248 #define NOT_TO STATUS_bits.NOT_TO
249 #define RP0 STATUS_bits.RP0
250 #define RP1 STATUS_bits.RP1
251 #define IRP STATUS_bits.IRP