2 // Register Declarations for Microchip 16C433 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define GPIO_ADDR 0x0005
34 #define PCLATH_ADDR 0x000A
35 #define INTCON_ADDR 0x000B
36 #define PIR1_ADDR 0x000C
37 #define ADRES_ADDR 0x001E
38 #define ADCON0_ADDR 0x001F
39 #define OPTION_REG_ADDR 0x0081
40 #define TRISIO_ADDR 0x0085
41 #define PIE1_ADDR 0x008C
42 #define PCON_ADDR 0x008E
43 #define OSCCAL_ADDR 0x008F
44 #define ADCON1_ADDR 0x009F
47 // Memory organization.
53 // P16C433.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
56 // This header file defines configurations, registers, and other useful bits of
57 // information for the PIC16C433 microcontroller. These names are taken to match
58 // the data sheets as closely as possible.
60 // Note that the processor must be selected before this file is
61 // included. The processor may be selected the following ways:
63 // 1. Command line switch:
64 // C:\ MPASM MYFILE.ASM /PIC16C433
65 // 2. LIST directive in the source file
67 // 3. Processor Type entry in the MPASM full-screen interface
69 //==========================================================================
73 //==========================================================================
77 //1.00 31 Aug 2000 Original Release
78 //1.10 28 Mar 2001 Corrected definitions of LINTX and LINRX.
79 //==========================================================================
83 //==========================================================================
86 // MESSG "Processor-header file mismatch. Verify selected processor."
89 //==========================================================================
91 // Register Definitions
93 //==========================================================================
98 //----- Register Files------------------------------------------------------
100 extern __sfr __at (INDF_ADDR) INDF;
101 extern __sfr __at (TMR0_ADDR) TMR0;
102 extern __sfr __at (PCL_ADDR) PCL;
103 extern __sfr __at (STATUS_ADDR) STATUS;
104 extern __sfr __at (FSR_ADDR) FSR;
105 extern __sfr __at (GPIO_ADDR) GPIO;
106 extern __sfr __at (PCLATH_ADDR) PCLATH;
107 extern __sfr __at (INTCON_ADDR) INTCON;
108 extern __sfr __at (PIR1_ADDR) PIR1;
109 extern __sfr __at (ADRES_ADDR) ADRES;
110 extern __sfr __at (ADCON0_ADDR) ADCON0;
112 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
113 extern __sfr __at (TRISIO_ADDR) TRISIO;
114 extern __sfr __at (PIE1_ADDR) PIE1;
115 extern __sfr __at (PCON_ADDR) PCON;
116 extern __sfr __at (OSCCAL_ADDR) OSCCAL;
117 extern __sfr __at (ADCON1_ADDR) ADCON1;
119 //----- STATUS Bits --------------------------------------------------------
122 //----- LIN Port bits (within GPIO) ----------------------------------------
124 //----- ADCON0 Bits --------------------------------------------------------
127 //----- INTCON Bits --------------------------------------------------------
130 //----- PIR1 Bits ----------------------------------------------------------
133 //----- OPTION Bits --------------------------------------------------------
136 //----- PIE1 Bits ----------------------------------------------------------
139 //----- PCON Bits ----------------------------------------------------------
142 //----- OSCCAL Bits --------------------------------------------------------
145 //----- ADCON1 Bits --------------------------------------------------------
148 //==========================================================================
152 //==========================================================================
155 // __BADRAM H'06'-H'09', H'0D'-H'1D'
156 // __BADRAM H'86'-H'89', H'8D', H'90'-H'9E', H'C0'-H'EF'
158 //==========================================================================
160 // Configuration Bits
162 //==========================================================================
164 #define _MCLRE_ON 0x3FFF
165 #define _MCLRE_OFF 0x3F7F
166 #define _CP_ALL 0x009F
167 #define _CP_75 0x15BF
168 #define _CP_50 0x2ADF
169 #define _CP_OFF 0x3FFF
170 #define _PWRTE_OFF 0x3FFF
171 #define _PWRTE_ON 0x3FEF
172 #define _WDT_ON 0x3FFF
173 #define _WDT_OFF 0x3FF7
174 #define _LP_OSC 0x3FF8
175 #define _XT_OSC 0x3FF9
176 #define _HS_OSC 0x3FFA
177 #define _INTRC_OSC 0x3FFC
178 #define _INTRC_OSC_NOCLKOUT 0x3FFC
179 #define _INTRC_OSC_CLKOUT 0x3FFD
180 #define _EXTRC_OSC 0x3FFE
181 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
182 #define _EXTRC_OSC_CLKOUT 0x3FFF
186 // ----- ADCON0 bits --------------------
189 unsigned char ADON:1;
192 unsigned char CHS0:1;
193 unsigned char CHS1:1;
195 unsigned char ADCS0:1;
196 unsigned char ADCS1:1;
201 unsigned char NOT_DONE:1;
211 unsigned char GO_DONE:1;
219 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
221 #ifndef NO_BIT_DEFINES
222 #define ADON ADCON0_bits.ADON
223 #define GO ADCON0_bits.GO
224 #define NOT_DONE ADCON0_bits.NOT_DONE
225 #define GO_DONE ADCON0_bits.GO_DONE
226 #define CHS0 ADCON0_bits.CHS0
227 #define CHS1 ADCON0_bits.CHS1
228 #define ADCS0 ADCON0_bits.ADCS0
229 #define ADCS1 ADCON0_bits.ADCS1
230 #endif /* NO_BIT_DEFINES */
232 // ----- ADCON1 bits --------------------
235 unsigned char PCFG0:1;
236 unsigned char PCFG1:1;
237 unsigned char PCFG2:1;
245 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
247 #ifndef NO_BIT_DEFINES
248 #define PCFG0 ADCON1_bits.PCFG0
249 #define PCFG1 ADCON1_bits.PCFG1
250 #define PCFG2 ADCON1_bits.PCFG2
251 #endif /* NO_BIT_DEFINES */
253 // ----- INTCON bits --------------------
256 unsigned char GPIF:1;
257 unsigned char INTF:1;
258 unsigned char T0IF:1;
259 unsigned char GPIE:1;
260 unsigned char INTE:1;
261 unsigned char T0IE:1;
262 unsigned char PEIE:1;
266 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
268 #ifndef NO_BIT_DEFINES
269 #define GPIF INTCON_bits.GPIF
270 #define INTF INTCON_bits.INTF
271 #define T0IF INTCON_bits.T0IF
272 #define GPIE INTCON_bits.GPIE
273 #define INTE INTCON_bits.INTE
274 #define T0IE INTCON_bits.T0IE
275 #define PEIE INTCON_bits.PEIE
276 #define GIE INTCON_bits.GIE
277 #endif /* NO_BIT_DEFINES */
279 // ----- OPTION_REG bits --------------------
286 unsigned char T0SE:1;
287 unsigned char T0CS:1;
288 unsigned char INTEDG:1;
289 unsigned char NOT_GPPU:1;
291 } __OPTION_REG_bits_t;
292 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
294 #ifndef NO_BIT_DEFINES
295 #define PS0 OPTION_REG_bits.PS0
296 #define PS1 OPTION_REG_bits.PS1
297 #define PS2 OPTION_REG_bits.PS2
298 #define PSA OPTION_REG_bits.PSA
299 #define T0SE OPTION_REG_bits.T0SE
300 #define T0CS OPTION_REG_bits.T0CS
301 #define INTEDG OPTION_REG_bits.INTEDG
302 #define NOT_GPPU OPTION_REG_bits.NOT_GPPU
303 #endif /* NO_BIT_DEFINES */
305 // ----- OSCCAL bits --------------------
310 unsigned char CALSLW:1;
311 unsigned char CALFST:1;
312 unsigned char CAL0:1;
313 unsigned char CAL1:1;
314 unsigned char CAL2:1;
315 unsigned char CAL3:1;
318 extern volatile __OSCCAL_bits_t __at(OSCCAL_ADDR) OSCCAL_bits;
320 #ifndef NO_BIT_DEFINES
321 #define CALSLW OSCCAL_bits.CALSLW
322 #define CALFST OSCCAL_bits.CALFST
323 #define CAL0 OSCCAL_bits.CAL0
324 #define CAL1 OSCCAL_bits.CAL1
325 #define CAL2 OSCCAL_bits.CAL2
326 #define CAL3 OSCCAL_bits.CAL3
327 #endif /* NO_BIT_DEFINES */
329 // ----- PCON bits --------------------
333 unsigned char NOT_POR:1;
342 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
344 #ifndef NO_BIT_DEFINES
345 #define NOT_POR PCON_bits.NOT_POR
346 #endif /* NO_BIT_DEFINES */
348 // ----- PIE1 bits --------------------
357 unsigned char ADIE:1;
361 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
363 #ifndef NO_BIT_DEFINES
364 #define ADIE PIE1_bits.ADIE
365 #endif /* NO_BIT_DEFINES */
367 // ----- PIR1 bits --------------------
376 unsigned char ADIF:1;
380 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
382 #ifndef NO_BIT_DEFINES
383 #define ADIF PIR1_bits.ADIF
384 #endif /* NO_BIT_DEFINES */
386 // ----- STATUS bits --------------------
392 unsigned char NOT_PD:1;
393 unsigned char NOT_TO:1;
405 unsigned char LINRX:1;
406 unsigned char LINTX:1;
409 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
411 #ifndef NO_BIT_DEFINES
412 #define C STATUS_bits.C
413 #define DC STATUS_bits.DC
414 #define Z STATUS_bits.Z
415 #define NOT_PD STATUS_bits.NOT_PD
416 #define NOT_TO STATUS_bits.NOT_TO
417 #define RP0 STATUS_bits.RP0
418 #define RP1 STATUS_bits.RP1
419 #define LINRX STATUS_bits.LINRX
420 #define IRP STATUS_bits.IRP
421 #define LINTX STATUS_bits.LINTX
422 #endif /* NO_BIT_DEFINES */