2 // Register Declarations for Microchip 16C433 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define GPIO_ADDR 0x0005
34 #define PCLATH_ADDR 0x000A
35 #define INTCON_ADDR 0x000B
36 #define PIR1_ADDR 0x000C
37 #define ADRES_ADDR 0x001E
38 #define ADCON0_ADDR 0x001F
39 #define OPTION_REG_ADDR 0x0081
40 #define TRISIO_ADDR 0x0085
41 #define PIE1_ADDR 0x008C
42 #define PCON_ADDR 0x008E
43 #define OSCCAL_ADDR 0x008F
44 #define ADCON1_ADDR 0x009F
47 // Memory organization.
50 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
51 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
52 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
53 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
54 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
55 #pragma memmap GPIO_ADDR GPIO_ADDR SFR 0x000 // GPIO
56 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
57 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
58 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
59 #pragma memmap ADRES_ADDR ADRES_ADDR SFR 0x000 // ADRES
60 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
61 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
62 #pragma memmap TRISIO_ADDR TRISIO_ADDR SFR 0x000 // TRISIO
63 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
64 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
65 #pragma memmap OSCCAL_ADDR OSCCAL_ADDR SFR 0x000 // OSCCAL
66 #pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
70 // P16C433.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
73 // This header file defines configurations, registers, and other useful bits of
74 // information for the PIC16C433 microcontroller. These names are taken to match
75 // the data sheets as closely as possible.
77 // Note that the processor must be selected before this file is
78 // included. The processor may be selected the following ways:
80 // 1. Command line switch:
81 // C:\ MPASM MYFILE.ASM /PIC16C433
82 // 2. LIST directive in the source file
84 // 3. Processor Type entry in the MPASM full-screen interface
86 //==========================================================================
90 //==========================================================================
94 //1.00 31 Aug 2000 Original Release
95 //1.10 28 Mar 2001 Corrected definitions of LINTX and LINRX.
96 //==========================================================================
100 //==========================================================================
103 // MESSG "Processor-header file mismatch. Verify selected processor."
106 //==========================================================================
108 // Register Definitions
110 //==========================================================================
115 //----- Register Files------------------------------------------------------
117 extern __data __at (INDF_ADDR) volatile char INDF;
118 extern __sfr __at (TMR0_ADDR) TMR0;
119 extern __data __at (PCL_ADDR) volatile char PCL;
120 extern __sfr __at (STATUS_ADDR) STATUS;
121 extern __sfr __at (FSR_ADDR) FSR;
122 extern __sfr __at (GPIO_ADDR) GPIO;
123 extern __sfr __at (PCLATH_ADDR) PCLATH;
124 extern __sfr __at (INTCON_ADDR) INTCON;
125 extern __sfr __at (PIR1_ADDR) PIR1;
126 extern __sfr __at (ADRES_ADDR) ADRES;
127 extern __sfr __at (ADCON0_ADDR) ADCON0;
129 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
130 extern __sfr __at (TRISIO_ADDR) TRISIO;
131 extern __sfr __at (PIE1_ADDR) PIE1;
132 extern __sfr __at (PCON_ADDR) PCON;
133 extern __sfr __at (OSCCAL_ADDR) OSCCAL;
134 extern __sfr __at (ADCON1_ADDR) ADCON1;
136 //----- STATUS Bits --------------------------------------------------------
139 //----- LIN Port bits (within GPIO) ----------------------------------------
141 //----- ADCON0 Bits --------------------------------------------------------
144 //----- INTCON Bits --------------------------------------------------------
147 //----- PIR1 Bits ----------------------------------------------------------
150 //----- OPTION Bits --------------------------------------------------------
153 //----- PIE1 Bits ----------------------------------------------------------
156 //----- PCON Bits ----------------------------------------------------------
159 //----- OSCCAL Bits --------------------------------------------------------
162 //----- ADCON1 Bits --------------------------------------------------------
165 //==========================================================================
169 //==========================================================================
172 // __BADRAM H'06'-H'09', H'0D'-H'1D'
173 // __BADRAM H'86'-H'89', H'8D', H'90'-H'9E', H'C0'-H'EF'
175 //==========================================================================
177 // Configuration Bits
179 //==========================================================================
181 #define _MCLRE_ON 0x3FFF
182 #define _MCLRE_OFF 0x3F7F
183 #define _CP_ALL 0x009F
184 #define _CP_75 0x15BF
185 #define _CP_50 0x2ADF
186 #define _CP_OFF 0x3FFF
187 #define _PWRTE_OFF 0x3FFF
188 #define _PWRTE_ON 0x3FEF
189 #define _WDT_ON 0x3FFF
190 #define _WDT_OFF 0x3FF7
191 #define _LP_OSC 0x3FF8
192 #define _XT_OSC 0x3FF9
193 #define _HS_OSC 0x3FFA
194 #define _INTRC_OSC 0x3FFC
195 #define _INTRC_OSC_NOCLKOUT 0x3FFC
196 #define _INTRC_OSC_CLKOUT 0x3FFD
197 #define _EXTRC_OSC 0x3FFE
198 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
199 #define _EXTRC_OSC_CLKOUT 0x3FFF
203 // ----- ADCON0 bits --------------------
206 unsigned char ADON:1;
209 unsigned char CHS0:1;
210 unsigned char CHS1:1;
212 unsigned char ADCS0:1;
213 unsigned char ADCS1:1;
218 unsigned char NOT_DONE:1;
228 unsigned char GO_DONE:1;
236 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
238 #define ADON ADCON0_bits.ADON
239 #define GO ADCON0_bits.GO
240 #define NOT_DONE ADCON0_bits.NOT_DONE
241 #define GO_DONE ADCON0_bits.GO_DONE
242 #define CHS0 ADCON0_bits.CHS0
243 #define CHS1 ADCON0_bits.CHS1
244 #define ADCS0 ADCON0_bits.ADCS0
245 #define ADCS1 ADCON0_bits.ADCS1
247 // ----- ADCON1 bits --------------------
250 unsigned char PCFG0:1;
251 unsigned char PCFG1:1;
252 unsigned char PCFG2:1;
260 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
262 #define PCFG0 ADCON1_bits.PCFG0
263 #define PCFG1 ADCON1_bits.PCFG1
264 #define PCFG2 ADCON1_bits.PCFG2
266 // ----- INTCON bits --------------------
269 unsigned char GPIF:1;
270 unsigned char INTF:1;
271 unsigned char T0IF:1;
272 unsigned char GPIE:1;
273 unsigned char INTE:1;
274 unsigned char T0IE:1;
275 unsigned char PEIE:1;
279 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
281 #define GPIF INTCON_bits.GPIF
282 #define INTF INTCON_bits.INTF
283 #define T0IF INTCON_bits.T0IF
284 #define GPIE INTCON_bits.GPIE
285 #define INTE INTCON_bits.INTE
286 #define T0IE INTCON_bits.T0IE
287 #define PEIE INTCON_bits.PEIE
288 #define GIE INTCON_bits.GIE
290 // ----- OPTION_REG bits --------------------
297 unsigned char T0SE:1;
298 unsigned char T0CS:1;
299 unsigned char INTEDG:1;
300 unsigned char NOT_GPPU:1;
302 } __OPTION_REG_bits_t;
303 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
305 #define PS0 OPTION_REG_bits.PS0
306 #define PS1 OPTION_REG_bits.PS1
307 #define PS2 OPTION_REG_bits.PS2
308 #define PSA OPTION_REG_bits.PSA
309 #define T0SE OPTION_REG_bits.T0SE
310 #define T0CS OPTION_REG_bits.T0CS
311 #define INTEDG OPTION_REG_bits.INTEDG
312 #define NOT_GPPU OPTION_REG_bits.NOT_GPPU
314 // ----- OSCCAL bits --------------------
319 unsigned char CALSLW:1;
320 unsigned char CALFST:1;
321 unsigned char CAL0:1;
322 unsigned char CAL1:1;
323 unsigned char CAL2:1;
324 unsigned char CAL3:1;
327 extern volatile __OSCCAL_bits_t __at(OSCCAL_ADDR) OSCCAL_bits;
329 #define CALSLW OSCCAL_bits.CALSLW
330 #define CALFST OSCCAL_bits.CALFST
331 #define CAL0 OSCCAL_bits.CAL0
332 #define CAL1 OSCCAL_bits.CAL1
333 #define CAL2 OSCCAL_bits.CAL2
334 #define CAL3 OSCCAL_bits.CAL3
336 // ----- PCON bits --------------------
340 unsigned char NOT_POR:1;
349 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
351 #define NOT_POR PCON_bits.NOT_POR
353 // ----- PIE1 bits --------------------
362 unsigned char ADIE:1;
366 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
368 #define ADIE PIE1_bits.ADIE
370 // ----- PIR1 bits --------------------
379 unsigned char ADIF:1;
383 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
385 #define ADIF PIR1_bits.ADIF
387 // ----- STATUS bits --------------------
393 unsigned char NOT_PD:1;
394 unsigned char NOT_TO:1;
406 unsigned char LINRX:1;
407 unsigned char LINTX:1;
410 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
412 #define C STATUS_bits.C
413 #define DC STATUS_bits.DC
414 #define Z STATUS_bits.Z
415 #define NOT_PD STATUS_bits.NOT_PD
416 #define NOT_TO STATUS_bits.NOT_TO
417 #define RP0 STATUS_bits.RP0
418 #define RP1 STATUS_bits.RP1
419 #define LINRX STATUS_bits.LINRX
420 #define IRP STATUS_bits.IRP
421 #define LINTX STATUS_bits.LINTX