2 // Register Declarations for Microchip 16C432 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PCLATH_ADDR 0x000A
36 #define INTCON_ADDR 0x000B
37 #define PIR1_ADDR 0x000C
38 #define CMCON_ADDR 0x001F
39 #define OPTION_REG_ADDR 0x0081
40 #define TRISA_ADDR 0x0085
41 #define TRISB_ADDR 0x0086
42 #define PIE1_ADDR 0x008C
43 #define PCON_ADDR 0x008E
44 #define LININTF_ADDR 0x0090
45 #define VRCON_ADDR 0x009F
48 // Memory organization.
51 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
52 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
53 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
54 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
55 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
56 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
57 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
58 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
59 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
60 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
61 #pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000 // CMCON
62 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
63 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
64 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
65 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
66 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
67 #pragma memmap LININTF_ADDR LININTF_ADDR SFR 0x000 // LININTF
68 #pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON
72 // P16C432.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
75 // This header file defines configurations, registers, and other useful bits of
76 // information for the PIC16C432 microcontroller. These names are taken to match
77 // the data sheets as closely as possible.
79 // Note that the processor must be selected before this file is
80 // included. The processor may be selected the following ways:
82 // 1. Command line switch:
83 // C:\ MPASM MYFILE.ASM /PIC16C432
84 // 2. LIST directive in the source file
86 // 3. Processor Type entry in the MPASM full-screen interface
88 //==========================================================================
92 //==========================================================================
96 //1.00 31 Aug 2000 Initial Release
97 //1.10 28 Mar 2001 Corrected definition of LINTX
99 //==========================================================================
103 //==========================================================================
106 // MESSG "Processor-header file mismatch. Verify selected processor."
109 //==========================================================================
111 // Register Definitions
113 //==========================================================================
118 //----- Register Files------------------------------------------------------
120 extern data __at (INDF_ADDR) volatile char INDF;
121 extern sfr __at (TMR0_ADDR) TMR0;
122 extern data __at (PCL_ADDR) volatile char PCL;
123 extern sfr __at (STATUS_ADDR) STATUS;
124 extern sfr __at (FSR_ADDR) FSR;
125 extern sfr __at (PORTA_ADDR) PORTA;
126 extern sfr __at (PORTB_ADDR) PORTB;
127 extern sfr __at (PCLATH_ADDR) PCLATH;
128 extern sfr __at (INTCON_ADDR) INTCON;
129 extern sfr __at (PIR1_ADDR) PIR1;
130 extern sfr __at (CMCON_ADDR) CMCON;
132 extern sfr __at (OPTION_REG_ADDR) OPTION_REG;
133 extern sfr __at (TRISA_ADDR) TRISA;
134 extern sfr __at (TRISB_ADDR) TRISB;
135 extern sfr __at (PIE1_ADDR) PIE1;
136 extern sfr __at (PCON_ADDR) PCON;
137 extern sfr __at (LININTF_ADDR) LININTF;
138 extern sfr __at (VRCON_ADDR) VRCON;
140 //----- STATUS Bits --------------------------------------------------------
143 //----- INTCON Bits --------------------------------------------------------
146 //----- PORTA Bits --------------------------------------------------------
148 //----- PIR1 Bits ----------------------------------------------------------
151 //----- CMCON Bits ---------------------------------------------------------
154 //----- OPTION Bits --------------------------------------------------------
157 //----- PIE1 Bits ----------------------------------------------------------
160 //----- PCON Bits ----------------------------------------------------------
163 //----- VRCON Bits ---------------------------------------------------------
166 //----- LININTF Bits ----------------------------------------------------------
169 //==========================================================================
173 //==========================================================================
176 // __BADRAM H'07'-H'09', H'0D'-H'1E'
177 // __BADRAM H'87'-H'89', H'8D', H'8F', H'91'-H'9E'
178 // __BADRAM H'C0'-H'EF'
180 //==========================================================================
182 // Configuration Bits
184 //==========================================================================
186 #define _BODEN_ON 0x3FFF
187 #define _BODEN_OFF 0x3FBF
188 #define _CP_ALL 0x00CF
189 #define _CP_75 0x15DF
190 #define _CP_50 0x2AEF
191 #define _CP_OFF 0x3FFF
192 #define _PWRTE_OFF 0x3FFF
193 #define _PWRTE_ON 0x3FF7
194 #define _WDT_ON 0x3FFF
195 #define _WDT_OFF 0x3FFB
196 #define _LP_OSC 0x3FFC
197 #define _XT_OSC 0x3FFD
198 #define _HS_OSC 0x3FFE
199 #define _RC_OSC 0x3FFF
203 // ----- CMCON bits --------------------
212 unsigned char C1OUT:1;
213 unsigned char C2OUT:1;
216 extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;
218 #define CM0 CMCON_bits.CM0
219 #define CM1 CMCON_bits.CM1
220 #define CM2 CMCON_bits.CM2
221 #define CIS CMCON_bits.CIS
222 #define C1OUT CMCON_bits.C1OUT
223 #define C2OUT CMCON_bits.C2OUT
225 // ----- INTCON bits --------------------
228 unsigned char RBIF:1;
229 unsigned char INTF:1;
230 unsigned char T0IF:1;
231 unsigned char RBIE:1;
232 unsigned char INTE:1;
233 unsigned char T0IE:1;
234 unsigned char PEIE:1;
238 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
240 #define RBIF INTCON_bits.RBIF
241 #define INTF INTCON_bits.INTF
242 #define T0IF INTCON_bits.T0IF
243 #define RBIE INTCON_bits.RBIE
244 #define INTE INTCON_bits.INTE
245 #define T0IE INTCON_bits.T0IE
246 #define PEIE INTCON_bits.PEIE
247 #define GIE INTCON_bits.GIE
249 // ----- LININTF bits --------------------
252 unsigned char LINVDD:1;
254 unsigned char LINTX:1;
262 extern volatile __LININTF_bits_t __at(LININTF_ADDR) LININTF_bits;
264 #define LINVDD LININTF_bits.LINVDD
265 #define LINTX LININTF_bits.LINTX
267 // ----- OPTION_REG bits --------------------
274 unsigned char T0SE:1;
275 unsigned char T0CS:1;
276 unsigned char INTEDG:1;
277 unsigned char NOT_RBPU:1;
279 } __OPTION_REG_bits_t;
280 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
282 #define PS0 OPTION_REG_bits.PS0
283 #define PS1 OPTION_REG_bits.PS1
284 #define PS2 OPTION_REG_bits.PS2
285 #define PSA OPTION_REG_bits.PSA
286 #define T0SE OPTION_REG_bits.T0SE
287 #define T0CS OPTION_REG_bits.T0CS
288 #define INTEDG OPTION_REG_bits.INTEDG
289 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
291 // ----- PCON bits --------------------
294 unsigned char NOT_BO:1;
295 unsigned char NOT_POR:1;
304 unsigned char NOT_BOR:1;
314 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
316 #define NOT_BO PCON_bits.NOT_BO
317 #define NOT_BOR PCON_bits.NOT_BOR
318 #define NOT_POR PCON_bits.NOT_POR
320 // ----- PIE1 bits --------------------
329 unsigned char CMIE:1;
333 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
335 #define CMIE PIE1_bits.CMIE
337 // ----- PIR1 bits --------------------
346 unsigned char CMIF:1;
350 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
352 #define CMIF PIR1_bits.CMIF
354 // ----- PORTA bits --------------------
358 unsigned char LINRX:1;
367 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
369 #define LINRX PORTA_bits.LINRX
371 // ----- STATUS bits --------------------
377 unsigned char NOT_PD:1;
378 unsigned char NOT_TO:1;
384 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
386 #define C STATUS_bits.C
387 #define DC STATUS_bits.DC
388 #define Z STATUS_bits.Z
389 #define NOT_PD STATUS_bits.NOT_PD
390 #define NOT_TO STATUS_bits.NOT_TO
391 #define RP0 STATUS_bits.RP0
392 #define RP1 STATUS_bits.RP1
393 #define IRP STATUS_bits.IRP
395 // ----- VRCON bits --------------------
404 unsigned char VROE:1;
405 unsigned char VREN:1;
408 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
410 #define VR0 VRCON_bits.VR0
411 #define VR1 VRCON_bits.VR1
412 #define VR2 VRCON_bits.VR2
413 #define VR3 VRCON_bits.VR3
414 #define VRR VRCON_bits.VRR
415 #define VROE VRCON_bits.VROE
416 #define VREN VRCON_bits.VREN