2 // Register Declarations for Microchip 16C432 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PCLATH_ADDR 0x000A
36 #define INTCON_ADDR 0x000B
37 #define PIR1_ADDR 0x000C
38 #define CMCON_ADDR 0x001F
39 #define OPTION_REG_ADDR 0x0081
40 #define TRISA_ADDR 0x0085
41 #define TRISB_ADDR 0x0086
42 #define PIE1_ADDR 0x008C
43 #define PCON_ADDR 0x008E
44 #define LINPRT_ADDR 0x0090
45 #define VRCON_ADDR 0x009F
48 // Memory organization.
54 // P16C432.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
57 // This header file defines configurations, registers, and other useful bits of
58 // information for the PIC16C432 microcontroller. These names are taken to match
59 // the data sheets as closely as possible.
61 // Note that the processor must be selected before this file is
62 // included. The processor may be selected the following ways:
64 // 1. Command line switch:
65 // C:\ MPASM MYFILE.ASM /PIC16C432
66 // 2. LIST directive in the source file
68 // 3. Processor Type entry in the MPASM full-screen interface
70 //==========================================================================
74 //==========================================================================
78 //1.00 31 Aug 2000 Initial Release
79 //1.10 28 Mar 2001 Corrected definition of LINTX
81 //==========================================================================
85 //==========================================================================
88 // MESSG "Processor-header file mismatch. Verify selected processor."
91 //==========================================================================
93 // Register Definitions
95 //==========================================================================
100 //----- Register Files------------------------------------------------------
102 extern __sfr __at (INDF_ADDR) INDF;
103 extern __sfr __at (TMR0_ADDR) TMR0;
104 extern __sfr __at (PCL_ADDR) PCL;
105 extern __sfr __at (STATUS_ADDR) STATUS;
106 extern __sfr __at (FSR_ADDR) FSR;
107 extern __sfr __at (PORTA_ADDR) PORTA;
108 extern __sfr __at (PORTB_ADDR) PORTB;
109 extern __sfr __at (PCLATH_ADDR) PCLATH;
110 extern __sfr __at (INTCON_ADDR) INTCON;
111 extern __sfr __at (PIR1_ADDR) PIR1;
112 extern __sfr __at (CMCON_ADDR) CMCON;
114 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
115 extern __sfr __at (TRISA_ADDR) TRISA;
116 extern __sfr __at (TRISB_ADDR) TRISB;
117 extern __sfr __at (PIE1_ADDR) PIE1;
118 extern __sfr __at (PCON_ADDR) PCON;
119 extern __sfr __at (LINPRT_ADDR) LINPRT;
120 extern __sfr __at (VRCON_ADDR) VRCON;
122 //----- STATUS Bits --------------------------------------------------------
125 //----- INTCON Bits --------------------------------------------------------
128 //----- PORTA Bits --------------------------------------------------------
130 //----- PIR1 Bits ----------------------------------------------------------
133 //----- CMCON Bits ---------------------------------------------------------
136 //----- OPTION Bits --------------------------------------------------------
139 //----- PIE1 Bits ----------------------------------------------------------
142 //----- PCON Bits ----------------------------------------------------------
145 //----- VRCON Bits ---------------------------------------------------------
148 //----- LINPRT Bits ----------------------------------------------------------
151 //==========================================================================
155 //==========================================================================
158 // __BADRAM H'07'-H'09', H'0D'-H'1E'
159 // __BADRAM H'87'-H'89', H'8D', H'8F', H'91'-H'9E'
160 // __BADRAM H'C0'-H'EF'
162 //==========================================================================
164 // Configuration Bits
166 //==========================================================================
168 #define _BODEN_ON 0x3FFF
169 #define _BODEN_OFF 0x3FBF
170 #define _CP_ALL 0x00CF
171 #define _CP_75 0x15DF
172 #define _CP_50 0x2AEF
173 #define _CP_OFF 0x3FFF
174 #define _PWRTE_OFF 0x3FFF
175 #define _PWRTE_ON 0x3FF7
176 #define _WDT_ON 0x3FFF
177 #define _WDT_OFF 0x3FFB
178 #define _LP_OSC 0x3FFC
179 #define _XT_OSC 0x3FFD
180 #define _HS_OSC 0x3FFE
181 #define _RC_OSC 0x3FFF
185 // ----- CMCON bits --------------------
194 unsigned char C1OUT:1;
195 unsigned char C2OUT:1;
198 extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;
200 #ifndef NO_BIT_DEFINES
201 #define CM0 CMCON_bits.CM0
202 #define CM1 CMCON_bits.CM1
203 #define CM2 CMCON_bits.CM2
204 #define CIS CMCON_bits.CIS
205 #define C1OUT CMCON_bits.C1OUT
206 #define C2OUT CMCON_bits.C2OUT
207 #endif /* NO_BIT_DEFINES */
209 // ----- INTCON bits --------------------
212 unsigned char RBIF:1;
213 unsigned char INTF:1;
214 unsigned char T0IF:1;
215 unsigned char RBIE:1;
216 unsigned char INTE:1;
217 unsigned char T0IE:1;
218 unsigned char PEIE:1;
222 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
224 #ifndef NO_BIT_DEFINES
225 #define RBIF INTCON_bits.RBIF
226 #define INTF INTCON_bits.INTF
227 #define T0IF INTCON_bits.T0IF
228 #define RBIE INTCON_bits.RBIE
229 #define INTE INTCON_bits.INTE
230 #define T0IE INTCON_bits.T0IE
231 #define PEIE INTCON_bits.PEIE
232 #define GIE INTCON_bits.GIE
233 #endif /* NO_BIT_DEFINES */
235 // ----- LINPRT bits --------------------
238 unsigned char LINVDD:1;
240 unsigned char LINTX:1;
248 extern volatile __LINPRT_bits_t __at(LINPRT_ADDR) LINPRT_bits;
250 #ifndef NO_BIT_DEFINES
251 #define LINVDD LINPRT_bits.LINVDD
252 #define LINTX LINPRT_bits.LINTX
253 #endif /* NO_BIT_DEFINES */
255 // ----- OPTION_REG bits --------------------
262 unsigned char T0SE:1;
263 unsigned char T0CS:1;
264 unsigned char INTEDG:1;
265 unsigned char NOT_RBPU:1;
267 } __OPTION_REG_bits_t;
268 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
270 #ifndef NO_BIT_DEFINES
271 #define PS0 OPTION_REG_bits.PS0
272 #define PS1 OPTION_REG_bits.PS1
273 #define PS2 OPTION_REG_bits.PS2
274 #define PSA OPTION_REG_bits.PSA
275 #define T0SE OPTION_REG_bits.T0SE
276 #define T0CS OPTION_REG_bits.T0CS
277 #define INTEDG OPTION_REG_bits.INTEDG
278 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
279 #endif /* NO_BIT_DEFINES */
281 // ----- PCON bits --------------------
284 unsigned char NOT_BO:1;
285 unsigned char NOT_POR:1;
294 unsigned char NOT_BOR:1;
304 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
306 #ifndef NO_BIT_DEFINES
307 #define NOT_BO PCON_bits.NOT_BO
308 #define NOT_BOR PCON_bits.NOT_BOR
309 #define NOT_POR PCON_bits.NOT_POR
310 #endif /* NO_BIT_DEFINES */
312 // ----- PIE1 bits --------------------
321 unsigned char CMIE:1;
325 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
327 #ifndef NO_BIT_DEFINES
328 #define CMIE PIE1_bits.CMIE
329 #endif /* NO_BIT_DEFINES */
331 // ----- PIR1 bits --------------------
340 unsigned char CMIF:1;
344 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
346 #ifndef NO_BIT_DEFINES
347 #define CMIF PIR1_bits.CMIF
348 #endif /* NO_BIT_DEFINES */
350 // ----- PORTA bits --------------------
354 unsigned char LINRX:1;
363 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
365 #ifndef NO_BIT_DEFINES
366 #define LINRX PORTA_bits.LINRX
367 #endif /* NO_BIT_DEFINES */
369 // ----- PORTB bits --------------------
382 extern volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
384 #ifndef NO_BIT_DEFINES
385 #define RB0 PORTB_bits.RB0
386 #define RB1 PORTB_bits.RB1
387 #define RB2 PORTB_bits.RB2
388 #define RB3 PORTB_bits.RB3
389 #define RB4 PORTB_bits.RB4
390 #define RB5 PORTB_bits.RB5
391 #define RB6 PORTB_bits.RB6
392 #define RB7 PORTB_bits.RB7
393 #endif /* NO_BIT_DEFINES */
395 // ----- STATUS bits --------------------
401 unsigned char NOT_PD:1;
402 unsigned char NOT_TO:1;
408 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
410 #ifndef NO_BIT_DEFINES
411 #define C STATUS_bits.C
412 #define DC STATUS_bits.DC
413 #define Z STATUS_bits.Z
414 #define NOT_PD STATUS_bits.NOT_PD
415 #define NOT_TO STATUS_bits.NOT_TO
416 #define RP0 STATUS_bits.RP0
417 #define RP1 STATUS_bits.RP1
418 #define IRP STATUS_bits.IRP
419 #endif /* NO_BIT_DEFINES */
421 // ----- TRISB bits --------------------
424 unsigned char TRISB0:1;
425 unsigned char TRISB1:1;
426 unsigned char TRISB2:1;
427 unsigned char TRISB3:1;
428 unsigned char TRISB4:1;
429 unsigned char TRISB5:1;
430 unsigned char TRISB6:1;
431 unsigned char TRISB7:1;
434 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
436 #ifndef NO_BIT_DEFINES
437 #define TRISB0 TRISB_bits.TRISB0
438 #define TRISB1 TRISB_bits.TRISB1
439 #define TRISB2 TRISB_bits.TRISB2
440 #define TRISB3 TRISB_bits.TRISB3
441 #define TRISB4 TRISB_bits.TRISB4
442 #define TRISB5 TRISB_bits.TRISB5
443 #define TRISB6 TRISB_bits.TRISB6
444 #define TRISB7 TRISB_bits.TRISB7
445 #endif /* NO_BIT_DEFINES */
447 // ----- VRCON bits --------------------
456 unsigned char VROE:1;
457 unsigned char VREN:1;
460 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
462 #ifndef NO_BIT_DEFINES
463 #define VR0 VRCON_bits.VR0
464 #define VR1 VRCON_bits.VR1
465 #define VR2 VRCON_bits.VR2
466 #define VR3 VRCON_bits.VR3
467 #define VRR VRCON_bits.VRR
468 #define VROE VRCON_bits.VROE
469 #define VREN VRCON_bits.VREN
470 #endif /* NO_BIT_DEFINES */