2 // Register Declarations for Microchip 12F683 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define GPIO_ADDR 0x0005
34 #define PCLATH_ADDR 0x000A
35 #define INTCON_ADDR 0x000B
36 #define PIR1_ADDR 0x000C
37 #define TMR1L_ADDR 0x000E
38 #define TMR1H_ADDR 0x000F
39 #define T1CON_ADDR 0x0010
40 #define TMR2_ADDR 0x0011
41 #define T2CON_ADDR 0x0012
42 #define CCPR1L_ADDR 0x0013
43 #define CCPR1H_ADDR 0x0014
44 #define CCP1CON_ADDR 0x0015
45 #define WDTCON_ADDR 0x0018
46 #define CMCON0_ADDR 0x0019
47 #define CMCON1_ADDR 0x001A
48 #define ADRESH_ADDR 0x001E
49 #define ADCON0_ADDR 0x001F
50 #define OPTION_REG_ADDR 0x0081
51 #define TRISIO_ADDR 0x0085
52 #define PIE1_ADDR 0x008C
53 #define PCON_ADDR 0x008E
54 #define OSCCON_ADDR 0x008F
55 #define OSCTUNE_ADDR 0x0090
56 #define PR2_ADDR 0x0092
57 #define WPU_ADDR 0x0095
58 #define WPUA_ADDR 0x0095
59 #define IOC_ADDR 0x0096
60 #define IOCA_ADDR 0x0096
61 #define VRCON_ADDR 0x0099
62 #define EEDATA_ADDR 0x009A
63 #define EEDAT_ADDR 0x009A
64 #define EEADR_ADDR 0x009B
65 #define EECON1_ADDR 0x009C
66 #define EECON2_ADDR 0x009D
67 #define ADRESL_ADDR 0x009E
68 #define ANSEL_ADDR 0x009F
71 // Memory organization.
77 // P12F683.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
80 // This header file defines configurations, registers, and other useful bits of
81 // information for the PIC12F683 microcontroller. These names are taken to match
82 // the data sheets as closely as possible.
84 // Note that the processor must be selected before this file is
85 // included. The processor may be selected the following ways:
87 // 1. Command line switch:
88 // C:\ MPASM MYFILE.ASM /PIC16F684
89 // 2. LIST directive in the source file
91 // 3. Processor Type entry in the MPASM full-screen interface
93 //==========================================================================
97 //==========================================================================
98 //1.00 12/09/03 Original
100 //==========================================================================
104 //==========================================================================
107 // MESSG "Processor-header file mismatch. Verify selected processor."
110 //==========================================================================
112 // Register Definitions
114 //==========================================================================
119 //----- Register Files------------------------------------------------------
121 extern __sfr __at (INDF_ADDR) INDF;
122 extern __sfr __at (TMR0_ADDR) TMR0;
123 extern __sfr __at (PCL_ADDR) PCL;
124 extern __sfr __at (STATUS_ADDR) STATUS;
125 extern __sfr __at (FSR_ADDR) FSR;
126 extern __sfr __at (GPIO_ADDR) GPIO;
128 extern __sfr __at (PCLATH_ADDR) PCLATH;
129 extern __sfr __at (INTCON_ADDR) INTCON;
130 extern __sfr __at (PIR1_ADDR) PIR1;
132 extern __sfr __at (TMR1L_ADDR) TMR1L;
133 extern __sfr __at (TMR1H_ADDR) TMR1H;
134 extern __sfr __at (T1CON_ADDR) T1CON;
135 extern __sfr __at (TMR2_ADDR) TMR2;
136 extern __sfr __at (T2CON_ADDR) T2CON;
137 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
138 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
139 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
141 extern __sfr __at (WDTCON_ADDR) WDTCON;
142 extern __sfr __at (CMCON0_ADDR) CMCON0;
143 extern __sfr __at (CMCON1_ADDR) CMCON1;
145 extern __sfr __at (ADRESH_ADDR) ADRESH;
146 extern __sfr __at (ADCON0_ADDR) ADCON0;
148 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
150 extern __sfr __at (TRISIO_ADDR) TRISIO;
152 extern __sfr __at (PIE1_ADDR) PIE1;
154 extern __sfr __at (PCON_ADDR) PCON;
155 extern __sfr __at (OSCCON_ADDR) OSCCON;
156 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
158 extern __sfr __at (PR2_ADDR) PR2;
160 extern __sfr __at (WPU_ADDR) WPU;
161 extern __sfr __at (WPUA_ADDR) WPUA;
162 extern __sfr __at (IOC_ADDR) IOC;
163 extern __sfr __at (IOCA_ADDR) IOCA;
165 extern __sfr __at (VRCON_ADDR) VRCON;
166 extern __sfr __at (EEDATA_ADDR) EEDATA;
167 extern __sfr __at (EEDAT_ADDR) EEDAT;
168 extern __sfr __at (EEADR_ADDR) EEADR;
169 extern __sfr __at (EECON1_ADDR) EECON1;
170 extern __sfr __at (EECON2_ADDR) EECON2;
171 extern __sfr __at (ADRESL_ADDR) ADRESL;
172 extern __sfr __at (ANSEL_ADDR) ANSEL;
175 //----- STATUS Bits --------------------------------------------------------
178 //----- INTCON Bits --------------------------------------------------------
181 //----- PIR1 Bits ----------------------------------------------------------
184 //----- T1CON Bits ---------------------------------------------------------
187 //----- T2CON Bits ---------------------------------------------------------
190 //----- CCP1CON Bits -------------------------------------------------------
193 //----- WDTCON Bits --------------------------------------------------------
196 //----- COMCON0 Bits -------------------------------------------------------
199 //----- COMCON1 Bits -------------------------------------------------------
202 //----- ADCON0 Bits --------------------------------------------------------
205 //----- OPTION Bits --------------------------------------------------------
209 //----- PIE1 Bits ----------------------------------------------------------
212 //----- PCON Bits ----------------------------------------------------------
215 //----- OSCCON Bits --------------------------------------------------------
218 //----- OSCTUNE Bits -------------------------------------------------------
222 //----- IOC --------------------------------------------------------------
225 //----- IOCA --------------------------------------------------------------
228 //----- VRCON Bits ---------------------------------------------------------
231 //----- EECON1 -------------------------------------------------------------
234 //----- ANSEL --------------------------------------------------------------
237 //==========================================================================
241 //==========================================================================
244 // __BADRAM H'06', H'08'-H'09', H'0D', H'1B'-H'1D'
245 // __BADRAM H'86', H'88'-H'89', H'8D', H'93'-H'94', H'97'-H'98', H'C0'-H'EF'
247 //==========================================================================
249 // Configuration Bits
251 //==========================================================================
253 #define _FCMEN_ON 0x3FFF
254 #define _FCMEN_OFF 0x37FF
255 #define _IESO_ON 0x3FFF
256 #define _IESO_OFF 0x3BFF
257 #define _BOD_ON 0x3FFF
258 #define _BOD_NSLEEP 0x3EFF
259 #define _BOD_SBODEN 0x3DFF
260 #define _BOD_OFF 0x3CFF
261 #define _CPD_ON 0x3F7F
262 #define _CPD_OFF 0x3FFF
263 #define _CP_ON 0x3FBF
264 #define _CP_OFF 0x3FFF
265 #define _MCLRE_ON 0x3FFF
266 #define _MCLRE_OFF 0x3FDF
267 #define _PWRTE_OFF 0x3FFF
268 #define _PWRTE_ON 0x3FEF
269 #define _WDT_ON 0x3FFF
270 #define _WDT_OFF 0x3FF7
271 #define _LP_OSC 0x3FF8
272 #define _XT_OSC 0x3FF9
273 #define _HS_OSC 0x3FFA
274 #define _EC_OSC 0x3FFB
275 #define _INTRC_OSC_NOCLKOUT 0x3FFC
276 #define _INTOSCIO 0x3FFC
277 #define _INTRC_OSC_CLKOUT 0x3FFD
278 #define _INTOSC 0x3FFD
279 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
280 #define _EXTRCIO 0x3FFE
281 #define _EXTRC_OSC_CLKOUT 0x3FFF
282 #define _EXTRC 0x3FFF
286 // ----- ADCON0 bits --------------------
289 unsigned char ADON:1;
291 unsigned char CHS0:1;
292 unsigned char CHS1:1;
293 unsigned char CHS2:1;
295 unsigned char VCFG:1;
296 unsigned char ADFM:1;
300 unsigned char NOT_DONE:1;
310 unsigned char GO_DONE:1;
319 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
321 #define ADON ADCON0_bits.ADON
322 #define GO ADCON0_bits.GO
323 #define NOT_DONE ADCON0_bits.NOT_DONE
324 #define GO_DONE ADCON0_bits.GO_DONE
325 #define CHS0 ADCON0_bits.CHS0
326 #define CHS1 ADCON0_bits.CHS1
327 #define CHS2 ADCON0_bits.CHS2
328 #define VCFG ADCON0_bits.VCFG
329 #define ADFM ADCON0_bits.ADFM
331 // ----- ANSEL bits --------------------
334 unsigned char ANS0:1;
335 unsigned char ANS1:1;
336 unsigned char ANS2:1;
337 unsigned char ANS3:1;
338 unsigned char ADCS0:1;
339 unsigned char ADCS1:1;
340 unsigned char ADCS2:1;
344 extern volatile __ANSEL_bits_t __at(ANSEL_ADDR) ANSEL_bits;
346 #define ANS0 ANSEL_bits.ANS0
347 #define ANS1 ANSEL_bits.ANS1
348 #define ANS2 ANSEL_bits.ANS2
349 #define ANS3 ANSEL_bits.ANS3
350 #define ADCS0 ANSEL_bits.ADCS0
351 #define ADCS1 ANSEL_bits.ADCS1
352 #define ADCS2 ANSEL_bits.ADCS2
354 // ----- CCP1CON bits --------------------
357 unsigned char CCP1M0:1;
358 unsigned char CCP1M1:1;
359 unsigned char CCP1M2:1;
360 unsigned char CCP1M3:1;
361 unsigned char DC1B0:1;
362 unsigned char DC1B1:1;
367 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
369 #define CCP1M0 CCP1CON_bits.CCP1M0
370 #define CCP1M1 CCP1CON_bits.CCP1M1
371 #define CCP1M2 CCP1CON_bits.CCP1M2
372 #define CCP1M3 CCP1CON_bits.CCP1M3
373 #define DC1B0 CCP1CON_bits.DC1B0
374 #define DC1B1 CCP1CON_bits.DC1B1
376 // ----- CMCON0 bits --------------------
383 unsigned char CINV:1;
385 unsigned char COUT:1;
389 extern volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits;
391 #define CM0 CMCON0_bits.CM0
392 #define CM1 CMCON0_bits.CM1
393 #define CM2 CMCON0_bits.CM2
394 #define CIS CMCON0_bits.CIS
395 #define CINV CMCON0_bits.CINV
396 #define COUT CMCON0_bits.COUT
398 // ----- CMCON1 bits --------------------
401 unsigned char CMSYNC:1;
402 unsigned char T1GSS:1;
411 extern volatile __CMCON1_bits_t __at(CMCON1_ADDR) CMCON1_bits;
413 #define CMSYNC CMCON1_bits.CMSYNC
414 #define T1GSS CMCON1_bits.T1GSS
416 // ----- EECON1 bits --------------------
421 unsigned char WREN:1;
422 unsigned char WRERR:1;
429 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
431 #define RD EECON1_bits.RD
432 #define WR EECON1_bits.WR
433 #define WREN EECON1_bits.WREN
434 #define WRERR EECON1_bits.WRERR
436 // ----- INTCON bits --------------------
439 unsigned char GPIF:1;
440 unsigned char INTF:1;
441 unsigned char T0IF:1;
442 unsigned char GPIE:1;
443 unsigned char INTE:1;
444 unsigned char T0IE:1;
445 unsigned char PEIE:1;
449 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
451 #define GPIF INTCON_bits.GPIF
452 #define INTF INTCON_bits.INTF
453 #define T0IF INTCON_bits.T0IF
454 #define GPIE INTCON_bits.GPIE
455 #define INTE INTCON_bits.INTE
456 #define T0IE INTCON_bits.T0IE
457 #define PEIE INTCON_bits.PEIE
458 #define GIE INTCON_bits.GIE
460 // ----- IOC bits --------------------
463 unsigned char IOC0:1;
464 unsigned char IOC1:1;
465 unsigned char IOC2:1;
466 unsigned char IOC3:1;
467 unsigned char IOC4:1;
468 unsigned char IOC5:1;
473 extern volatile __IOC_bits_t __at(IOC_ADDR) IOC_bits;
475 #define IOC0 IOC_bits.IOC0
476 #define IOC1 IOC_bits.IOC1
477 #define IOC2 IOC_bits.IOC2
478 #define IOC3 IOC_bits.IOC3
479 #define IOC4 IOC_bits.IOC4
480 #define IOC5 IOC_bits.IOC5
482 // ----- IOCA bits --------------------
485 unsigned char IOCA0:1;
486 unsigned char IOCA1:1;
487 unsigned char IOCA2:1;
488 unsigned char IOCA3:1;
489 unsigned char IOCA4:1;
490 unsigned char IOCA5:1;
495 extern volatile __IOCA_bits_t __at(IOCA_ADDR) IOCA_bits;
497 #define IOCA0 IOCA_bits.IOCA0
498 #define IOCA1 IOCA_bits.IOCA1
499 #define IOCA2 IOCA_bits.IOCA2
500 #define IOCA3 IOCA_bits.IOCA3
501 #define IOCA4 IOCA_bits.IOCA4
502 #define IOCA5 IOCA_bits.IOCA5
504 // ----- OPTION_REG bits --------------------
511 unsigned char T0SE:1;
512 unsigned char T0CS:1;
513 unsigned char INTEDG:1;
514 unsigned char NOT_GPPU:1;
516 } __OPTION_REG_bits_t;
517 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
519 #define PS0 OPTION_REG_bits.PS0
520 #define PS1 OPTION_REG_bits.PS1
521 #define PS2 OPTION_REG_bits.PS2
522 #define PSA OPTION_REG_bits.PSA
523 #define T0SE OPTION_REG_bits.T0SE
524 #define T0CS OPTION_REG_bits.T0CS
525 #define INTEDG OPTION_REG_bits.INTEDG
526 #define NOT_GPPU OPTION_REG_bits.NOT_GPPU
528 // ----- OSCCON bits --------------------
534 unsigned char OSTS:1;
535 unsigned char IRCF0:1;
536 unsigned char IRCF1:1;
537 unsigned char IRCF2:1;
541 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
543 #define SCS OSCCON_bits.SCS
544 #define LTS OSCCON_bits.LTS
545 #define HTS OSCCON_bits.HTS
546 #define OSTS OSCCON_bits.OSTS
547 #define IRCF0 OSCCON_bits.IRCF0
548 #define IRCF1 OSCCON_bits.IRCF1
549 #define IRCF2 OSCCON_bits.IRCF2
551 // ----- OSCTUNE bits --------------------
554 unsigned char TUN0:1;
555 unsigned char TUN1:1;
556 unsigned char TUN2:1;
557 unsigned char TUN3:1;
558 unsigned char TUN4:1;
564 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
566 #define TUN0 OSCTUNE_bits.TUN0
567 #define TUN1 OSCTUNE_bits.TUN1
568 #define TUN2 OSCTUNE_bits.TUN2
569 #define TUN3 OSCTUNE_bits.TUN3
570 #define TUN4 OSCTUNE_bits.TUN4
572 // ----- PCON bits --------------------
575 unsigned char NOT_BOD:1;
576 unsigned char NOT_POR:1;
579 unsigned char SBODEN:1;
580 unsigned char ULPWUE:1;
585 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
587 #define NOT_BOD PCON_bits.NOT_BOD
588 #define NOT_POR PCON_bits.NOT_POR
589 #define SBODEN PCON_bits.SBODEN
590 #define ULPWUE PCON_bits.ULPWUE
592 // ----- PIE1 bits --------------------
595 unsigned char T1IE:1;
596 unsigned char T2IE:1;
597 unsigned char OSFIE:1;
598 unsigned char CMIE:1;
600 unsigned char CCP1IE:1;
601 unsigned char ADIE:1;
602 unsigned char EEIE:1;
605 unsigned char TMR1IE:1;
606 unsigned char TMR2IE:1;
615 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
617 #define T1IE PIE1_bits.T1IE
618 #define TMR1IE PIE1_bits.TMR1IE
619 #define T2IE PIE1_bits.T2IE
620 #define TMR2IE PIE1_bits.TMR2IE
621 #define OSFIE PIE1_bits.OSFIE
622 #define CMIE PIE1_bits.CMIE
623 #define CCP1IE PIE1_bits.CCP1IE
624 #define ADIE PIE1_bits.ADIE
625 #define EEIE PIE1_bits.EEIE
627 // ----- PIR1 bits --------------------
630 unsigned char T1IF:1;
631 unsigned char T2IF:1;
632 unsigned char OSFIF:1;
633 unsigned char CMIF:1;
635 unsigned char CCP1IF:1;
636 unsigned char ADIF:1;
637 unsigned char EEIF:1;
640 unsigned char TMR1IF:1;
641 unsigned char TMR2IF:1;
650 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
652 #define T1IF PIR1_bits.T1IF
653 #define TMR1IF PIR1_bits.TMR1IF
654 #define T2IF PIR1_bits.T2IF
655 #define TMR2IF PIR1_bits.TMR2IF
656 #define OSFIF PIR1_bits.OSFIF
657 #define CMIF PIR1_bits.CMIF
658 #define CCP1IF PIR1_bits.CCP1IF
659 #define ADIF PIR1_bits.ADIF
660 #define EEIF PIR1_bits.EEIF
662 // ----- STATUS bits --------------------
668 unsigned char NOT_PD:1;
669 unsigned char NOT_TO:1;
675 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
677 #define C STATUS_bits.C
678 #define DC STATUS_bits.DC
679 #define Z STATUS_bits.Z
680 #define NOT_PD STATUS_bits.NOT_PD
681 #define NOT_TO STATUS_bits.NOT_TO
682 #define RP0 STATUS_bits.RP0
683 #define RP1 STATUS_bits.RP1
684 #define IRP STATUS_bits.IRP
686 // ----- T1CON bits --------------------
689 unsigned char TMR1ON:1;
690 unsigned char TMR1CS:1;
691 unsigned char NOT_T1SYNC:1;
692 unsigned char T1OSCEN:1;
693 unsigned char T1CKPS0:1;
694 unsigned char T1CKPS1:1;
695 unsigned char T1GE:1;
696 unsigned char T1GINV:1;
699 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
701 #define TMR1ON T1CON_bits.TMR1ON
702 #define TMR1CS T1CON_bits.TMR1CS
703 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
704 #define T1OSCEN T1CON_bits.T1OSCEN
705 #define T1CKPS0 T1CON_bits.T1CKPS0
706 #define T1CKPS1 T1CON_bits.T1CKPS1
707 #define T1GE T1CON_bits.T1GE
708 #define T1GINV T1CON_bits.T1GINV
710 // ----- T2CON bits --------------------
713 unsigned char T2CKPS0:1;
714 unsigned char T2CKPS1:1;
715 unsigned char TMR2ON:1;
716 unsigned char TOUTPS0:1;
717 unsigned char TOUTPS1:1;
718 unsigned char TOUTPS2:1;
719 unsigned char TOUTPS3:1;
723 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
725 #define T2CKPS0 T2CON_bits.T2CKPS0
726 #define T2CKPS1 T2CON_bits.T2CKPS1
727 #define TMR2ON T2CON_bits.TMR2ON
728 #define TOUTPS0 T2CON_bits.TOUTPS0
729 #define TOUTPS1 T2CON_bits.TOUTPS1
730 #define TOUTPS2 T2CON_bits.TOUTPS2
731 #define TOUTPS3 T2CON_bits.TOUTPS3
733 // ----- VRCON bits --------------------
743 unsigned char VREN:1;
746 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
748 #define VR0 VRCON_bits.VR0
749 #define VR1 VRCON_bits.VR1
750 #define VR2 VRCON_bits.VR2
751 #define VR3 VRCON_bits.VR3
752 #define VRR VRCON_bits.VRR
753 #define VREN VRCON_bits.VREN
755 // ----- WDTCON bits --------------------
758 unsigned char SWDTEN:1;
759 unsigned char WDTPS0:1;
760 unsigned char WDTPS1:1;
761 unsigned char WDTPS2:1;
762 unsigned char WDTPS3:1;
768 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
770 #define SWDTEN WDTCON_bits.SWDTEN
771 #define WDTPS0 WDTCON_bits.WDTPS0
772 #define WDTPS1 WDTCON_bits.WDTPS1
773 #define WDTPS2 WDTCON_bits.WDTPS2
774 #define WDTPS3 WDTCON_bits.WDTPS3