2 // Register Declarations for Microchip 12F683 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define GPIO_ADDR 0x0005
34 #define PCLATH_ADDR 0x000A
35 #define INTCON_ADDR 0x000B
36 #define PIR1_ADDR 0x000C
37 #define TMR1L_ADDR 0x000E
38 #define TMR1H_ADDR 0x000F
39 #define T1CON_ADDR 0x0010
40 #define TMR2_ADDR 0x0011
41 #define T2CON_ADDR 0x0012
42 #define CCPR1L_ADDR 0x0013
43 #define CCPR1H_ADDR 0x0014
44 #define CCP1CON_ADDR 0x0015
45 #define WDTCON_ADDR 0x0018
46 #define CMCON0_ADDR 0x0019
47 #define CMCON1_ADDR 0x001A
48 #define ADRESH_ADDR 0x001E
49 #define ADCON0_ADDR 0x001F
50 #define OPTION_REG_ADDR 0x0081
51 #define TRISIO_ADDR 0x0085
52 #define PIE1_ADDR 0x008C
53 #define PCON_ADDR 0x008E
54 #define OSCCON_ADDR 0x008F
55 #define OSCTUNE_ADDR 0x0090
56 #define PR2_ADDR 0x0092
57 #define WPU_ADDR 0x0095
58 #define WPUA_ADDR 0x0095
59 #define IOC_ADDR 0x0096
60 #define IOCA_ADDR 0x0096
61 #define VRCON_ADDR 0x0099
62 #define EEDATA_ADDR 0x009A
63 #define EEDAT_ADDR 0x009A
64 #define EEADR_ADDR 0x009B
65 #define EECON1_ADDR 0x009C
66 #define EECON2_ADDR 0x009D
67 #define ADRESL_ADDR 0x009E
68 #define ANSEL_ADDR 0x009F
71 // Memory organization.
74 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
75 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
76 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
77 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
78 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
79 #pragma memmap GPIO_ADDR GPIO_ADDR SFR 0x000 // GPIO
80 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
81 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
82 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
83 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
84 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
85 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
86 #pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
87 #pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
88 #pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
89 #pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
90 #pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
91 #pragma memmap WDTCON_ADDR WDTCON_ADDR SFR 0x000 // WDTCON
92 #pragma memmap CMCON0_ADDR CMCON0_ADDR SFR 0x000 // CMCON0
93 #pragma memmap CMCON1_ADDR CMCON1_ADDR SFR 0x000 // CMCON1
94 #pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH
95 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
96 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
97 #pragma memmap TRISIO_ADDR TRISIO_ADDR SFR 0x000 // TRISIO
98 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
99 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
100 #pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON
101 #pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE
102 #pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
103 #pragma memmap WPU_ADDR WPU_ADDR SFR 0x000 // WPU
104 #pragma memmap WPUA_ADDR WPUA_ADDR SFR 0x000 // WPUA
105 #pragma memmap IOC_ADDR IOC_ADDR SFR 0x000 // IOC
106 #pragma memmap IOCA_ADDR IOCA_ADDR SFR 0x000 // IOCA
107 #pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON
108 #pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA
109 #pragma memmap EEDAT_ADDR EEDAT_ADDR SFR 0x000 // EEDAT
110 #pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR
111 #pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1
112 #pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2
113 #pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL
114 #pragma memmap ANSEL_ADDR ANSEL_ADDR SFR 0x000 // ANSEL
118 // P12F683.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
121 // This header file defines configurations, registers, and other useful bits of
122 // information for the PIC12F683 microcontroller. These names are taken to match
123 // the data sheets as closely as possible.
125 // Note that the processor must be selected before this file is
126 // included. The processor may be selected the following ways:
128 // 1. Command line switch:
129 // C:\ MPASM MYFILE.ASM /PIC16F684
130 // 2. LIST directive in the source file
132 // 3. Processor Type entry in the MPASM full-screen interface
134 //==========================================================================
138 //==========================================================================
139 //1.00 12/09/03 Original
141 //==========================================================================
145 //==========================================================================
148 // MESSG "Processor-header file mismatch. Verify selected processor."
151 //==========================================================================
153 // Register Definitions
155 //==========================================================================
160 //----- Register Files------------------------------------------------------
162 extern __data __at (INDF_ADDR) volatile char INDF;
163 extern __sfr __at (TMR0_ADDR) TMR0;
164 extern __data __at (PCL_ADDR) volatile char PCL;
165 extern __sfr __at (STATUS_ADDR) STATUS;
166 extern __sfr __at (FSR_ADDR) FSR;
167 extern __sfr __at (GPIO_ADDR) GPIO;
169 extern __sfr __at (PCLATH_ADDR) PCLATH;
170 extern __sfr __at (INTCON_ADDR) INTCON;
171 extern __sfr __at (PIR1_ADDR) PIR1;
173 extern __sfr __at (TMR1L_ADDR) TMR1L;
174 extern __sfr __at (TMR1H_ADDR) TMR1H;
175 extern __sfr __at (T1CON_ADDR) T1CON;
176 extern __sfr __at (TMR2_ADDR) TMR2;
177 extern __sfr __at (T2CON_ADDR) T2CON;
178 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
179 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
180 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
182 extern __sfr __at (WDTCON_ADDR) WDTCON;
183 extern __sfr __at (CMCON0_ADDR) CMCON0;
184 extern __sfr __at (CMCON1_ADDR) CMCON1;
186 extern __sfr __at (ADRESH_ADDR) ADRESH;
187 extern __sfr __at (ADCON0_ADDR) ADCON0;
189 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
191 extern __sfr __at (TRISIO_ADDR) TRISIO;
193 extern __sfr __at (PIE1_ADDR) PIE1;
195 extern __sfr __at (PCON_ADDR) PCON;
196 extern __sfr __at (OSCCON_ADDR) OSCCON;
197 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
199 extern __sfr __at (PR2_ADDR) PR2;
201 extern __sfr __at (WPU_ADDR) WPU;
202 extern __sfr __at (WPUA_ADDR) WPUA;
203 extern __sfr __at (IOC_ADDR) IOC;
204 extern __sfr __at (IOCA_ADDR) IOCA;
206 extern __sfr __at (VRCON_ADDR) VRCON;
207 extern __sfr __at (EEDATA_ADDR) EEDATA;
208 extern __sfr __at (EEDAT_ADDR) EEDAT;
209 extern __sfr __at (EEADR_ADDR) EEADR;
210 extern __sfr __at (EECON1_ADDR) EECON1;
211 extern __sfr __at (EECON2_ADDR) EECON2;
212 extern __sfr __at (ADRESL_ADDR) ADRESL;
213 extern __sfr __at (ANSEL_ADDR) ANSEL;
216 //----- STATUS Bits --------------------------------------------------------
219 //----- INTCON Bits --------------------------------------------------------
222 //----- PIR1 Bits ----------------------------------------------------------
225 //----- T1CON Bits ---------------------------------------------------------
228 //----- T2CON Bits ---------------------------------------------------------
231 //----- CCP1CON Bits -------------------------------------------------------
234 //----- WDTCON Bits --------------------------------------------------------
237 //----- CMCON0 Bits -------------------------------------------------------
240 //----- CMCON1 Bits -------------------------------------------------------
243 //----- ADCON0 Bits --------------------------------------------------------
246 //----- OPTION Bits --------------------------------------------------------
250 //----- PIE1 Bits ----------------------------------------------------------
253 //----- PCON Bits ----------------------------------------------------------
256 //----- OSCCON Bits --------------------------------------------------------
259 //----- OSCTUNE Bits -------------------------------------------------------
263 //----- IOC --------------------------------------------------------------
266 //----- IOCA --------------------------------------------------------------
269 //----- VRCON Bits ---------------------------------------------------------
272 //----- EECON1 -------------------------------------------------------------
275 //----- ANSEL --------------------------------------------------------------
278 //==========================================================================
282 //==========================================================================
285 // __BADRAM H'06', H'08'-H'09', H'0D', H'1B'-H'1D'
286 // __BADRAM H'86', H'88'-H'89', H'8D', H'93'-H'94', H'97'-H'98', H'C0'-H'EF'
288 //==========================================================================
290 // Configuration Bits
292 //==========================================================================
294 #define _FCMEN_ON 0x3FFF
295 #define _FCMEN_OFF 0x37FF
296 #define _IESO_ON 0x3FFF
297 #define _IESO_OFF 0x3BFF
298 #define _BOD_ON 0x3FFF
299 #define _BOD_NSLEEP 0x3EFF
300 #define _BOD_SBODEN 0x3DFF
301 #define _BOD_OFF 0x3CFF
302 #define _CPD_ON 0x3F7F
303 #define _CPD_OFF 0x3FFF
304 #define _CP_ON 0x3FBF
305 #define _CP_OFF 0x3FFF
306 #define _MCLRE_ON 0x3FFF
307 #define _MCLRE_OFF 0x3FDF
308 #define _PWRTE_OFF 0x3FFF
309 #define _PWRTE_ON 0x3FEF
310 #define _WDT_ON 0x3FFF
311 #define _WDT_OFF 0x3FF7
312 #define _LP_OSC 0x3FF8
313 #define _XT_OSC 0x3FF9
314 #define _HS_OSC 0x3FFA
315 #define _EC_OSC 0x3FFB
316 #define _INTRC_OSC_NOCLKOUT 0x3FFC
317 #define _INTOSCIO 0x3FFC
318 #define _INTRC_OSC_CLKOUT 0x3FFD
319 #define _INTOSC 0x3FFD
320 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
321 #define _EXTRCIO 0x3FFE
322 #define _EXTRC_OSC_CLKOUT 0x3FFF
323 #define _EXTRC 0x3FFF
327 // ----- ADCON0 bits --------------------
330 unsigned char ADON:1;
332 unsigned char CHS0:1;
333 unsigned char CHS1:1;
334 unsigned char CHS2:1;
336 unsigned char VCFG:1;
337 unsigned char ADFM:1;
341 unsigned char NOT_DONE:1;
351 unsigned char GO_DONE:1;
360 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
362 #define ADON ADCON0_bits.ADON
363 #define GO ADCON0_bits.GO
364 #define NOT_DONE ADCON0_bits.NOT_DONE
365 #define GO_DONE ADCON0_bits.GO_DONE
366 #define CHS0 ADCON0_bits.CHS0
367 #define CHS1 ADCON0_bits.CHS1
368 #define CHS2 ADCON0_bits.CHS2
369 #define VCFG ADCON0_bits.VCFG
370 #define ADFM ADCON0_bits.ADFM
372 // ----- CCP1CON bits --------------------
375 unsigned char CCP1M0:1;
376 unsigned char CCP1M1:1;
377 unsigned char CCP1M2:1;
378 unsigned char CCP1M3:1;
379 unsigned char DC1B0:1;
380 unsigned char DC1B1:1;
385 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
387 #define CCP1M0 CCP1CON_bits.CCP1M0
388 #define CCP1M1 CCP1CON_bits.CCP1M1
389 #define CCP1M2 CCP1CON_bits.CCP1M2
390 #define CCP1M3 CCP1CON_bits.CCP1M3
391 #define DC1B0 CCP1CON_bits.DC1B0
392 #define DC1B1 CCP1CON_bits.DC1B1
394 // ----- CMCON0 bits --------------------
401 unsigned char CINV:1;
403 unsigned char COUT:1;
407 extern volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits;
409 #define CM0 CMCON0_bits.CM0
410 #define CM1 CMCON0_bits.CM1
411 #define CM2 CMCON0_bits.CM2
412 #define CIS CMCON0_bits.CIS
413 #define CINV CMCON0_bits.CINV
414 #define COUT CMCON0_bits.COUT
416 // ----- CMCON1 bits --------------------
419 unsigned char CMSYNC:1;
420 unsigned char T1GSS:1;
429 extern volatile __CMCON1_bits_t __at(CMCON1_ADDR) CMCON1_bits;
431 #define CMSYNC CMCON1_bits.CMSYNC
432 #define T1GSS CMCON1_bits.T1GSS
434 // ----- INTCON bits --------------------
437 unsigned char GPIF:1;
438 unsigned char INTF:1;
439 unsigned char T0IF:1;
440 unsigned char GPIE:1;
441 unsigned char INTE:1;
442 unsigned char T0IE:1;
443 unsigned char PEIE:1;
447 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
449 #define GPIF INTCON_bits.GPIF
450 #define INTF INTCON_bits.INTF
451 #define T0IF INTCON_bits.T0IF
452 #define GPIE INTCON_bits.GPIE
453 #define INTE INTCON_bits.INTE
454 #define T0IE INTCON_bits.T0IE
455 #define PEIE INTCON_bits.PEIE
456 #define GIE INTCON_bits.GIE
458 // ----- OPTION_REG bits --------------------
465 unsigned char T0SE:1;
466 unsigned char T0CS:1;
467 unsigned char INTEDG:1;
468 unsigned char NOT_GPPU:1;
470 } __OPTION_REG_bits_t;
471 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
473 #define PS0 OPTION_REG_bits.PS0
474 #define PS1 OPTION_REG_bits.PS1
475 #define PS2 OPTION_REG_bits.PS2
476 #define PSA OPTION_REG_bits.PSA
477 #define T0SE OPTION_REG_bits.T0SE
478 #define T0CS OPTION_REG_bits.T0CS
479 #define INTEDG OPTION_REG_bits.INTEDG
480 #define NOT_GPPU OPTION_REG_bits.NOT_GPPU
482 // ----- OSCCON bits --------------------
488 unsigned char OSTS:1;
489 unsigned char IRCF0:1;
490 unsigned char IRCF1:1;
491 unsigned char IRCF2:1;
495 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
497 #define SCS OSCCON_bits.SCS
498 #define LTS OSCCON_bits.LTS
499 #define HTS OSCCON_bits.HTS
500 #define OSTS OSCCON_bits.OSTS
501 #define IRCF0 OSCCON_bits.IRCF0
502 #define IRCF1 OSCCON_bits.IRCF1
503 #define IRCF2 OSCCON_bits.IRCF2
505 // ----- OSCTUNE bits --------------------
508 unsigned char TUN0:1;
509 unsigned char TUN1:1;
510 unsigned char TUN2:1;
511 unsigned char TUN3:1;
512 unsigned char TUN4:1;
513 unsigned char IOC5:1;
518 unsigned char IOC0:1;
519 unsigned char IOC1:1;
520 unsigned char IOC2:1;
521 unsigned char IOC3:1;
522 unsigned char IOC4:1;
523 unsigned char IOCA5:1;
528 unsigned char IOCA0:1;
529 unsigned char IOCA1:1;
530 unsigned char IOCA2:1;
531 unsigned char IOCA3:1;
532 unsigned char IOCA4:1;
538 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
540 #define TUN0 OSCTUNE_bits.TUN0
541 #define IOC0 OSCTUNE_bits.IOC0
542 #define IOCA0 OSCTUNE_bits.IOCA0
543 #define TUN1 OSCTUNE_bits.TUN1
544 #define IOC1 OSCTUNE_bits.IOC1
545 #define IOCA1 OSCTUNE_bits.IOCA1
546 #define TUN2 OSCTUNE_bits.TUN2
547 #define IOC2 OSCTUNE_bits.IOC2
548 #define IOCA2 OSCTUNE_bits.IOCA2
549 #define TUN3 OSCTUNE_bits.TUN3
550 #define IOC3 OSCTUNE_bits.IOC3
551 #define IOCA3 OSCTUNE_bits.IOCA3
552 #define TUN4 OSCTUNE_bits.TUN4
553 #define IOC4 OSCTUNE_bits.IOC4
554 #define IOCA4 OSCTUNE_bits.IOCA4
555 #define IOC5 OSCTUNE_bits.IOC5
556 #define IOCA5 OSCTUNE_bits.IOCA5
558 // ----- PCON bits --------------------
561 unsigned char NOT_BOD:1;
562 unsigned char NOT_POR:1;
565 unsigned char SBODEN:1;
566 unsigned char ULPWUE:1;
571 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
573 #define NOT_BOD PCON_bits.NOT_BOD
574 #define NOT_POR PCON_bits.NOT_POR
575 #define SBODEN PCON_bits.SBODEN
576 #define ULPWUE PCON_bits.ULPWUE
578 // ----- PIE1 bits --------------------
581 unsigned char T1IE:1;
582 unsigned char T2IE:1;
583 unsigned char OSFIE:1;
584 unsigned char CMIE:1;
586 unsigned char CCP1IE:1;
587 unsigned char ADIE:1;
588 unsigned char EEIE:1;
591 unsigned char TMR1IE:1;
592 unsigned char TMR2IE:1;
601 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
603 #define T1IE PIE1_bits.T1IE
604 #define TMR1IE PIE1_bits.TMR1IE
605 #define T2IE PIE1_bits.T2IE
606 #define TMR2IE PIE1_bits.TMR2IE
607 #define OSFIE PIE1_bits.OSFIE
608 #define CMIE PIE1_bits.CMIE
609 #define CCP1IE PIE1_bits.CCP1IE
610 #define ADIE PIE1_bits.ADIE
611 #define EEIE PIE1_bits.EEIE
613 // ----- PIR1 bits --------------------
616 unsigned char T1IF:1;
617 unsigned char T2IF:1;
618 unsigned char OSFIF:1;
619 unsigned char CMIF:1;
621 unsigned char CCP1IF:1;
622 unsigned char ADIF:1;
623 unsigned char EEIF:1;
626 unsigned char TMR1IF:1;
627 unsigned char TMR2IF:1;
636 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
638 #define T1IF PIR1_bits.T1IF
639 #define TMR1IF PIR1_bits.TMR1IF
640 #define T2IF PIR1_bits.T2IF
641 #define TMR2IF PIR1_bits.TMR2IF
642 #define OSFIF PIR1_bits.OSFIF
643 #define CMIF PIR1_bits.CMIF
644 #define CCP1IF PIR1_bits.CCP1IF
645 #define ADIF PIR1_bits.ADIF
646 #define EEIF PIR1_bits.EEIF
648 // ----- STATUS bits --------------------
654 unsigned char NOT_PD:1;
655 unsigned char NOT_TO:1;
661 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
663 #define C STATUS_bits.C
664 #define DC STATUS_bits.DC
665 #define Z STATUS_bits.Z
666 #define NOT_PD STATUS_bits.NOT_PD
667 #define NOT_TO STATUS_bits.NOT_TO
668 #define RP0 STATUS_bits.RP0
669 #define RP1 STATUS_bits.RP1
670 #define IRP STATUS_bits.IRP
672 // ----- T1CON bits --------------------
675 unsigned char TMR1ON:1;
676 unsigned char TMR1CS:1;
677 unsigned char NOT_T1SYNC:1;
678 unsigned char T1OSCEN:1;
679 unsigned char T1CKPS0:1;
680 unsigned char T1CKPS1:1;
681 unsigned char T1GE:1;
682 unsigned char T1GINV:1;
685 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
687 #define TMR1ON T1CON_bits.TMR1ON
688 #define TMR1CS T1CON_bits.TMR1CS
689 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
690 #define T1OSCEN T1CON_bits.T1OSCEN
691 #define T1CKPS0 T1CON_bits.T1CKPS0
692 #define T1CKPS1 T1CON_bits.T1CKPS1
693 #define T1GE T1CON_bits.T1GE
694 #define T1GINV T1CON_bits.T1GINV
696 // ----- T2CON bits --------------------
699 unsigned char T2CKPS0:1;
700 unsigned char T2CKPS1:1;
701 unsigned char TMR2ON:1;
702 unsigned char TOUTPS0:1;
703 unsigned char TOUTPS1:1;
704 unsigned char TOUTPS2:1;
705 unsigned char TOUTPS3:1;
709 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
711 #define T2CKPS0 T2CON_bits.T2CKPS0
712 #define T2CKPS1 T2CON_bits.T2CKPS1
713 #define TMR2ON T2CON_bits.TMR2ON
714 #define TOUTPS0 T2CON_bits.TOUTPS0
715 #define TOUTPS1 T2CON_bits.TOUTPS1
716 #define TOUTPS2 T2CON_bits.TOUTPS2
717 #define TOUTPS3 T2CON_bits.TOUTPS3
719 // ----- VRCON bits --------------------
726 unsigned char ADCS0:1;
728 unsigned char ADCS2:1;
729 unsigned char VREN:1;
734 unsigned char WREN:1;
735 unsigned char WRERR:1;
737 unsigned char ADCS1:1;
742 unsigned char ANS0:1;
743 unsigned char ANS1:1;
744 unsigned char ANS2:1;
745 unsigned char ANS3:1;
752 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
754 #define VR0 VRCON_bits.VR0
755 #define RD VRCON_bits.RD
756 #define ANS0 VRCON_bits.ANS0
757 #define VR1 VRCON_bits.VR1
758 #define WR VRCON_bits.WR
759 #define ANS1 VRCON_bits.ANS1
760 #define VR2 VRCON_bits.VR2
761 #define WREN VRCON_bits.WREN
762 #define ANS2 VRCON_bits.ANS2
763 #define VR3 VRCON_bits.VR3
764 #define WRERR VRCON_bits.WRERR
765 #define ANS3 VRCON_bits.ANS3
766 #define ADCS0 VRCON_bits.ADCS0
767 #define VRR VRCON_bits.VRR
768 #define ADCS1 VRCON_bits.ADCS1
769 #define ADCS2 VRCON_bits.ADCS2
770 #define VREN VRCON_bits.VREN
772 // ----- WDTCON bits --------------------
775 unsigned char SWDTEN:1;
776 unsigned char WDTPS0:1;
777 unsigned char WDTPS1:1;
778 unsigned char WDTPS2:1;
779 unsigned char WDTPS3:1;
785 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
787 #define SWDTEN WDTCON_bits.SWDTEN
788 #define WDTPS0 WDTCON_bits.WDTPS0
789 #define WDTPS1 WDTCON_bits.WDTPS1
790 #define WDTPS2 WDTCON_bits.WDTPS2
791 #define WDTPS3 WDTCON_bits.WDTPS3