2 // Register Declarations for Microchip 12F683 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define GPIO_ADDR 0x0005
34 #define PCLATH_ADDR 0x000A
35 #define INTCON_ADDR 0x000B
36 #define PIR1_ADDR 0x000C
37 #define TMR1L_ADDR 0x000E
38 #define TMR1H_ADDR 0x000F
39 #define T1CON_ADDR 0x0010
40 #define TMR2_ADDR 0x0011
41 #define T2CON_ADDR 0x0012
42 #define CCPR1L_ADDR 0x0013
43 #define CCPR1H_ADDR 0x0014
44 #define CCP1CON_ADDR 0x0015
45 #define WDTCON_ADDR 0x0018
46 #define CMCON0_ADDR 0x0019
47 #define CMCON1_ADDR 0x001A
48 #define ADRESH_ADDR 0x001E
49 #define ADCON0_ADDR 0x001F
50 #define OPTION_REG_ADDR 0x0081
51 #define TRISIO_ADDR 0x0085
52 #define PIE1_ADDR 0x008C
53 #define PCON_ADDR 0x008E
54 #define OSCCON_ADDR 0x008F
55 #define OSCTUNE_ADDR 0x0090
56 #define PR2_ADDR 0x0092
57 #define WPU_ADDR 0x0095
58 #define WPUA_ADDR 0x0095
59 #define IOC_ADDR 0x0096
60 #define IOCA_ADDR 0x0096
61 #define VRCON_ADDR 0x0099
62 #define EEDATA_ADDR 0x009A
63 #define EEDAT_ADDR 0x009A
64 #define EEADR_ADDR 0x009B
65 #define EECON1_ADDR 0x009C
66 #define EECON2_ADDR 0x009D
67 #define ADRESL_ADDR 0x009E
68 #define ANSEL_ADDR 0x009F
71 // Memory organization.
77 // P12F683.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
80 // This header file defines configurations, registers, and other useful bits of
81 // information for the PIC12F683 microcontroller. These names are taken to match
82 // the data sheets as closely as possible.
84 // Note that the processor must be selected before this file is
85 // included. The processor may be selected the following ways:
87 // 1. Command line switch:
88 // C:\ MPASM MYFILE.ASM /PIC16F684
89 // 2. LIST directive in the source file
91 // 3. Processor Type entry in the MPASM full-screen interface
93 //==========================================================================
97 //==========================================================================
98 //1.01 01/05/07 GPIO Bits
99 //1.00 12/09/03 Original
101 //==========================================================================
105 //==========================================================================
108 // MESSG "Processor-header file mismatch. Verify selected processor."
111 //==========================================================================
113 // Register Definitions
115 //==========================================================================
120 //----- Register Files------------------------------------------------------
122 extern __sfr __at (INDF_ADDR) INDF;
123 extern __sfr __at (TMR0_ADDR) TMR0;
124 extern __sfr __at (PCL_ADDR) PCL;
125 extern __sfr __at (STATUS_ADDR) STATUS;
126 extern __sfr __at (FSR_ADDR) FSR;
127 extern __sfr __at (GPIO_ADDR) GPIO;
129 extern __sfr __at (PCLATH_ADDR) PCLATH;
130 extern __sfr __at (INTCON_ADDR) INTCON;
131 extern __sfr __at (PIR1_ADDR) PIR1;
133 extern __sfr __at (TMR1L_ADDR) TMR1L;
134 extern __sfr __at (TMR1H_ADDR) TMR1H;
135 extern __sfr __at (T1CON_ADDR) T1CON;
136 extern __sfr __at (TMR2_ADDR) TMR2;
137 extern __sfr __at (T2CON_ADDR) T2CON;
138 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
139 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
140 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
142 extern __sfr __at (WDTCON_ADDR) WDTCON;
143 extern __sfr __at (CMCON0_ADDR) CMCON0;
144 extern __sfr __at (CMCON1_ADDR) CMCON1;
146 extern __sfr __at (ADRESH_ADDR) ADRESH;
147 extern __sfr __at (ADCON0_ADDR) ADCON0;
149 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
151 extern __sfr __at (TRISIO_ADDR) TRISIO;
153 extern __sfr __at (PIE1_ADDR) PIE1;
155 extern __sfr __at (PCON_ADDR) PCON;
156 extern __sfr __at (OSCCON_ADDR) OSCCON;
157 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
159 extern __sfr __at (PR2_ADDR) PR2;
161 extern __sfr __at (WPU_ADDR) WPU;
162 extern __sfr __at (WPUA_ADDR) WPUA;
163 extern __sfr __at (IOC_ADDR) IOC;
164 extern __sfr __at (IOCA_ADDR) IOCA;
166 extern __sfr __at (VRCON_ADDR) VRCON;
167 extern __sfr __at (EEDATA_ADDR) EEDATA;
168 extern __sfr __at (EEDAT_ADDR) EEDAT;
169 extern __sfr __at (EEADR_ADDR) EEADR;
170 extern __sfr __at (EECON1_ADDR) EECON1;
171 extern __sfr __at (EECON2_ADDR) EECON2;
172 extern __sfr __at (ADRESL_ADDR) ADRESL;
173 extern __sfr __at (ANSEL_ADDR) ANSEL;
176 //----- STATUS Bits --------------------------------------------------------
179 //----- INTCON Bits --------------------------------------------------------
182 //----- PIR1 Bits ----------------------------------------------------------
185 //----- T1CON Bits ---------------------------------------------------------
188 //----- T2CON Bits ---------------------------------------------------------
191 //----- CCP1CON Bits -------------------------------------------------------
194 //----- WDTCON Bits --------------------------------------------------------
197 //----- COMCON0 Bits -------------------------------------------------------
200 //----- COMCON1 Bits -------------------------------------------------------
203 //----- ADCON0 Bits --------------------------------------------------------
206 //----- OPTION Bits --------------------------------------------------------
210 //----- PIE1 Bits ----------------------------------------------------------
213 //----- PCON Bits ----------------------------------------------------------
216 //----- OSCCON Bits --------------------------------------------------------
219 //----- OSCTUNE Bits -------------------------------------------------------
223 //----- IOC --------------------------------------------------------------
226 //----- IOCA --------------------------------------------------------------
229 //----- VRCON Bits ---------------------------------------------------------
232 //----- EECON1 -------------------------------------------------------------
235 //----- ANSEL --------------------------------------------------------------
238 //==========================================================================
242 //==========================================================================
245 // __BADRAM H'06', H'08'-H'09', H'0D', H'1B'-H'1D'
246 // __BADRAM H'86', H'88'-H'89', H'8D', H'93'-H'94', H'97'-H'98', H'C0'-H'EF'
248 //==========================================================================
250 // Configuration Bits
252 //==========================================================================
254 #define _FCMEN_ON 0x3FFF
255 #define _FCMEN_OFF 0x37FF
256 #define _IESO_ON 0x3FFF
257 #define _IESO_OFF 0x3BFF
258 #define _BOD_ON 0x3FFF
259 #define _BOD_NSLEEP 0x3EFF
260 #define _BOD_SBODEN 0x3DFF
261 #define _BOD_OFF 0x3CFF
262 #define _CPD_ON 0x3F7F
263 #define _CPD_OFF 0x3FFF
264 #define _CP_ON 0x3FBF
265 #define _CP_OFF 0x3FFF
266 #define _MCLRE_ON 0x3FFF
267 #define _MCLRE_OFF 0x3FDF
268 #define _PWRTE_OFF 0x3FFF
269 #define _PWRTE_ON 0x3FEF
270 #define _WDT_ON 0x3FFF
271 #define _WDT_OFF 0x3FF7
272 #define _LP_OSC 0x3FF8
273 #define _XT_OSC 0x3FF9
274 #define _HS_OSC 0x3FFA
275 #define _EC_OSC 0x3FFB
276 #define _INTRC_OSC_NOCLKOUT 0x3FFC
277 #define _INTOSCIO 0x3FFC
278 #define _INTRC_OSC_CLKOUT 0x3FFD
279 #define _INTOSC 0x3FFD
280 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
281 #define _EXTRCIO 0x3FFE
282 #define _EXTRC_OSC_CLKOUT 0x3FFF
283 #define _EXTRC 0x3FFF
287 // ----- ADCON0 bits --------------------
290 unsigned char ADON:1;
292 unsigned char CHS0:1;
293 unsigned char CHS1:1;
294 unsigned char CHS2:1;
296 unsigned char VCFG:1;
297 unsigned char ADFM:1;
301 unsigned char NOT_DONE:1;
311 unsigned char GO_DONE:1;
320 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
322 #ifndef NO_BIT_DEFINES
323 #define ADON ADCON0_bits.ADON
324 #define GO ADCON0_bits.GO
325 #define NOT_DONE ADCON0_bits.NOT_DONE
326 #define GO_DONE ADCON0_bits.GO_DONE
327 #define CHS0 ADCON0_bits.CHS0
328 #define CHS1 ADCON0_bits.CHS1
329 #define CHS2 ADCON0_bits.CHS2
330 #define VCFG ADCON0_bits.VCFG
331 #define ADFM ADCON0_bits.ADFM
332 #endif /* NO_BIT_DEFINES */
334 // ----- ANSEL bits --------------------
337 unsigned char ANS0:1;
338 unsigned char ANS1:1;
339 unsigned char ANS2:1;
340 unsigned char ANS3:1;
341 unsigned char ADCS0:1;
342 unsigned char ADCS1:1;
343 unsigned char ADCS2:1;
347 extern volatile __ANSEL_bits_t __at(ANSEL_ADDR) ANSEL_bits;
349 #ifndef NO_BIT_DEFINES
350 #define ANS0 ANSEL_bits.ANS0
351 #define ANS1 ANSEL_bits.ANS1
352 #define ANS2 ANSEL_bits.ANS2
353 #define ANS3 ANSEL_bits.ANS3
354 #define ADCS0 ANSEL_bits.ADCS0
355 #define ADCS1 ANSEL_bits.ADCS1
356 #define ADCS2 ANSEL_bits.ADCS2
357 #endif /* NO_BIT_DEFINES */
359 // ----- CCP1CON bits --------------------
362 unsigned char CCP1M0:1;
363 unsigned char CCP1M1:1;
364 unsigned char CCP1M2:1;
365 unsigned char CCP1M3:1;
366 unsigned char DC1B0:1;
367 unsigned char DC1B1:1;
372 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
374 #ifndef NO_BIT_DEFINES
375 #define CCP1M0 CCP1CON_bits.CCP1M0
376 #define CCP1M1 CCP1CON_bits.CCP1M1
377 #define CCP1M2 CCP1CON_bits.CCP1M2
378 #define CCP1M3 CCP1CON_bits.CCP1M3
379 #define DC1B0 CCP1CON_bits.DC1B0
380 #define DC1B1 CCP1CON_bits.DC1B1
381 #endif /* NO_BIT_DEFINES */
383 // ----- CMCON0 bits --------------------
390 unsigned char CINV:1;
392 unsigned char COUT:1;
396 extern volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits;
398 #ifndef NO_BIT_DEFINES
399 #define CM0 CMCON0_bits.CM0
400 #define CM1 CMCON0_bits.CM1
401 #define CM2 CMCON0_bits.CM2
402 #define CIS CMCON0_bits.CIS
403 #define CINV CMCON0_bits.CINV
404 #define COUT CMCON0_bits.COUT
405 #endif /* NO_BIT_DEFINES */
407 // ----- CMCON1 bits --------------------
410 unsigned char CMSYNC:1;
411 unsigned char T1GSS:1;
420 extern volatile __CMCON1_bits_t __at(CMCON1_ADDR) CMCON1_bits;
422 #ifndef NO_BIT_DEFINES
423 #define CMSYNC CMCON1_bits.CMSYNC
424 #define T1GSS CMCON1_bits.T1GSS
425 #endif /* NO_BIT_DEFINES */
427 // ----- EECON1 bits --------------------
432 unsigned char WREN:1;
433 unsigned char WRERR:1;
440 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
442 #ifndef NO_BIT_DEFINES
443 #define RD EECON1_bits.RD
444 #define WR EECON1_bits.WR
445 #define WREN EECON1_bits.WREN
446 #define WRERR EECON1_bits.WRERR
447 #endif /* NO_BIT_DEFINES */
449 // ----- GPIO bits --------------------
462 unsigned char GPIO0:1;
463 unsigned char GPIO1:1;
464 unsigned char GPIO2:1;
465 unsigned char GPIO3:1;
466 unsigned char GPIO4:1;
467 unsigned char GPIO5:1;
472 extern volatile __GPIO_bits_t __at(GPIO_ADDR) GPIO_bits;
474 #ifndef NO_BIT_DEFINES
475 #define GP0 GPIO_bits.GP0
476 #define GPIO0 GPIO_bits.GPIO0
477 #define GP1 GPIO_bits.GP1
478 #define GPIO1 GPIO_bits.GPIO1
479 #define GP2 GPIO_bits.GP2
480 #define GPIO2 GPIO_bits.GPIO2
481 #define GP3 GPIO_bits.GP3
482 #define GPIO3 GPIO_bits.GPIO3
483 #define GP4 GPIO_bits.GP4
484 #define GPIO4 GPIO_bits.GPIO4
485 #define GP5 GPIO_bits.GP5
486 #define GPIO5 GPIO_bits.GPIO5
487 #endif /* NO_BIT_DEFINES */
489 // ----- INTCON bits --------------------
492 unsigned char GPIF:1;
493 unsigned char INTF:1;
494 unsigned char T0IF:1;
495 unsigned char GPIE:1;
496 unsigned char INTE:1;
497 unsigned char T0IE:1;
498 unsigned char PEIE:1;
502 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
504 #ifndef NO_BIT_DEFINES
505 #define GPIF INTCON_bits.GPIF
506 #define INTF INTCON_bits.INTF
507 #define T0IF INTCON_bits.T0IF
508 #define GPIE INTCON_bits.GPIE
509 #define INTE INTCON_bits.INTE
510 #define T0IE INTCON_bits.T0IE
511 #define PEIE INTCON_bits.PEIE
512 #define GIE INTCON_bits.GIE
513 #endif /* NO_BIT_DEFINES */
515 // ----- IOC bits --------------------
518 unsigned char IOC0:1;
519 unsigned char IOC1:1;
520 unsigned char IOC2:1;
521 unsigned char IOC3:1;
522 unsigned char IOC4:1;
523 unsigned char IOC5:1;
528 extern volatile __IOC_bits_t __at(IOC_ADDR) IOC_bits;
530 #ifndef NO_BIT_DEFINES
531 #define IOC0 IOC_bits.IOC0
532 #define IOC1 IOC_bits.IOC1
533 #define IOC2 IOC_bits.IOC2
534 #define IOC3 IOC_bits.IOC3
535 #define IOC4 IOC_bits.IOC4
536 #define IOC5 IOC_bits.IOC5
537 #endif /* NO_BIT_DEFINES */
539 // ----- IOCA bits --------------------
542 unsigned char IOCA0:1;
543 unsigned char IOCA1:1;
544 unsigned char IOCA2:1;
545 unsigned char IOCA3:1;
546 unsigned char IOCA4:1;
547 unsigned char IOCA5:1;
552 extern volatile __IOCA_bits_t __at(IOCA_ADDR) IOCA_bits;
554 #ifndef NO_BIT_DEFINES
555 #define IOCA0 IOCA_bits.IOCA0
556 #define IOCA1 IOCA_bits.IOCA1
557 #define IOCA2 IOCA_bits.IOCA2
558 #define IOCA3 IOCA_bits.IOCA3
559 #define IOCA4 IOCA_bits.IOCA4
560 #define IOCA5 IOCA_bits.IOCA5
561 #endif /* NO_BIT_DEFINES */
563 // ----- OPTION_REG bits --------------------
570 unsigned char T0SE:1;
571 unsigned char T0CS:1;
572 unsigned char INTEDG:1;
573 unsigned char NOT_GPPU:1;
575 } __OPTION_REG_bits_t;
576 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
578 #ifndef NO_BIT_DEFINES
579 #define PS0 OPTION_REG_bits.PS0
580 #define PS1 OPTION_REG_bits.PS1
581 #define PS2 OPTION_REG_bits.PS2
582 #define PSA OPTION_REG_bits.PSA
583 #define T0SE OPTION_REG_bits.T0SE
584 #define T0CS OPTION_REG_bits.T0CS
585 #define INTEDG OPTION_REG_bits.INTEDG
586 #define NOT_GPPU OPTION_REG_bits.NOT_GPPU
587 #endif /* NO_BIT_DEFINES */
589 // ----- OSCCON bits --------------------
595 unsigned char OSTS:1;
596 unsigned char IRCF0:1;
597 unsigned char IRCF1:1;
598 unsigned char IRCF2:1;
602 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
604 #ifndef NO_BIT_DEFINES
605 #define SCS OSCCON_bits.SCS
606 #define LTS OSCCON_bits.LTS
607 #define HTS OSCCON_bits.HTS
608 #define OSTS OSCCON_bits.OSTS
609 #define IRCF0 OSCCON_bits.IRCF0
610 #define IRCF1 OSCCON_bits.IRCF1
611 #define IRCF2 OSCCON_bits.IRCF2
612 #endif /* NO_BIT_DEFINES */
614 // ----- OSCTUNE bits --------------------
617 unsigned char TUN0:1;
618 unsigned char TUN1:1;
619 unsigned char TUN2:1;
620 unsigned char TUN3:1;
621 unsigned char TUN4:1;
627 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
629 #ifndef NO_BIT_DEFINES
630 #define TUN0 OSCTUNE_bits.TUN0
631 #define TUN1 OSCTUNE_bits.TUN1
632 #define TUN2 OSCTUNE_bits.TUN2
633 #define TUN3 OSCTUNE_bits.TUN3
634 #define TUN4 OSCTUNE_bits.TUN4
635 #endif /* NO_BIT_DEFINES */
637 // ----- PCON bits --------------------
640 unsigned char NOT_BOD:1;
641 unsigned char NOT_POR:1;
644 unsigned char SBODEN:1;
645 unsigned char ULPWUE:1;
650 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
652 #ifndef NO_BIT_DEFINES
653 #define NOT_BOD PCON_bits.NOT_BOD
654 #define NOT_POR PCON_bits.NOT_POR
655 #define SBODEN PCON_bits.SBODEN
656 #define ULPWUE PCON_bits.ULPWUE
657 #endif /* NO_BIT_DEFINES */
659 // ----- PIE1 bits --------------------
662 unsigned char T1IE:1;
663 unsigned char T2IE:1;
664 unsigned char OSFIE:1;
665 unsigned char CMIE:1;
667 unsigned char CCP1IE:1;
668 unsigned char ADIE:1;
669 unsigned char EEIE:1;
672 unsigned char TMR1IE:1;
673 unsigned char TMR2IE:1;
682 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
684 #ifndef NO_BIT_DEFINES
685 #define T1IE PIE1_bits.T1IE
686 #define TMR1IE PIE1_bits.TMR1IE
687 #define T2IE PIE1_bits.T2IE
688 #define TMR2IE PIE1_bits.TMR2IE
689 #define OSFIE PIE1_bits.OSFIE
690 #define CMIE PIE1_bits.CMIE
691 #define CCP1IE PIE1_bits.CCP1IE
692 #define ADIE PIE1_bits.ADIE
693 #define EEIE PIE1_bits.EEIE
694 #endif /* NO_BIT_DEFINES */
696 // ----- PIR1 bits --------------------
699 unsigned char T1IF:1;
700 unsigned char T2IF:1;
701 unsigned char OSFIF:1;
702 unsigned char CMIF:1;
704 unsigned char CCP1IF:1;
705 unsigned char ADIF:1;
706 unsigned char EEIF:1;
709 unsigned char TMR1IF:1;
710 unsigned char TMR2IF:1;
719 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
721 #ifndef NO_BIT_DEFINES
722 #define T1IF PIR1_bits.T1IF
723 #define TMR1IF PIR1_bits.TMR1IF
724 #define T2IF PIR1_bits.T2IF
725 #define TMR2IF PIR1_bits.TMR2IF
726 #define OSFIF PIR1_bits.OSFIF
727 #define CMIF PIR1_bits.CMIF
728 #define CCP1IF PIR1_bits.CCP1IF
729 #define ADIF PIR1_bits.ADIF
730 #define EEIF PIR1_bits.EEIF
731 #endif /* NO_BIT_DEFINES */
733 // ----- STATUS bits --------------------
739 unsigned char NOT_PD:1;
740 unsigned char NOT_TO:1;
746 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
748 #ifndef NO_BIT_DEFINES
749 #define C STATUS_bits.C
750 #define DC STATUS_bits.DC
751 #define Z STATUS_bits.Z
752 #define NOT_PD STATUS_bits.NOT_PD
753 #define NOT_TO STATUS_bits.NOT_TO
754 #define RP0 STATUS_bits.RP0
755 #define RP1 STATUS_bits.RP1
756 #define IRP STATUS_bits.IRP
757 #endif /* NO_BIT_DEFINES */
759 // ----- T1CON bits --------------------
762 unsigned char TMR1ON:1;
763 unsigned char TMR1CS:1;
764 unsigned char NOT_T1SYNC:1;
765 unsigned char T1OSCEN:1;
766 unsigned char T1CKPS0:1;
767 unsigned char T1CKPS1:1;
768 unsigned char T1GE:1;
769 unsigned char T1GINV:1;
772 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
774 #ifndef NO_BIT_DEFINES
775 #define TMR1ON T1CON_bits.TMR1ON
776 #define TMR1CS T1CON_bits.TMR1CS
777 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
778 #define T1OSCEN T1CON_bits.T1OSCEN
779 #define T1CKPS0 T1CON_bits.T1CKPS0
780 #define T1CKPS1 T1CON_bits.T1CKPS1
781 #define T1GE T1CON_bits.T1GE
782 #define T1GINV T1CON_bits.T1GINV
783 #endif /* NO_BIT_DEFINES */
785 // ----- T2CON bits --------------------
788 unsigned char T2CKPS0:1;
789 unsigned char T2CKPS1:1;
790 unsigned char TMR2ON:1;
791 unsigned char TOUTPS0:1;
792 unsigned char TOUTPS1:1;
793 unsigned char TOUTPS2:1;
794 unsigned char TOUTPS3:1;
798 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
800 #ifndef NO_BIT_DEFINES
801 #define T2CKPS0 T2CON_bits.T2CKPS0
802 #define T2CKPS1 T2CON_bits.T2CKPS1
803 #define TMR2ON T2CON_bits.TMR2ON
804 #define TOUTPS0 T2CON_bits.TOUTPS0
805 #define TOUTPS1 T2CON_bits.TOUTPS1
806 #define TOUTPS2 T2CON_bits.TOUTPS2
807 #define TOUTPS3 T2CON_bits.TOUTPS3
808 #endif /* NO_BIT_DEFINES */
810 // ----- VRCON bits --------------------
820 unsigned char VREN:1;
823 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
825 #ifndef NO_BIT_DEFINES
826 #define VR0 VRCON_bits.VR0
827 #define VR1 VRCON_bits.VR1
828 #define VR2 VRCON_bits.VR2
829 #define VR3 VRCON_bits.VR3
830 #define VRR VRCON_bits.VRR
831 #define VREN VRCON_bits.VREN
832 #endif /* NO_BIT_DEFINES */
834 // ----- WDTCON bits --------------------
837 unsigned char SWDTEN:1;
838 unsigned char WDTPS0:1;
839 unsigned char WDTPS1:1;
840 unsigned char WDTPS2:1;
841 unsigned char WDTPS3:1;
847 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
849 #ifndef NO_BIT_DEFINES
850 #define SWDTEN WDTCON_bits.SWDTEN
851 #define WDTPS0 WDTCON_bits.WDTPS0
852 #define WDTPS1 WDTCON_bits.WDTPS1
853 #define WDTPS2 WDTCON_bits.WDTPS2
854 #define WDTPS3 WDTCON_bits.WDTPS3
855 #endif /* NO_BIT_DEFINES */