2 // Register Declarations for Microchip 12F675 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define GPIO_ADDR 0x0005
34 #define PCLATH_ADDR 0x000A
35 #define INTCON_ADDR 0x000B
36 #define PIR1_ADDR 0x000C
37 #define TMR1L_ADDR 0x000E
38 #define TMR1H_ADDR 0x000F
39 #define T1CON_ADDR 0x0010
40 #define CMCON_ADDR 0x0019
41 #define ADRESH_ADDR 0x001E
42 #define ADCON0_ADDR 0x001F
43 #define OPTION_REG_ADDR 0x0081
44 #define TRISIO_ADDR 0x0085
45 #define PIE1_ADDR 0x008C
46 #define PCON_ADDR 0x008E
47 #define OSCCAL_ADDR 0x0090
48 #define WPU_ADDR 0x0095
49 #define IOC_ADDR 0x0096
50 #define IOCB_ADDR 0x0096
51 #define VRCON_ADDR 0x0099
52 #define EEDATA_ADDR 0x009A
53 #define EEDAT_ADDR 0x009A
54 #define EEADR_ADDR 0x009B
55 #define EECON1_ADDR 0x009C
56 #define EECON2_ADDR 0x009D
57 #define ADRESL_ADDR 0x009E
58 #define ANSEL_ADDR 0x009F
61 // Memory organization.
67 // P12F675.INC Standard Header File, Version 1.04 Microchip Technology, Inc.
70 // This header file defines configurations, registers, and other useful bits of
71 // information for the PIC12F675 microcontroller. These names are taken to match
72 // the data sheets as closely as possible.
74 // Note that the processor must be selected before this file is
75 // included. The processor may be selected the following ways:
77 // 1. Command line switch:
78 // C:\ MPASM MYFILE.ASM /PIC12F675
79 // 2. LIST directive in the source file
81 // 3. Processor Type entry in the MPASM full-screen interface
83 //==========================================================================
87 //==========================================================================
88 //1.04 07/01/02 Updated configuration bit names
89 //1.03 05/10/02 Corrected ADCON0 register, added IOC register
90 //1.02 02/28/02 Updated per datasheet
91 //1.01 01/31/02 Updated per datasheet
92 //1.00 08/24/01 Original
94 //==========================================================================
98 //==========================================================================
101 // MESSG "Processor-header file mismatch. Verify selected processor."
104 //==========================================================================
106 // Register Definitions
108 //==========================================================================
113 //----- Register Files------------------------------------------------------
115 extern __data __at (INDF_ADDR) volatile char INDF;
116 extern __sfr __at (TMR0_ADDR) TMR0;
117 extern __data __at (PCL_ADDR) volatile char PCL;
118 extern __sfr __at (STATUS_ADDR) STATUS;
119 extern __sfr __at (FSR_ADDR) FSR;
120 extern __sfr __at (GPIO_ADDR) GPIO;
122 extern __sfr __at (PCLATH_ADDR) PCLATH;
123 extern __sfr __at (INTCON_ADDR) INTCON;
124 extern __sfr __at (PIR1_ADDR) PIR1;
126 extern __sfr __at (TMR1L_ADDR) TMR1L;
127 extern __sfr __at (TMR1H_ADDR) TMR1H;
128 extern __sfr __at (T1CON_ADDR) T1CON;
130 extern __sfr __at (CMCON_ADDR) CMCON;
132 extern __sfr __at (ADRESH_ADDR) ADRESH;
133 extern __sfr __at (ADCON0_ADDR) ADCON0;
136 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
138 extern __sfr __at (TRISIO_ADDR) TRISIO;
140 extern __sfr __at (PIE1_ADDR) PIE1;
142 extern __sfr __at (PCON_ADDR) PCON;
144 extern __sfr __at (OSCCAL_ADDR) OSCCAL;
146 extern __sfr __at (WPU_ADDR) WPU;
147 extern __sfr __at (IOC_ADDR) IOC;
148 extern __sfr __at (IOCB_ADDR) IOCB;
150 extern __sfr __at (VRCON_ADDR) VRCON;
151 extern __sfr __at (EEDATA_ADDR) EEDATA;
152 extern __sfr __at (EEDAT_ADDR) EEDAT;
153 extern __sfr __at (EEADR_ADDR) EEADR;
154 extern __sfr __at (EECON1_ADDR) EECON1;
155 extern __sfr __at (EECON2_ADDR) EECON2;
156 extern __sfr __at (ADRESL_ADDR) ADRESL;
157 extern __sfr __at (ANSEL_ADDR) ANSEL;
160 //----- STATUS Bits --------------------------------------------------------
163 //----- GPIO Bits --------------------------------------------------------
166 //----- INTCON Bits --------------------------------------------------------
169 //----- PIR1 Bits ----------------------------------------------------------
172 //----- T1CON Bits ---------------------------------------------------------
175 //----- COMCON Bits --------------------------------------------------------
178 //----- ADCON0 Bits --------------------------------------------------------
181 //----- OPTION Bits --------------------------------------------------------
184 //----- PIE1 Bits ----------------------------------------------------------
187 //----- PCON Bits ----------------------------------------------------------
190 //----- OSCCAL Bits --------------------------------------------------------
193 //----- IOCB Bits --------------------------------------------------------
196 //----- IOC Bits --------------------------------------------------------
199 //----- VRCON Bits ---------------------------------------------------------
202 //----- EECON1 -------------------------------------------------------------
205 //----- ANSEL --------------------------------------------------------------
208 //==========================================================================
212 //==========================================================================
215 // __BADRAM H'06'-H'09', H'0D', H'11'-H'18', H'1A'-H'1D', H'60'-H'7F'
216 // __BADRAM H'86'-H'89', H'8D', H'8F', H'91'-H'94', H'97'-H'98', H'E0'-H'FF'
218 //==========================================================================
220 // Configuration Bits
222 //==========================================================================
224 #define _CPD_ON 0x3EFF
225 #define _CPD_OFF 0x3FFF
226 #define _CP_ON 0x3F7F
227 #define _CP_OFF 0x3FFF
228 #define _BODEN_ON 0x3FFF
229 #define _BODEN_OFF 0x3FBF
230 #define _MCLRE_ON 0x3FFF
231 #define _MCLRE_OFF 0x3FDF
232 #define _PWRTE_OFF 0x3FFF
233 #define _PWRTE_ON 0x3FEF
234 #define _WDT_ON 0x3FFF
235 #define _WDT_OFF 0x3FF7
236 #define _LP_OSC 0x3FF8
237 #define _XT_OSC 0x3FF9
238 #define _HS_OSC 0x3FFA
239 #define _EC_OSC 0x3FFB
240 #define _INTRC_OSC_NOCLKOUT 0x3FFC
241 #define _INTRC_OSC_CLKOUT 0x3FFD
242 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
243 #define _EXTRC_OSC_CLKOUT 0x3FFF
247 // ----- ADCON0 bits --------------------
250 unsigned char ADON:1;
252 unsigned char CHS0:1;
253 unsigned char CHS1:1;
256 unsigned char VCFG:1;
257 unsigned char ADFM:1;
261 unsigned char NOT_DONE:1;
271 unsigned char GO_DONE:1;
280 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
282 #define ADON ADCON0_bits.ADON
283 #define GO ADCON0_bits.GO
284 #define NOT_DONE ADCON0_bits.NOT_DONE
285 #define GO_DONE ADCON0_bits.GO_DONE
286 #define CHS0 ADCON0_bits.CHS0
287 #define CHS1 ADCON0_bits.CHS1
288 #define VCFG ADCON0_bits.VCFG
289 #define ADFM ADCON0_bits.ADFM
291 // ----- ANSEL bits --------------------
294 unsigned char ANS0:1;
295 unsigned char ANS1:1;
296 unsigned char ANS2:1;
297 unsigned char ANS3:1;
298 unsigned char ADCS0:1;
299 unsigned char ADCS1:1;
300 unsigned char ADCS2:1;
304 extern volatile __ANSEL_bits_t __at(ANSEL_ADDR) ANSEL_bits;
306 #define ANS0 ANSEL_bits.ANS0
307 #define ANS1 ANSEL_bits.ANS1
308 #define ANS2 ANSEL_bits.ANS2
309 #define ANS3 ANSEL_bits.ANS3
310 #define ADCS0 ANSEL_bits.ADCS0
311 #define ADCS1 ANSEL_bits.ADCS1
312 #define ADCS2 ANSEL_bits.ADCS2
314 // ----- CMCON bits --------------------
321 unsigned char CINV:1;
323 unsigned char COUT:1;
327 extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;
329 #define CM0 CMCON_bits.CM0
330 #define CM1 CMCON_bits.CM1
331 #define CM2 CMCON_bits.CM2
332 #define CIS CMCON_bits.CIS
333 #define CINV CMCON_bits.CINV
334 #define COUT CMCON_bits.COUT
336 // ----- EECON1 bits --------------------
341 unsigned char WREN:1;
342 unsigned char WRERR:1;
349 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
351 #define RD EECON1_bits.RD
352 #define WR EECON1_bits.WR
353 #define WREN EECON1_bits.WREN
354 #define WRERR EECON1_bits.WRERR
356 // ----- GPIO bits --------------------
369 unsigned char GPIO0:1;
370 unsigned char GPIO1:1;
371 unsigned char GPIO2:1;
372 unsigned char GPIO3:1;
373 unsigned char GPIO4:1;
374 unsigned char GPIO5:1;
379 extern volatile __GPIO_bits_t __at(GPIO_ADDR) GPIO_bits;
381 #define GP0 GPIO_bits.GP0
382 #define GPIO0 GPIO_bits.GPIO0
383 #define GP1 GPIO_bits.GP1
384 #define GPIO1 GPIO_bits.GPIO1
385 #define GP2 GPIO_bits.GP2
386 #define GPIO2 GPIO_bits.GPIO2
387 #define GP3 GPIO_bits.GP3
388 #define GPIO3 GPIO_bits.GPIO3
389 #define GP4 GPIO_bits.GP4
390 #define GPIO4 GPIO_bits.GPIO4
391 #define GP5 GPIO_bits.GP5
392 #define GPIO5 GPIO_bits.GPIO5
394 // ----- INTCON bits --------------------
397 unsigned char GPIF:1;
398 unsigned char INTF:1;
399 unsigned char T0IF:1;
400 unsigned char GPIE:1;
401 unsigned char INTE:1;
402 unsigned char T0IE:1;
403 unsigned char PEIE:1;
407 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
409 #define GPIF INTCON_bits.GPIF
410 #define INTF INTCON_bits.INTF
411 #define T0IF INTCON_bits.T0IF
412 #define GPIE INTCON_bits.GPIE
413 #define INTE INTCON_bits.INTE
414 #define T0IE INTCON_bits.T0IE
415 #define PEIE INTCON_bits.PEIE
416 #define GIE INTCON_bits.GIE
418 // ----- IOC bits --------------------
421 unsigned char IOC0:1;
422 unsigned char IOC1:1;
423 unsigned char IOC2:1;
424 unsigned char IOC3:1;
425 unsigned char IOC4:1;
426 unsigned char IOC5:1;
431 extern volatile __IOC_bits_t __at(IOC_ADDR) IOC_bits;
433 #define IOC0 IOC_bits.IOC0
434 #define IOC1 IOC_bits.IOC1
435 #define IOC2 IOC_bits.IOC2
436 #define IOC3 IOC_bits.IOC3
437 #define IOC4 IOC_bits.IOC4
438 #define IOC5 IOC_bits.IOC5
440 // ----- IOCB bits --------------------
443 unsigned char IOCB0:1;
444 unsigned char IOCB1:1;
445 unsigned char IOCB2:1;
446 unsigned char IOCB3:1;
447 unsigned char IOCB4:1;
448 unsigned char IOCB5:1;
453 extern volatile __IOCB_bits_t __at(IOCB_ADDR) IOCB_bits;
455 #define IOCB0 IOCB_bits.IOCB0
456 #define IOCB1 IOCB_bits.IOCB1
457 #define IOCB2 IOCB_bits.IOCB2
458 #define IOCB3 IOCB_bits.IOCB3
459 #define IOCB4 IOCB_bits.IOCB4
460 #define IOCB5 IOCB_bits.IOCB5
462 // ----- OPTION_REG bits --------------------
469 unsigned char T0SE:1;
470 unsigned char T0CS:1;
471 unsigned char INTEDG:1;
472 unsigned char NOT_GPPU:1;
474 } __OPTION_REG_bits_t;
475 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
477 #define PS0 OPTION_REG_bits.PS0
478 #define PS1 OPTION_REG_bits.PS1
479 #define PS2 OPTION_REG_bits.PS2
480 #define PSA OPTION_REG_bits.PSA
481 #define T0SE OPTION_REG_bits.T0SE
482 #define T0CS OPTION_REG_bits.T0CS
483 #define INTEDG OPTION_REG_bits.INTEDG
484 #define NOT_GPPU OPTION_REG_bits.NOT_GPPU
486 // ----- OSCCAL bits --------------------
491 unsigned char CAL0:1;
492 unsigned char CAL1:1;
493 unsigned char CAL2:1;
494 unsigned char CAL3:1;
495 unsigned char CAL4:1;
496 unsigned char CAL5:1;
499 extern volatile __OSCCAL_bits_t __at(OSCCAL_ADDR) OSCCAL_bits;
501 #define CAL0 OSCCAL_bits.CAL0
502 #define CAL1 OSCCAL_bits.CAL1
503 #define CAL2 OSCCAL_bits.CAL2
504 #define CAL3 OSCCAL_bits.CAL3
505 #define CAL4 OSCCAL_bits.CAL4
506 #define CAL5 OSCCAL_bits.CAL5
508 // ----- PCON bits --------------------
511 unsigned char NOT_BOD:1;
512 unsigned char NOT_POR:1;
521 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
523 #define NOT_BOD PCON_bits.NOT_BOD
524 #define NOT_POR PCON_bits.NOT_POR
526 // ----- PIE1 bits --------------------
529 unsigned char T1IE:1;
532 unsigned char CMIE:1;
535 unsigned char ADIE:1;
536 unsigned char EEIE:1;
539 unsigned char TMR1IE:1;
549 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
551 #define T1IE PIE1_bits.T1IE
552 #define TMR1IE PIE1_bits.TMR1IE
553 #define CMIE PIE1_bits.CMIE
554 #define ADIE PIE1_bits.ADIE
555 #define EEIE PIE1_bits.EEIE
557 // ----- PIR1 bits --------------------
560 unsigned char T1IF:1;
563 unsigned char CMIF:1;
566 unsigned char ADIF:1;
567 unsigned char EEIF:1;
570 unsigned char TMR1IF:1;
580 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
582 #define T1IF PIR1_bits.T1IF
583 #define TMR1IF PIR1_bits.TMR1IF
584 #define CMIF PIR1_bits.CMIF
585 #define ADIF PIR1_bits.ADIF
586 #define EEIF PIR1_bits.EEIF
588 // ----- STATUS bits --------------------
594 unsigned char NOT_PD:1;
595 unsigned char NOT_TO:1;
601 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
603 #define C STATUS_bits.C
604 #define DC STATUS_bits.DC
605 #define Z STATUS_bits.Z
606 #define NOT_PD STATUS_bits.NOT_PD
607 #define NOT_TO STATUS_bits.NOT_TO
608 #define RP0 STATUS_bits.RP0
609 #define RP1 STATUS_bits.RP1
610 #define IRP STATUS_bits.IRP
612 // ----- T1CON bits --------------------
615 unsigned char TMR1ON:1;
616 unsigned char TMR1CS:1;
617 unsigned char NOT_T1SYNC:1;
618 unsigned char T1OSCEN:1;
619 unsigned char T1CKPS0:1;
620 unsigned char T1CKPS1:1;
621 unsigned char TMR1GE:1;
625 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
627 #define TMR1ON T1CON_bits.TMR1ON
628 #define TMR1CS T1CON_bits.TMR1CS
629 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
630 #define T1OSCEN T1CON_bits.T1OSCEN
631 #define T1CKPS0 T1CON_bits.T1CKPS0
632 #define T1CKPS1 T1CON_bits.T1CKPS1
633 #define TMR1GE T1CON_bits.TMR1GE
635 // ----- VRCON bits --------------------
645 unsigned char VREN:1;
648 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
650 #define VR0 VRCON_bits.VR0
651 #define VR1 VRCON_bits.VR1
652 #define VR2 VRCON_bits.VR2
653 #define VR3 VRCON_bits.VR3
654 #define VRR VRCON_bits.VRR
655 #define VREN VRCON_bits.VREN