2 // Register Declarations for Microchip 12F675 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define GPIO_ADDR 0x0005
34 #define PCLATH_ADDR 0x000A
35 #define INTCON_ADDR 0x000B
36 #define PIR1_ADDR 0x000C
37 #define TMR1L_ADDR 0x000E
38 #define TMR1H_ADDR 0x000F
39 #define T1CON_ADDR 0x0010
40 #define CMCON_ADDR 0x0019
41 #define ADRESH_ADDR 0x001E
42 #define ADCON0_ADDR 0x001F
43 #define OPTION_REG_ADDR 0x0081
44 #define TRISIO_ADDR 0x0085
45 #define PIE1_ADDR 0x008C
46 #define PCON_ADDR 0x008E
47 #define OSCCAL_ADDR 0x0090
48 #define WPU_ADDR 0x0095
49 #define IOC_ADDR 0x0096
50 #define IOCB_ADDR 0x0096
51 #define VRCON_ADDR 0x0099
52 #define EEDATA_ADDR 0x009A
53 #define EEDAT_ADDR 0x009A
54 #define EEADR_ADDR 0x009B
55 #define EECON1_ADDR 0x009C
56 #define EECON2_ADDR 0x009D
57 #define ADRESL_ADDR 0x009E
58 #define ANSEL_ADDR 0x009F
61 // Memory organization.
64 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
65 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
66 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
67 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
68 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
69 #pragma memmap GPIO_ADDR GPIO_ADDR SFR 0x000 // GPIO
70 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
71 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
72 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
73 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
74 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
75 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
76 #pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000 // CMCON
77 #pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH
78 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
79 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
80 #pragma memmap TRISIO_ADDR TRISIO_ADDR SFR 0x000 // TRISIO
81 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
82 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
83 #pragma memmap OSCCAL_ADDR OSCCAL_ADDR SFR 0x000 // OSCCAL
84 #pragma memmap WPU_ADDR WPU_ADDR SFR 0x000 // WPU
85 #pragma memmap IOC_ADDR IOC_ADDR SFR 0x000 // IOC
86 #pragma memmap IOCB_ADDR IOCB_ADDR SFR 0x000 // IOCB
87 #pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON
88 #pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA
89 #pragma memmap EEDAT_ADDR EEDAT_ADDR SFR 0x000 // EEDAT
90 #pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR
91 #pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1
92 #pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2
93 #pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL
94 #pragma memmap ANSEL_ADDR ANSEL_ADDR SFR 0x000 // ANSEL
98 // P12F675.INC Standard Header File, Version 1.04 Microchip Technology, Inc.
101 // This header file defines configurations, registers, and other useful bits of
102 // information for the PIC12F675 microcontroller. These names are taken to match
103 // the data sheets as closely as possible.
105 // Note that the processor must be selected before this file is
106 // included. The processor may be selected the following ways:
108 // 1. Command line switch:
109 // C:\ MPASM MYFILE.ASM /PIC12F675
110 // 2. LIST directive in the source file
112 // 3. Processor Type entry in the MPASM full-screen interface
114 //==========================================================================
118 //==========================================================================
119 //1.04 07/01/02 Updated configuration bit names
120 //1.03 05/10/02 Corrected ADCON0 register, added IOC register
121 //1.02 02/28/02 Updated per datasheet
122 //1.01 01/31/02 Updated per datasheet
123 //1.00 08/24/01 Original
125 //==========================================================================
129 //==========================================================================
132 // MESSG "Processor-header file mismatch. Verify selected processor."
135 //==========================================================================
137 // Register Definitions
139 //==========================================================================
144 //----- Register Files------------------------------------------------------
146 extern __data __at (INDF_ADDR) volatile char INDF;
147 extern __sfr __at (TMR0_ADDR) TMR0;
148 extern __data __at (PCL_ADDR) volatile char PCL;
149 extern __sfr __at (STATUS_ADDR) STATUS;
150 extern __sfr __at (FSR_ADDR) FSR;
151 extern __sfr __at (GPIO_ADDR) GPIO;
153 extern __sfr __at (PCLATH_ADDR) PCLATH;
154 extern __sfr __at (INTCON_ADDR) INTCON;
155 extern __sfr __at (PIR1_ADDR) PIR1;
157 extern __sfr __at (TMR1L_ADDR) TMR1L;
158 extern __sfr __at (TMR1H_ADDR) TMR1H;
159 extern __sfr __at (T1CON_ADDR) T1CON;
161 extern __sfr __at (CMCON_ADDR) CMCON;
163 extern __sfr __at (ADRESH_ADDR) ADRESH;
164 extern __sfr __at (ADCON0_ADDR) ADCON0;
167 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
169 extern __sfr __at (TRISIO_ADDR) TRISIO;
171 extern __sfr __at (PIE1_ADDR) PIE1;
173 extern __sfr __at (PCON_ADDR) PCON;
175 extern __sfr __at (OSCCAL_ADDR) OSCCAL;
177 extern __sfr __at (WPU_ADDR) WPU;
178 extern __sfr __at (IOC_ADDR) IOC;
179 extern __sfr __at (IOCB_ADDR) IOCB;
181 extern __sfr __at (VRCON_ADDR) VRCON;
182 extern __sfr __at (EEDATA_ADDR) EEDATA;
183 extern __sfr __at (EEDAT_ADDR) EEDAT;
184 extern __sfr __at (EEADR_ADDR) EEADR;
185 extern __sfr __at (EECON1_ADDR) EECON1;
186 extern __sfr __at (EECON2_ADDR) EECON2;
187 extern __sfr __at (ADRESL_ADDR) ADRESL;
188 extern __sfr __at (ANSEL_ADDR) ANSEL;
191 //----- STATUS Bits --------------------------------------------------------
194 //----- GPIO Bits --------------------------------------------------------
197 //----- INTCON Bits --------------------------------------------------------
200 //----- PIR1 Bits ----------------------------------------------------------
203 //----- T1CON Bits ---------------------------------------------------------
206 //----- CMCON Bits --------------------------------------------------------
209 //----- ADCON0 Bits --------------------------------------------------------
212 //----- OPTION Bits --------------------------------------------------------
215 //----- PIE1 Bits ----------------------------------------------------------
218 //----- PCON Bits ----------------------------------------------------------
221 //----- OSCCAL Bits --------------------------------------------------------
224 //----- IOCB Bits --------------------------------------------------------
227 //----- IOC Bits --------------------------------------------------------
230 //----- VRCON Bits ---------------------------------------------------------
233 //----- EECON1 -------------------------------------------------------------
236 //----- ANSEL --------------------------------------------------------------
239 //==========================================================================
243 //==========================================================================
246 // __BADRAM H'06'-H'09', H'0D', H'11'-H'18', H'1A'-H'1D', H'60'-H'7F'
247 // __BADRAM H'86'-H'89', H'8D', H'8F', H'91'-H'94', H'97'-H'98', H'E0'-H'FF'
249 //==========================================================================
251 // Configuration Bits
253 //==========================================================================
255 #define _CPD_ON 0x3EFF
256 #define _CPD_OFF 0x3FFF
257 #define _CP_ON 0x3F7F
258 #define _CP_OFF 0x3FFF
259 #define _BODEN_ON 0x3FFF
260 #define _BODEN_OFF 0x3FBF
261 #define _MCLRE_ON 0x3FFF
262 #define _MCLRE_OFF 0x3FDF
263 #define _PWRTE_OFF 0x3FFF
264 #define _PWRTE_ON 0x3FEF
265 #define _WDT_ON 0x3FFF
266 #define _WDT_OFF 0x3FF7
267 #define _LP_OSC 0x3FF8
268 #define _XT_OSC 0x3FF9
269 #define _HS_OSC 0x3FFA
270 #define _EC_OSC 0x3FFB
271 #define _INTRC_OSC_NOCLKOUT 0x3FFC
272 #define _INTRC_OSC_CLKOUT 0x3FFD
273 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
274 #define _EXTRC_OSC_CLKOUT 0x3FFF
278 // ----- ADCON0 bits --------------------
281 unsigned char ADON:1;
283 unsigned char CHS0:1;
284 unsigned char CHS1:1;
287 unsigned char VCFG:1;
288 unsigned char ADFM:1;
292 unsigned char NOT_DONE:1;
302 unsigned char GO_DONE:1;
311 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
313 #define ADON ADCON0_bits.ADON
314 #define GO ADCON0_bits.GO
315 #define NOT_DONE ADCON0_bits.NOT_DONE
316 #define GO_DONE ADCON0_bits.GO_DONE
317 #define CHS0 ADCON0_bits.CHS0
318 #define CHS1 ADCON0_bits.CHS1
319 #define VCFG ADCON0_bits.VCFG
320 #define ADFM ADCON0_bits.ADFM
322 // ----- CMCON bits --------------------
329 unsigned char CINV:1;
331 unsigned char COUT:1;
335 extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;
337 #define CM0 CMCON_bits.CM0
338 #define CM1 CMCON_bits.CM1
339 #define CM2 CMCON_bits.CM2
340 #define CIS CMCON_bits.CIS
341 #define CINV CMCON_bits.CINV
342 #define COUT CMCON_bits.COUT
344 // ----- GPIO bits --------------------
357 unsigned char GPIO0:1;
358 unsigned char GPIO1:1;
359 unsigned char GPIO2:1;
360 unsigned char GPIO3:1;
361 unsigned char GPIO4:1;
362 unsigned char GPIO5:1;
367 extern volatile __GPIO_bits_t __at(GPIO_ADDR) GPIO_bits;
369 #define GP0 GPIO_bits.GP0
370 #define GPIO0 GPIO_bits.GPIO0
371 #define GP1 GPIO_bits.GP1
372 #define GPIO1 GPIO_bits.GPIO1
373 #define GP2 GPIO_bits.GP2
374 #define GPIO2 GPIO_bits.GPIO2
375 #define GP3 GPIO_bits.GP3
376 #define GPIO3 GPIO_bits.GPIO3
377 #define GP4 GPIO_bits.GP4
378 #define GPIO4 GPIO_bits.GPIO4
379 #define GP5 GPIO_bits.GP5
380 #define GPIO5 GPIO_bits.GPIO5
382 // ----- INTCON bits --------------------
385 unsigned char GPIF:1;
386 unsigned char INTF:1;
387 unsigned char T0IF:1;
388 unsigned char GPIE:1;
389 unsigned char INTE:1;
390 unsigned char T0IE:1;
391 unsigned char PEIE:1;
395 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
397 #define GPIF INTCON_bits.GPIF
398 #define INTF INTCON_bits.INTF
399 #define T0IF INTCON_bits.T0IF
400 #define GPIE INTCON_bits.GPIE
401 #define INTE INTCON_bits.INTE
402 #define T0IE INTCON_bits.T0IE
403 #define PEIE INTCON_bits.PEIE
404 #define GIE INTCON_bits.GIE
406 // ----- IOC bits --------------------
409 unsigned char IOC0:1;
410 unsigned char IOC1:1;
411 unsigned char IOC2:1;
412 unsigned char IOC3:1;
413 unsigned char IOC4:1;
414 unsigned char IOC5:1;
419 extern volatile __IOC_bits_t __at(IOC_ADDR) IOC_bits;
421 #define IOC0 IOC_bits.IOC0
422 #define IOC1 IOC_bits.IOC1
423 #define IOC2 IOC_bits.IOC2
424 #define IOC3 IOC_bits.IOC3
425 #define IOC4 IOC_bits.IOC4
426 #define IOC5 IOC_bits.IOC5
428 // ----- IOCB bits --------------------
431 unsigned char IOCB0:1;
432 unsigned char IOCB1:1;
433 unsigned char IOCB2:1;
434 unsigned char IOCB3:1;
435 unsigned char IOCB4:1;
436 unsigned char IOCB5:1;
441 extern volatile __IOCB_bits_t __at(IOCB_ADDR) IOCB_bits;
443 #define IOCB0 IOCB_bits.IOCB0
444 #define IOCB1 IOCB_bits.IOCB1
445 #define IOCB2 IOCB_bits.IOCB2
446 #define IOCB3 IOCB_bits.IOCB3
447 #define IOCB4 IOCB_bits.IOCB4
448 #define IOCB5 IOCB_bits.IOCB5
450 // ----- OPTION_REG bits --------------------
457 unsigned char T0SE:1;
458 unsigned char T0CS:1;
459 unsigned char INTEDG:1;
460 unsigned char NOT_GPPU:1;
462 } __OPTION_REG_bits_t;
463 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
465 #define PS0 OPTION_REG_bits.PS0
466 #define PS1 OPTION_REG_bits.PS1
467 #define PS2 OPTION_REG_bits.PS2
468 #define PSA OPTION_REG_bits.PSA
469 #define T0SE OPTION_REG_bits.T0SE
470 #define T0CS OPTION_REG_bits.T0CS
471 #define INTEDG OPTION_REG_bits.INTEDG
472 #define NOT_GPPU OPTION_REG_bits.NOT_GPPU
474 // ----- OSCCAL bits --------------------
479 unsigned char CAL0:1;
480 unsigned char CAL1:1;
481 unsigned char CAL2:1;
482 unsigned char CAL3:1;
483 unsigned char CAL4:1;
484 unsigned char CAL5:1;
487 extern volatile __OSCCAL_bits_t __at(OSCCAL_ADDR) OSCCAL_bits;
489 #define CAL0 OSCCAL_bits.CAL0
490 #define CAL1 OSCCAL_bits.CAL1
491 #define CAL2 OSCCAL_bits.CAL2
492 #define CAL3 OSCCAL_bits.CAL3
493 #define CAL4 OSCCAL_bits.CAL4
494 #define CAL5 OSCCAL_bits.CAL5
496 // ----- PCON bits --------------------
499 unsigned char NOT_BOD:1;
500 unsigned char NOT_POR:1;
509 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
511 #define NOT_BOD PCON_bits.NOT_BOD
512 #define NOT_POR PCON_bits.NOT_POR
514 // ----- PIE1 bits --------------------
517 unsigned char T1IE:1;
520 unsigned char CMIE:1;
523 unsigned char ADIE:1;
524 unsigned char EEIE:1;
527 unsigned char TMR1IE:1;
537 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
539 #define T1IE PIE1_bits.T1IE
540 #define TMR1IE PIE1_bits.TMR1IE
541 #define CMIE PIE1_bits.CMIE
542 #define ADIE PIE1_bits.ADIE
543 #define EEIE PIE1_bits.EEIE
545 // ----- PIR1 bits --------------------
548 unsigned char T1IF:1;
551 unsigned char CMIF:1;
554 unsigned char ADIF:1;
555 unsigned char EEIF:1;
558 unsigned char TMR1IF:1;
568 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
570 #define T1IF PIR1_bits.T1IF
571 #define TMR1IF PIR1_bits.TMR1IF
572 #define CMIF PIR1_bits.CMIF
573 #define ADIF PIR1_bits.ADIF
574 #define EEIF PIR1_bits.EEIF
576 // ----- STATUS bits --------------------
582 unsigned char NOT_PD:1;
583 unsigned char NOT_TO:1;
589 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
591 #define C STATUS_bits.C
592 #define DC STATUS_bits.DC
593 #define Z STATUS_bits.Z
594 #define NOT_PD STATUS_bits.NOT_PD
595 #define NOT_TO STATUS_bits.NOT_TO
596 #define RP0 STATUS_bits.RP0
597 #define RP1 STATUS_bits.RP1
598 #define IRP STATUS_bits.IRP
600 // ----- T1CON bits --------------------
603 unsigned char TMR1ON:1;
604 unsigned char TMR1CS:1;
605 unsigned char NOT_T1SYNC:1;
606 unsigned char T1OSCEN:1;
607 unsigned char T1CKPS0:1;
608 unsigned char T1CKPS1:1;
609 unsigned char TMR1GE:1;
613 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
615 #define TMR1ON T1CON_bits.TMR1ON
616 #define TMR1CS T1CON_bits.TMR1CS
617 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
618 #define T1OSCEN T1CON_bits.T1OSCEN
619 #define T1CKPS0 T1CON_bits.T1CKPS0
620 #define T1CKPS1 T1CON_bits.T1CKPS1
621 #define TMR1GE T1CON_bits.TMR1GE
623 // ----- VRCON bits --------------------
630 unsigned char ADCS0:1;
632 unsigned char ADCS2:1;
633 unsigned char VREN:1;
638 unsigned char WREN:1;
639 unsigned char WRERR:1;
641 unsigned char ADCS1:1;
646 unsigned char ANS0:1;
647 unsigned char ANS1:1;
648 unsigned char ANS2:1;
649 unsigned char ANS3:1;
656 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
658 #define VR0 VRCON_bits.VR0
659 #define RD VRCON_bits.RD
660 #define ANS0 VRCON_bits.ANS0
661 #define VR1 VRCON_bits.VR1
662 #define WR VRCON_bits.WR
663 #define ANS1 VRCON_bits.ANS1
664 #define VR2 VRCON_bits.VR2
665 #define WREN VRCON_bits.WREN
666 #define ANS2 VRCON_bits.ANS2
667 #define VR3 VRCON_bits.VR3
668 #define WRERR VRCON_bits.WRERR
669 #define ANS3 VRCON_bits.ANS3
670 #define ADCS0 VRCON_bits.ADCS0
671 #define VRR VRCON_bits.VRR
672 #define ADCS1 VRCON_bits.ADCS1
673 #define ADCS2 VRCON_bits.ADCS2
674 #define VREN VRCON_bits.VREN