2 // Register Declarations for Microchip 12F635 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define GPIO_ADDR 0x0005
35 #define PCLATH_ADDR 0x000A
36 #define INTCON_ADDR 0x000B
37 #define PIR1_ADDR 0x000C
38 #define TMR1L_ADDR 0x000E
39 #define TMR1H_ADDR 0x000F
40 #define T1CON_ADDR 0x0010
41 #define WDTCON_ADDR 0x0018
42 #define CMCON0_ADDR 0x0019
43 #define CMCON1_ADDR 0x001A
44 #define OPTION_REG_ADDR 0x0081
45 #define TRISA_ADDR 0x0085
46 #define TRISIO_ADDR 0x0085
47 #define PIE1_ADDR 0x008C
48 #define PCON_ADDR 0x008E
49 #define OSCCON_ADDR 0x008F
50 #define OSCTUNE_ADDR 0x0090
51 #define LVDCON_ADDR 0x0094
52 #define WPUDA_ADDR 0x0095
53 #define IOCA_ADDR 0x0096
54 #define WDA_ADDR 0x0097
55 #define VRCON_ADDR 0x0099
56 #define EEDAT_ADDR 0x009A
57 #define EEDATA_ADDR 0x009A
58 #define EEADR_ADDR 0x009B
59 #define EECON1_ADDR 0x009C
60 #define EECON2_ADDR 0x009D
61 #define CRCON_ADDR 0x0110
62 #define CRDAT0_ADDR 0x0111
63 #define CRDAT1_ADDR 0x0112
64 #define CRDAT2_ADDR 0x0113
65 #define CRDAT3_ADDR 0x0114
68 // Memory organization.
74 // P12F635.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
77 // This header file defines configurations, registers, and other useful bits of
78 // information for the PIC12F635 microcontroller. These names are taken to match
79 // the data sheets as closely as possible.
81 // Note that the processor must be selected before this file is
82 // included. The processor may be selected the following ways:
84 // 1. Command line switch:
85 // C:\ MPASM MYFILE.ASM /PIC12F635
86 // 2. LIST directive in the source file
88 // 3. Processor Type entry in the MPASM full-screen interface
90 //==========================================================================
94 //==========================================================================
95 //1.00 12/07/03 Original
96 //1.10 04/19/04 Release to match first revision datasheet --kjd
97 //1.20 06/07/04 Update and correct badram definitions --kjd
98 //==========================================================================
102 //==========================================================================
105 // MESSG "Processor-header file mismatch. Verify selected processor."
108 //==========================================================================
110 // Register Definitions
112 //==========================================================================
117 //----- Register Files------------------------------------------------------
119 extern __data __at (INDF_ADDR) volatile char INDF;
120 extern __sfr __at (TMR0_ADDR) TMR0;
121 extern __data __at (PCL_ADDR) volatile char PCL;
122 extern __sfr __at (STATUS_ADDR) STATUS;
123 extern __sfr __at (FSR_ADDR) FSR;
124 extern __sfr __at (PORTA_ADDR) PORTA;
125 extern __sfr __at (GPIO_ADDR) GPIO;
127 extern __sfr __at (PCLATH_ADDR) PCLATH;
128 extern __sfr __at (INTCON_ADDR) INTCON;
129 extern __sfr __at (PIR1_ADDR) PIR1;
131 extern __sfr __at (TMR1L_ADDR) TMR1L;
132 extern __sfr __at (TMR1H_ADDR) TMR1H;
133 extern __sfr __at (T1CON_ADDR) T1CON;
135 extern __sfr __at (WDTCON_ADDR) WDTCON;
136 extern __sfr __at (CMCON0_ADDR) CMCON0;
137 extern __sfr __at (CMCON1_ADDR) CMCON1;
140 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
142 extern __sfr __at (TRISA_ADDR) TRISA;
143 extern __sfr __at (TRISIO_ADDR) TRISIO;
145 extern __sfr __at (PIE1_ADDR) PIE1;
147 extern __sfr __at (PCON_ADDR) PCON;
148 extern __sfr __at (OSCCON_ADDR) OSCCON;
149 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
151 extern __sfr __at (LVDCON_ADDR) LVDCON;
152 extern __sfr __at (WPUDA_ADDR) WPUDA;
153 extern __sfr __at (IOCA_ADDR) IOCA;
154 extern __sfr __at (WDA_ADDR) WDA;
156 extern __sfr __at (VRCON_ADDR) VRCON;
157 extern __sfr __at (EEDAT_ADDR) EEDAT;
158 extern __sfr __at (EEDATA_ADDR) EEDATA;
159 extern __sfr __at (EEADR_ADDR) EEADR;
160 extern __sfr __at (EECON1_ADDR) EECON1;
161 extern __sfr __at (EECON2_ADDR) EECON2;
164 extern __sfr __at (CRCON_ADDR) CRCON;
165 extern __sfr __at (CRDAT0_ADDR) CRDAT0;
166 extern __sfr __at (CRDAT1_ADDR) CRDAT1;
167 extern __sfr __at (CRDAT2_ADDR) CRDAT2;
168 extern __sfr __at (CRDAT3_ADDR) CRDAT3;
170 //----- STATUS Bits --------------------------------------------------------
173 //----- INTCON Bits --------------------------------------------------------
176 //----- PIR1 Bits ----------------------------------------------------------
179 //----- T1CON Bits ---------------------------------------------------------
182 //----- WDTCON Bits --------------------------------------------------------
185 //----- CMCON0 Bits -------------------------------------------------------
188 //----- CMCON1 Bits -------------------------------------------------------
191 //----- OPTION Bits --------------------------------------------------------
194 //----- PIE1 Bits ----------------------------------------------------------
197 //----- PCON Bits ----------------------------------------------------------
200 //----- OSCCON Bits --------------------------------------------------------
203 //----- OSCTUNE Bits -------------------------------------------------------
206 //----- IOCA --------------------------------------------------------------
209 //----- EECON1 -------------------------------------------------------------
212 //----- VRCON ---------------------------------------------------------
216 //----- CRCON -------------------------------------------------------------
219 //----- LVDCON -------------------------------------------------------------
222 //----- WDA -------------------------------------------------------------
225 //----- WPUDA -------------------------------------------------------------
228 //----- PORTA -------------------------------------------------------------
231 //----- GPIO -------------------------------------------------------------
234 //==========================================================================
238 //==========================================================================
241 // __BADRAM H'06'-H'09', H'0D', H'11'-H'17', H'1B'-H'1F', H'20'-H'3F'
242 // __BADRAM H'86'-H'89', H'8D', H'91'-H'93', H'98', H'9E'-H'9F', H'A0'-H'EF'
243 // __BADRAM H'10C'-H'10F', H'115'-H'16F', H'106'-H'109', H'186'-H'189'
244 // __BADRAM H'18C'-H'1EF'
246 //==========================================================================
248 // Configuration Bits
250 //==========================================================================
251 #define _WUREN_ON 0x2FFF
252 #define _WUREN_OFF 0x3FFF
253 #define _FCMEN_ON 0x3FFF
254 #define _FCMEN_OFF 0x37FF
255 #define _IESO_ON 0x3FFF
256 #define _IESO_OFF 0x3BFF
257 #define _BOD_ON 0x3FFF
258 #define _BOD_NSLEEP 0x3EFF
259 #define _BOD_SBODEN 0x3DFF
260 #define _BOD_OFF 0x3CFF
261 #define _CPD_ON 0x3F7F
262 #define _CPD_OFF 0x3FFF
263 #define _CP_ON 0x3FBF
264 #define _CP_OFF 0x3FFF
265 #define _MCLRE_ON 0x3FFF
266 #define _MCLRE_OFF 0x3FDF
267 #define _PWRTE_OFF 0x3FFF
268 #define _PWRTE_ON 0x3FEF
269 #define _WDT_ON 0x3FFF
270 #define _WDT_OFF 0x3FF7
271 #define _LP_OSC 0x3FF8
272 #define _XT_OSC 0x3FF9
273 #define _HS_OSC 0x3FFA
274 #define _EC_OSC 0x3FFB
275 #define _INTRC_OSC_NOCLKOUT 0x3FFC
276 #define _INTRC_OSC_CLKOUT 0x3FFD
277 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
278 #define _EXTRC_OSC_CLKOUT 0x3FFF
282 // ----- CMCON0 bits --------------------
289 unsigned char C1INV:1;
291 unsigned char C1OUT:1;
295 extern volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits;
297 #define CM0 CMCON0_bits.CM0
298 #define CM1 CMCON0_bits.CM1
299 #define CM2 CMCON0_bits.CM2
300 #define CIS CMCON0_bits.CIS
301 #define C1INV CMCON0_bits.C1INV
302 #define C1OUT CMCON0_bits.C1OUT
304 // ----- CMCON1 bits --------------------
307 unsigned char C1SYNC:1;
308 unsigned char T1GSS:1;
317 extern volatile __CMCON1_bits_t __at(CMCON1_ADDR) CMCON1_bits;
319 #define C1SYNC CMCON1_bits.C1SYNC
320 #define T1GSS CMCON1_bits.T1GSS
322 // ----- INTCON bits --------------------
325 unsigned char RAIF:1;
326 unsigned char INTF:1;
327 unsigned char T0IF:1;
328 unsigned char RAIE:1;
329 unsigned char INTE:1;
330 unsigned char T0IE:1;
331 unsigned char PEIE:1;
335 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
337 #define RAIF INTCON_bits.RAIF
338 #define INTF INTCON_bits.INTF
339 #define T0IF INTCON_bits.T0IF
340 #define RAIE INTCON_bits.RAIE
341 #define INTE INTCON_bits.INTE
342 #define T0IE INTCON_bits.T0IE
343 #define PEIE INTCON_bits.PEIE
344 #define GIE INTCON_bits.GIE
346 // ----- OPTION_REG bits --------------------
353 unsigned char T0SE:1;
354 unsigned char T0CS:1;
355 unsigned char INTEDG:1;
356 unsigned char NOT_RAPU:1;
358 } __OPTION_REG_bits_t;
359 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
361 #define PS0 OPTION_REG_bits.PS0
362 #define PS1 OPTION_REG_bits.PS1
363 #define PS2 OPTION_REG_bits.PS2
364 #define PSA OPTION_REG_bits.PSA
365 #define T0SE OPTION_REG_bits.T0SE
366 #define T0CS OPTION_REG_bits.T0CS
367 #define INTEDG OPTION_REG_bits.INTEDG
368 #define NOT_RAPU OPTION_REG_bits.NOT_RAPU
370 // ----- OSCCON bits --------------------
376 unsigned char OSTS:1;
377 unsigned char IRCF0:1;
378 unsigned char IRCF1:1;
379 unsigned char IRCF2:1;
383 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
385 #define SCS OSCCON_bits.SCS
386 #define LTS OSCCON_bits.LTS
387 #define HTS OSCCON_bits.HTS
388 #define OSTS OSCCON_bits.OSTS
389 #define IRCF0 OSCCON_bits.IRCF0
390 #define IRCF1 OSCCON_bits.IRCF1
391 #define IRCF2 OSCCON_bits.IRCF2
393 // ----- OSCTUNE bits --------------------
396 unsigned char TUN0:1;
397 unsigned char TUN1:1;
398 unsigned char TUN2:1;
399 unsigned char TUN3:1;
400 unsigned char TUN4:1;
401 unsigned char IOCA5:1;
402 unsigned char ENC_DEC:1;
403 unsigned char VREN:1;
406 unsigned char IOCA0:1;
407 unsigned char IOCA1:1;
408 unsigned char IOCA2:1;
409 unsigned char IOCA3:1;
410 unsigned char IOCA4:1;
418 unsigned char WREN:1;
419 unsigned char WRERR:1;
420 unsigned char PLVDEN:1;
421 unsigned char IRVST:1;
430 unsigned char WDA4:1;
431 unsigned char WDA5:1;
436 unsigned char CRREG0:1;
437 unsigned char CRREG1:1;
438 unsigned char LVDL2:1;
440 unsigned char WPUDA4:1;
441 unsigned char WPUDA5:1;
446 unsigned char LVDL0:1;
447 unsigned char LVDL1:1;
448 unsigned char WDA2:1;
456 unsigned char WDA0:1;
457 unsigned char WDA1:1;
458 unsigned char WPUDA2:1;
466 unsigned char WPUDA0:1;
467 unsigned char WPUDA1:1;
496 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
498 #define TUN0 OSCTUNE_bits.TUN0
499 #define IOCA0 OSCTUNE_bits.IOCA0
500 #define RD OSCTUNE_bits.RD
501 #define VR0 OSCTUNE_bits.VR0
502 #define CRREG0 OSCTUNE_bits.CRREG0
503 #define LVDL0 OSCTUNE_bits.LVDL0
504 #define WDA0 OSCTUNE_bits.WDA0
505 #define WPUDA0 OSCTUNE_bits.WPUDA0
506 #define RA0 OSCTUNE_bits.RA0
507 #define GP0 OSCTUNE_bits.GP0
508 #define TUN1 OSCTUNE_bits.TUN1
509 #define IOCA1 OSCTUNE_bits.IOCA1
510 #define WR OSCTUNE_bits.WR
511 #define VR1 OSCTUNE_bits.VR1
512 #define CRREG1 OSCTUNE_bits.CRREG1
513 #define LVDL1 OSCTUNE_bits.LVDL1
514 #define WDA1 OSCTUNE_bits.WDA1
515 #define WPUDA1 OSCTUNE_bits.WPUDA1
516 #define RA1 OSCTUNE_bits.RA1
517 #define GP1 OSCTUNE_bits.GP1
518 #define TUN2 OSCTUNE_bits.TUN2
519 #define IOCA2 OSCTUNE_bits.IOCA2
520 #define WREN OSCTUNE_bits.WREN
521 #define VR2 OSCTUNE_bits.VR2
522 #define LVDL2 OSCTUNE_bits.LVDL2
523 #define WDA2 OSCTUNE_bits.WDA2
524 #define WPUDA2 OSCTUNE_bits.WPUDA2
525 #define RA2 OSCTUNE_bits.RA2
526 #define GP2 OSCTUNE_bits.GP2
527 #define TUN3 OSCTUNE_bits.TUN3
528 #define IOCA3 OSCTUNE_bits.IOCA3
529 #define WRERR OSCTUNE_bits.WRERR
530 #define VR3 OSCTUNE_bits.VR3
531 #define RA3 OSCTUNE_bits.RA3
532 #define GP3 OSCTUNE_bits.GP3
533 #define TUN4 OSCTUNE_bits.TUN4
534 #define IOCA4 OSCTUNE_bits.IOCA4
535 #define PLVDEN OSCTUNE_bits.PLVDEN
536 #define WDA4 OSCTUNE_bits.WDA4
537 #define WPUDA4 OSCTUNE_bits.WPUDA4
538 #define RA4 OSCTUNE_bits.RA4
539 #define GP4 OSCTUNE_bits.GP4
540 #define IOCA5 OSCTUNE_bits.IOCA5
541 #define VRR OSCTUNE_bits.VRR
542 #define IRVST OSCTUNE_bits.IRVST
543 #define WDA5 OSCTUNE_bits.WDA5
544 #define WPUDA5 OSCTUNE_bits.WPUDA5
545 #define RA5 OSCTUNE_bits.RA5
546 #define GP5 OSCTUNE_bits.GP5
547 #define ENC_DEC OSCTUNE_bits.ENC_DEC
548 #define VREN OSCTUNE_bits.VREN
549 #define GO OSCTUNE_bits.GO
551 // ----- PCON bits --------------------
554 unsigned char NOT_BOD:1;
555 unsigned char NOT_POR:1;
557 unsigned char NOT_WUR:1;
558 unsigned char SBODEN:1;
559 unsigned char ULPWUE:1;
564 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
566 #define NOT_BOD PCON_bits.NOT_BOD
567 #define NOT_POR PCON_bits.NOT_POR
568 #define NOT_WUR PCON_bits.NOT_WUR
569 #define SBODEN PCON_bits.SBODEN
570 #define ULPWUE PCON_bits.ULPWUE
572 // ----- PIE1 bits --------------------
575 unsigned char TMR1IE:1;
577 unsigned char OSFIE:1;
578 unsigned char C1IE:1;
580 unsigned char CRIE:1;
581 unsigned char LVDIE:1;
582 unsigned char EEIE:1;
585 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
587 #define TMR1IE PIE1_bits.TMR1IE
588 #define OSFIE PIE1_bits.OSFIE
589 #define C1IE PIE1_bits.C1IE
590 #define CRIE PIE1_bits.CRIE
591 #define LVDIE PIE1_bits.LVDIE
592 #define EEIE PIE1_bits.EEIE
594 // ----- PIR1 bits --------------------
597 unsigned char TMR1IF:1;
599 unsigned char OSFIF:1;
600 unsigned char C1IF:1;
602 unsigned char CRIF:1;
603 unsigned char LVDIF:1;
604 unsigned char EEIF:1;
607 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
609 #define TMR1IF PIR1_bits.TMR1IF
610 #define OSFIF PIR1_bits.OSFIF
611 #define C1IF PIR1_bits.C1IF
612 #define CRIF PIR1_bits.CRIF
613 #define LVDIF PIR1_bits.LVDIF
614 #define EEIF PIR1_bits.EEIF
616 // ----- STATUS bits --------------------
622 unsigned char NOT_PD:1;
623 unsigned char NOT_TO:1;
629 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
631 #define C STATUS_bits.C
632 #define DC STATUS_bits.DC
633 #define Z STATUS_bits.Z
634 #define NOT_PD STATUS_bits.NOT_PD
635 #define NOT_TO STATUS_bits.NOT_TO
636 #define RP0 STATUS_bits.RP0
637 #define RP1 STATUS_bits.RP1
638 #define IRP STATUS_bits.IRP
640 // ----- T1CON bits --------------------
643 unsigned char TMR1ON:1;
644 unsigned char TMR1CS:1;
645 unsigned char NOT_T1SYNC:1;
646 unsigned char T1OSCEN:1;
647 unsigned char T1CKPS0:1;
648 unsigned char T1CKPS1:1;
649 unsigned char TMR1GE:1;
650 unsigned char T1GINV:1;
653 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
655 #define TMR1ON T1CON_bits.TMR1ON
656 #define TMR1CS T1CON_bits.TMR1CS
657 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
658 #define T1OSCEN T1CON_bits.T1OSCEN
659 #define T1CKPS0 T1CON_bits.T1CKPS0
660 #define T1CKPS1 T1CON_bits.T1CKPS1
661 #define TMR1GE T1CON_bits.TMR1GE
662 #define T1GINV T1CON_bits.T1GINV
664 // ----- WDTCON bits --------------------
667 unsigned char SWDTEN:1;
668 unsigned char WDTPS0:1;
669 unsigned char WDTPS1:1;
670 unsigned char WDTPS2:1;
671 unsigned char WDTPS3:1;
677 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
679 #define SWDTEN WDTCON_bits.SWDTEN
680 #define WDTPS0 WDTCON_bits.WDTPS0
681 #define WDTPS1 WDTCON_bits.WDTPS1
682 #define WDTPS2 WDTCON_bits.WDTPS2
683 #define WDTPS3 WDTCON_bits.WDTPS3