2 // Register Declarations for Microchip 12F629 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define GPIO_ADDR 0x0005
34 #define PCLATH_ADDR 0x000A
35 #define INTCON_ADDR 0x000B
36 #define PIR1_ADDR 0x000C
37 #define TMR1L_ADDR 0x000E
38 #define TMR1H_ADDR 0x000F
39 #define T1CON_ADDR 0x0010
40 #define CMCON_ADDR 0x0019
41 #define OPTION_REG_ADDR 0x0081
42 #define TRISIO_ADDR 0x0085
43 #define PIE1_ADDR 0x008C
44 #define PCON_ADDR 0x008E
45 #define OSCCAL_ADDR 0x0090
46 #define WPU_ADDR 0x0095
47 #define IOCB_ADDR 0x0096
48 #define IOC_ADDR 0x0096
49 #define VRCON_ADDR 0x0099
50 #define EEDATA_ADDR 0x009A
51 #define EEDAT_ADDR 0x009A
52 #define EEADR_ADDR 0x009B
53 #define EECON1_ADDR 0x009C
54 #define EECON2_ADDR 0x009D
57 // Memory organization.
63 // P12F629.INC Standard Header File, Version 1.04 Microchip Technology, Inc.
66 // This header file defines configurations, registers, and other useful bits of
67 // information for the PIC12F629 microcontroller. These names are taken to match
68 // the data sheets as closely as possible.
70 // Note that the processor must be selected before this file is
71 // included. The processor may be selected the following ways:
73 // 1. Command line switch:
74 // C:\ MPASM MYFILE.ASM /PIC12F629
75 // 2. LIST directive in the source file
77 // 3. Processor Type entry in the MPASM full-screen interface
79 //==========================================================================
83 //==========================================================================
84 //1.04 07/01/02 Updated configuration bit names
85 //1.03 05/10/02 Added IOC register
86 //1.02 02/28/02 Updated per datasheet
87 //1.01 01/31/02 Updated per datasheet
88 //1.00 08/24/01 Original
90 //==========================================================================
94 //==========================================================================
97 // MESSG "Processor-header file mismatch. Verify selected processor."
100 //==========================================================================
102 // Register Definitions
104 //==========================================================================
109 //----- Register Files------------------------------------------------------
111 extern __data __at (INDF_ADDR) volatile char INDF;
112 extern __sfr __at (TMR0_ADDR) TMR0;
113 extern __data __at (PCL_ADDR) volatile char PCL;
114 extern __sfr __at (STATUS_ADDR) STATUS;
115 extern __sfr __at (FSR_ADDR) FSR;
116 extern __sfr __at (GPIO_ADDR) GPIO;
118 extern __sfr __at (PCLATH_ADDR) PCLATH;
119 extern __sfr __at (INTCON_ADDR) INTCON;
120 extern __sfr __at (PIR1_ADDR) PIR1;
122 extern __sfr __at (TMR1L_ADDR) TMR1L;
123 extern __sfr __at (TMR1H_ADDR) TMR1H;
124 extern __sfr __at (T1CON_ADDR) T1CON;
126 extern __sfr __at (CMCON_ADDR) CMCON;
128 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
130 extern __sfr __at (TRISIO_ADDR) TRISIO;
132 extern __sfr __at (PIE1_ADDR) PIE1;
134 extern __sfr __at (PCON_ADDR) PCON;
136 extern __sfr __at (OSCCAL_ADDR) OSCCAL;
138 extern __sfr __at (WPU_ADDR) WPU;
139 extern __sfr __at (IOCB_ADDR) IOCB;
140 extern __sfr __at (IOC_ADDR) IOC;
142 extern __sfr __at (VRCON_ADDR) VRCON;
143 extern __sfr __at (EEDATA_ADDR) EEDATA;
144 extern __sfr __at (EEDAT_ADDR) EEDAT;
145 extern __sfr __at (EEADR_ADDR) EEADR;
146 extern __sfr __at (EECON1_ADDR) EECON1;
147 extern __sfr __at (EECON2_ADDR) EECON2;
149 //----- STATUS Bits --------------------------------------------------------
152 //----- GPIO Bits --------------------------------------------------------
157 //----- INTCON Bits --------------------------------------------------------
160 //----- PIR1 Bits ----------------------------------------------------------
163 //----- T1CON Bits ---------------------------------------------------------
166 //----- CMCON Bits --------------------------------------------------------
169 //----- OPTION Bits --------------------------------------------------------
172 //----- PIE1 Bits ----------------------------------------------------------
175 //----- PCON Bits ----------------------------------------------------------
178 //----- OSCCAL Bits --------------------------------------------------------
181 //----- IOCB Bits --------------------------------------------------------
184 //----- IOC Bits --------------------------------------------------------
187 //----- VRCON Bits ---------------------------------------------------------
190 //----- EECON1 -------------------------------------------------------------
193 //==========================================================================
197 //==========================================================================
200 // __BADRAM H'06'-H'09', H'0D', H'11'-H'18', H'1A'-H'1F', H'60'-H'7F'
201 // __BADRAM H'86'-H'89', H'8D', H'8F', H'91'-H'94', H'97'-H'98', H'9E'-H'9F', H'E0'-H'FF'
203 //==========================================================================
205 // Configuration Bits
207 //==========================================================================
209 #define _CPD_ON 0x3EFF
210 #define _CPD_OFF 0x3FFF
211 #define _CP_ON 0x3F7F
212 #define _CP_OFF 0x3FFF
213 #define _BODEN_ON 0x3FFF
214 #define _BODEN_OFF 0x3FBF
215 #define _MCLRE_ON 0x3FFF
216 #define _MCLRE_OFF 0x3FDF
217 #define _PWRTE_OFF 0x3FFF
218 #define _PWRTE_ON 0x3FEF
219 #define _WDT_ON 0x3FFF
220 #define _WDT_OFF 0x3FF7
221 #define _LP_OSC 0x3FF8
222 #define _XT_OSC 0x3FF9
223 #define _HS_OSC 0x3FFA
224 #define _EC_OSC 0x3FFB
225 #define _INTRC_OSC_NOCLKOUT 0x3FFC
226 #define _INTRC_OSC_CLKOUT 0x3FFD
227 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
228 #define _EXTRC_OSC_CLKOUT 0x3FFF
232 // ----- CMCON bits --------------------
239 unsigned char CINV:1;
241 unsigned char COUT:1;
245 extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;
247 #define CM0 CMCON_bits.CM0
248 #define CM1 CMCON_bits.CM1
249 #define CM2 CMCON_bits.CM2
250 #define CIS CMCON_bits.CIS
251 #define CINV CMCON_bits.CINV
252 #define COUT CMCON_bits.COUT
254 // ----- GPIO bits --------------------
267 unsigned char GPIO0:1;
268 unsigned char GPIO1:1;
269 unsigned char GPIO2:1;
270 unsigned char GPIO3:1;
271 unsigned char GPIO4:1;
272 unsigned char GPIO5:1;
277 extern volatile __GPIO_bits_t __at(GPIO_ADDR) GPIO_bits;
279 #define GP0 GPIO_bits.GP0
280 #define GPIO0 GPIO_bits.GPIO0
281 #define GP1 GPIO_bits.GP1
282 #define GPIO1 GPIO_bits.GPIO1
283 #define GP2 GPIO_bits.GP2
284 #define GPIO2 GPIO_bits.GPIO2
285 #define GP3 GPIO_bits.GP3
286 #define GPIO3 GPIO_bits.GPIO3
287 #define GP4 GPIO_bits.GP4
288 #define GPIO4 GPIO_bits.GPIO4
289 #define GP5 GPIO_bits.GP5
290 #define GPIO5 GPIO_bits.GPIO5
292 // ----- INTCON bits --------------------
295 unsigned char GPIF:1;
296 unsigned char INTF:1;
297 unsigned char T0IF:1;
298 unsigned char GPIE:1;
299 unsigned char INTE:1;
300 unsigned char T0IE:1;
301 unsigned char PEIE:1;
305 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
307 #define GPIF INTCON_bits.GPIF
308 #define INTF INTCON_bits.INTF
309 #define T0IF INTCON_bits.T0IF
310 #define GPIE INTCON_bits.GPIE
311 #define INTE INTCON_bits.INTE
312 #define T0IE INTCON_bits.T0IE
313 #define PEIE INTCON_bits.PEIE
314 #define GIE INTCON_bits.GIE
316 // ----- IOC bits --------------------
319 unsigned char IOC0:1;
320 unsigned char IOC1:1;
321 unsigned char IOC2:1;
322 unsigned char IOC3:1;
323 unsigned char IOC4:1;
324 unsigned char IOC5:1;
329 extern volatile __IOC_bits_t __at(IOC_ADDR) IOC_bits;
331 #define IOC0 IOC_bits.IOC0
332 #define IOC1 IOC_bits.IOC1
333 #define IOC2 IOC_bits.IOC2
334 #define IOC3 IOC_bits.IOC3
335 #define IOC4 IOC_bits.IOC4
336 #define IOC5 IOC_bits.IOC5
338 // ----- IOCB bits --------------------
341 unsigned char IOCB0:1;
342 unsigned char IOCB1:1;
343 unsigned char IOCB2:1;
344 unsigned char IOCB3:1;
345 unsigned char IOCB4:1;
346 unsigned char IOCB5:1;
351 extern volatile __IOCB_bits_t __at(IOCB_ADDR) IOCB_bits;
353 #define IOCB0 IOCB_bits.IOCB0
354 #define IOCB1 IOCB_bits.IOCB1
355 #define IOCB2 IOCB_bits.IOCB2
356 #define IOCB3 IOCB_bits.IOCB3
357 #define IOCB4 IOCB_bits.IOCB4
358 #define IOCB5 IOCB_bits.IOCB5
360 // ----- OPTION_REG bits --------------------
367 unsigned char T0SE:1;
368 unsigned char T0CS:1;
369 unsigned char INTEDG:1;
370 unsigned char NOT_GPPU:1;
372 } __OPTION_REG_bits_t;
373 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
375 #define PS0 OPTION_REG_bits.PS0
376 #define PS1 OPTION_REG_bits.PS1
377 #define PS2 OPTION_REG_bits.PS2
378 #define PSA OPTION_REG_bits.PSA
379 #define T0SE OPTION_REG_bits.T0SE
380 #define T0CS OPTION_REG_bits.T0CS
381 #define INTEDG OPTION_REG_bits.INTEDG
382 #define NOT_GPPU OPTION_REG_bits.NOT_GPPU
384 // ----- OSCCAL bits --------------------
389 unsigned char CAL0:1;
390 unsigned char CAL1:1;
391 unsigned char CAL2:1;
392 unsigned char CAL3:1;
393 unsigned char CAL4:1;
394 unsigned char CAL5:1;
397 extern volatile __OSCCAL_bits_t __at(OSCCAL_ADDR) OSCCAL_bits;
399 #define CAL0 OSCCAL_bits.CAL0
400 #define CAL1 OSCCAL_bits.CAL1
401 #define CAL2 OSCCAL_bits.CAL2
402 #define CAL3 OSCCAL_bits.CAL3
403 #define CAL4 OSCCAL_bits.CAL4
404 #define CAL5 OSCCAL_bits.CAL5
406 // ----- PCON bits --------------------
409 unsigned char NOT_BOD:1;
410 unsigned char NOT_POR:1;
419 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
421 #define NOT_BOD PCON_bits.NOT_BOD
422 #define NOT_POR PCON_bits.NOT_POR
424 // ----- PIE1 bits --------------------
427 unsigned char T1IE:1;
430 unsigned char CMIE:1;
433 unsigned char ADIE:1;
434 unsigned char EEIE:1;
437 unsigned char TMR1IE:1;
447 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
449 #define T1IE PIE1_bits.T1IE
450 #define TMR1IE PIE1_bits.TMR1IE
451 #define CMIE PIE1_bits.CMIE
452 #define ADIE PIE1_bits.ADIE
453 #define EEIE PIE1_bits.EEIE
455 // ----- PIR1 bits --------------------
458 unsigned char T1IF:1;
461 unsigned char CMIF:1;
464 unsigned char ADIF:1;
465 unsigned char EEIF:1;
468 unsigned char TMR1IF:1;
478 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
480 #define T1IF PIR1_bits.T1IF
481 #define TMR1IF PIR1_bits.TMR1IF
482 #define CMIF PIR1_bits.CMIF
483 #define ADIF PIR1_bits.ADIF
484 #define EEIF PIR1_bits.EEIF
486 // ----- STATUS bits --------------------
492 unsigned char NOT_PD:1;
493 unsigned char NOT_TO:1;
499 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
501 #define C STATUS_bits.C
502 #define DC STATUS_bits.DC
503 #define Z STATUS_bits.Z
504 #define NOT_PD STATUS_bits.NOT_PD
505 #define NOT_TO STATUS_bits.NOT_TO
506 #define RP0 STATUS_bits.RP0
507 #define RP1 STATUS_bits.RP1
508 #define IRP STATUS_bits.IRP
510 // ----- T1CON bits --------------------
513 unsigned char TMR1ON:1;
514 unsigned char TMR1CS:1;
515 unsigned char NOT_T1SYNC:1;
516 unsigned char T1OSCEN:1;
517 unsigned char T1CKPS0:1;
518 unsigned char T1CKPS1:1;
519 unsigned char TMR1GE:1;
523 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
525 #define TMR1ON T1CON_bits.TMR1ON
526 #define TMR1CS T1CON_bits.TMR1CS
527 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
528 #define T1OSCEN T1CON_bits.T1OSCEN
529 #define T1CKPS0 T1CON_bits.T1CKPS0
530 #define T1CKPS1 T1CON_bits.T1CKPS1
531 #define TMR1GE T1CON_bits.TMR1GE
533 // ----- VRCON bits --------------------
543 unsigned char VREN:1;
548 unsigned char WREN:1;
549 unsigned char WRERR:1;
556 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
558 #define VR0 VRCON_bits.VR0
559 #define RD VRCON_bits.RD
560 #define VR1 VRCON_bits.VR1
561 #define WR VRCON_bits.WR
562 #define VR2 VRCON_bits.VR2
563 #define WREN VRCON_bits.WREN
564 #define VR3 VRCON_bits.VR3
565 #define WRERR VRCON_bits.WRERR
566 #define VRR VRCON_bits.VRR
567 #define VREN VRCON_bits.VREN