2 // Register Declarations for Microchip 12F629 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define GPIO_ADDR 0x0005
34 #define PCLATH_ADDR 0x000A
35 #define INTCON_ADDR 0x000B
36 #define PIR1_ADDR 0x000C
37 #define TMR1L_ADDR 0x000E
38 #define TMR1H_ADDR 0x000F
39 #define T1CON_ADDR 0x0010
40 #define CMCON_ADDR 0x0019
41 #define OPTION_REG_ADDR 0x0081
42 #define TRISIO_ADDR 0x0085
43 #define PIE1_ADDR 0x008C
44 #define PCON_ADDR 0x008E
45 #define OSCCAL_ADDR 0x0090
46 #define WPU_ADDR 0x0095
47 #define IOCB_ADDR 0x0096
48 #define IOC_ADDR 0x0096
49 #define VRCON_ADDR 0x0099
50 #define EEDATA_ADDR 0x009A
51 #define EEDAT_ADDR 0x009A
52 #define EEADR_ADDR 0x009B
53 #define EECON1_ADDR 0x009C
54 #define EECON2_ADDR 0x009D
57 // Memory organization.
60 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
61 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
62 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
63 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
64 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
65 #pragma memmap GPIO_ADDR GPIO_ADDR SFR 0x000 // GPIO
66 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
67 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
68 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
69 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
70 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
71 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
72 #pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000 // CMCON
73 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
74 #pragma memmap TRISIO_ADDR TRISIO_ADDR SFR 0x000 // TRISIO
75 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
76 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
77 #pragma memmap OSCCAL_ADDR OSCCAL_ADDR SFR 0x000 // OSCCAL
78 #pragma memmap WPU_ADDR WPU_ADDR SFR 0x000 // WPU
79 #pragma memmap IOCB_ADDR IOCB_ADDR SFR 0x000 // IOCB
80 #pragma memmap IOC_ADDR IOC_ADDR SFR 0x000 // IOC
81 #pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON
82 #pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA
83 #pragma memmap EEDAT_ADDR EEDAT_ADDR SFR 0x000 // EEDAT
84 #pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR
85 #pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1
86 #pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2
90 // P12F629.INC Standard Header File, Version 1.04 Microchip Technology, Inc.
93 // This header file defines configurations, registers, and other useful bits of
94 // information for the PIC12F629 microcontroller. These names are taken to match
95 // the data sheets as closely as possible.
97 // Note that the processor must be selected before this file is
98 // included. The processor may be selected the following ways:
100 // 1. Command line switch:
101 // C:\ MPASM MYFILE.ASM /PIC12F629
102 // 2. LIST directive in the source file
104 // 3. Processor Type entry in the MPASM full-screen interface
106 //==========================================================================
110 //==========================================================================
111 //1.04 07/01/02 Updated configuration bit names
112 //1.03 05/10/02 Added IOC register
113 //1.02 02/28/02 Updated per datasheet
114 //1.01 01/31/02 Updated per datasheet
115 //1.00 08/24/01 Original
117 //==========================================================================
121 //==========================================================================
124 // MESSG "Processor-header file mismatch. Verify selected processor."
127 //==========================================================================
129 // Register Definitions
131 //==========================================================================
136 //----- Register Files------------------------------------------------------
138 extern __data __at (INDF_ADDR) volatile char INDF;
139 extern __sfr __at (TMR0_ADDR) TMR0;
140 extern __data __at (PCL_ADDR) volatile char PCL;
141 extern __sfr __at (STATUS_ADDR) STATUS;
142 extern __sfr __at (FSR_ADDR) FSR;
143 extern __sfr __at (GPIO_ADDR) GPIO;
145 extern __sfr __at (PCLATH_ADDR) PCLATH;
146 extern __sfr __at (INTCON_ADDR) INTCON;
147 extern __sfr __at (PIR1_ADDR) PIR1;
149 extern __sfr __at (TMR1L_ADDR) TMR1L;
150 extern __sfr __at (TMR1H_ADDR) TMR1H;
151 extern __sfr __at (T1CON_ADDR) T1CON;
153 extern __sfr __at (CMCON_ADDR) CMCON;
155 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
157 extern __sfr __at (TRISIO_ADDR) TRISIO;
159 extern __sfr __at (PIE1_ADDR) PIE1;
161 extern __sfr __at (PCON_ADDR) PCON;
163 extern __sfr __at (OSCCAL_ADDR) OSCCAL;
165 extern __sfr __at (WPU_ADDR) WPU;
166 extern __sfr __at (IOCB_ADDR) IOCB;
167 extern __sfr __at (IOC_ADDR) IOC;
169 extern __sfr __at (VRCON_ADDR) VRCON;
170 extern __sfr __at (EEDATA_ADDR) EEDATA;
171 extern __sfr __at (EEDAT_ADDR) EEDAT;
172 extern __sfr __at (EEADR_ADDR) EEADR;
173 extern __sfr __at (EECON1_ADDR) EECON1;
174 extern __sfr __at (EECON2_ADDR) EECON2;
176 //----- STATUS Bits --------------------------------------------------------
179 //----- GPIO Bits --------------------------------------------------------
184 //----- INTCON Bits --------------------------------------------------------
187 //----- PIR1 Bits ----------------------------------------------------------
190 //----- T1CON Bits ---------------------------------------------------------
193 //----- CMCON Bits --------------------------------------------------------
196 //----- OPTION Bits --------------------------------------------------------
199 //----- PIE1 Bits ----------------------------------------------------------
202 //----- PCON Bits ----------------------------------------------------------
205 //----- OSCCAL Bits --------------------------------------------------------
208 //----- IOCB Bits --------------------------------------------------------
211 //----- IOC Bits --------------------------------------------------------
214 //----- VRCON Bits ---------------------------------------------------------
217 //----- EECON1 -------------------------------------------------------------
220 //==========================================================================
224 //==========================================================================
227 // __BADRAM H'06'-H'09', H'0D', H'11'-H'18', H'1A'-H'1F', H'60'-H'7F'
228 // __BADRAM H'86'-H'89', H'8D', H'8F', H'91'-H'94', H'97'-H'98', H'9E'-H'9F', H'E0'-H'FF'
230 //==========================================================================
232 // Configuration Bits
234 //==========================================================================
236 #define _CPD_ON 0x3EFF
237 #define _CPD_OFF 0x3FFF
238 #define _CP_ON 0x3F7F
239 #define _CP_OFF 0x3FFF
240 #define _BODEN_ON 0x3FFF
241 #define _BODEN_OFF 0x3FBF
242 #define _MCLRE_ON 0x3FFF
243 #define _MCLRE_OFF 0x3FDF
244 #define _PWRTE_OFF 0x3FFF
245 #define _PWRTE_ON 0x3FEF
246 #define _WDT_ON 0x3FFF
247 #define _WDT_OFF 0x3FF7
248 #define _LP_OSC 0x3FF8
249 #define _XT_OSC 0x3FF9
250 #define _HS_OSC 0x3FFA
251 #define _EC_OSC 0x3FFB
252 #define _INTRC_OSC_NOCLKOUT 0x3FFC
253 #define _INTRC_OSC_CLKOUT 0x3FFD
254 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
255 #define _EXTRC_OSC_CLKOUT 0x3FFF
259 // ----- CMCON bits --------------------
266 unsigned char CINV:1;
268 unsigned char COUT:1;
272 extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;
274 #define CM0 CMCON_bits.CM0
275 #define CM1 CMCON_bits.CM1
276 #define CM2 CMCON_bits.CM2
277 #define CIS CMCON_bits.CIS
278 #define CINV CMCON_bits.CINV
279 #define COUT CMCON_bits.COUT
281 // ----- GPIO bits --------------------
294 unsigned char GPIO0:1;
295 unsigned char GPIO1:1;
296 unsigned char GPIO2:1;
297 unsigned char GPIO3:1;
298 unsigned char GPIO4:1;
299 unsigned char GPIO5:1;
304 extern volatile __GPIO_bits_t __at(GPIO_ADDR) GPIO_bits;
306 #define GP0 GPIO_bits.GP0
307 #define GPIO0 GPIO_bits.GPIO0
308 #define GP1 GPIO_bits.GP1
309 #define GPIO1 GPIO_bits.GPIO1
310 #define GP2 GPIO_bits.GP2
311 #define GPIO2 GPIO_bits.GPIO2
312 #define GP3 GPIO_bits.GP3
313 #define GPIO3 GPIO_bits.GPIO3
314 #define GP4 GPIO_bits.GP4
315 #define GPIO4 GPIO_bits.GPIO4
316 #define GP5 GPIO_bits.GP5
317 #define GPIO5 GPIO_bits.GPIO5
319 // ----- INTCON bits --------------------
322 unsigned char GPIF:1;
323 unsigned char INTF:1;
324 unsigned char T0IF:1;
325 unsigned char GPIE:1;
326 unsigned char INTE:1;
327 unsigned char T0IE:1;
328 unsigned char PEIE:1;
332 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
334 #define GPIF INTCON_bits.GPIF
335 #define INTF INTCON_bits.INTF
336 #define T0IF INTCON_bits.T0IF
337 #define GPIE INTCON_bits.GPIE
338 #define INTE INTCON_bits.INTE
339 #define T0IE INTCON_bits.T0IE
340 #define PEIE INTCON_bits.PEIE
341 #define GIE INTCON_bits.GIE
343 // ----- IOC bits --------------------
346 unsigned char IOC0:1;
347 unsigned char IOC1:1;
348 unsigned char IOC2:1;
349 unsigned char IOC3:1;
350 unsigned char IOC4:1;
351 unsigned char IOC5:1;
356 extern volatile __IOC_bits_t __at(IOC_ADDR) IOC_bits;
358 #define IOC0 IOC_bits.IOC0
359 #define IOC1 IOC_bits.IOC1
360 #define IOC2 IOC_bits.IOC2
361 #define IOC3 IOC_bits.IOC3
362 #define IOC4 IOC_bits.IOC4
363 #define IOC5 IOC_bits.IOC5
365 // ----- IOCB bits --------------------
368 unsigned char IOCB0:1;
369 unsigned char IOCB1:1;
370 unsigned char IOCB2:1;
371 unsigned char IOCB3:1;
372 unsigned char IOCB4:1;
373 unsigned char IOCB5:1;
378 extern volatile __IOCB_bits_t __at(IOCB_ADDR) IOCB_bits;
380 #define IOCB0 IOCB_bits.IOCB0
381 #define IOCB1 IOCB_bits.IOCB1
382 #define IOCB2 IOCB_bits.IOCB2
383 #define IOCB3 IOCB_bits.IOCB3
384 #define IOCB4 IOCB_bits.IOCB4
385 #define IOCB5 IOCB_bits.IOCB5
387 // ----- OPTION_REG bits --------------------
394 unsigned char T0SE:1;
395 unsigned char T0CS:1;
396 unsigned char INTEDG:1;
397 unsigned char NOT_GPPU:1;
399 } __OPTION_REG_bits_t;
400 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
402 #define PS0 OPTION_REG_bits.PS0
403 #define PS1 OPTION_REG_bits.PS1
404 #define PS2 OPTION_REG_bits.PS2
405 #define PSA OPTION_REG_bits.PSA
406 #define T0SE OPTION_REG_bits.T0SE
407 #define T0CS OPTION_REG_bits.T0CS
408 #define INTEDG OPTION_REG_bits.INTEDG
409 #define NOT_GPPU OPTION_REG_bits.NOT_GPPU
411 // ----- OSCCAL bits --------------------
416 unsigned char CAL0:1;
417 unsigned char CAL1:1;
418 unsigned char CAL2:1;
419 unsigned char CAL3:1;
420 unsigned char CAL4:1;
421 unsigned char CAL5:1;
424 extern volatile __OSCCAL_bits_t __at(OSCCAL_ADDR) OSCCAL_bits;
426 #define CAL0 OSCCAL_bits.CAL0
427 #define CAL1 OSCCAL_bits.CAL1
428 #define CAL2 OSCCAL_bits.CAL2
429 #define CAL3 OSCCAL_bits.CAL3
430 #define CAL4 OSCCAL_bits.CAL4
431 #define CAL5 OSCCAL_bits.CAL5
433 // ----- PCON bits --------------------
436 unsigned char NOT_BOD:1;
437 unsigned char NOT_POR:1;
446 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
448 #define NOT_BOD PCON_bits.NOT_BOD
449 #define NOT_POR PCON_bits.NOT_POR
451 // ----- PIE1 bits --------------------
454 unsigned char T1IE:1;
457 unsigned char CMIE:1;
460 unsigned char ADIE:1;
461 unsigned char EEIE:1;
464 unsigned char TMR1IE:1;
474 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
476 #define T1IE PIE1_bits.T1IE
477 #define TMR1IE PIE1_bits.TMR1IE
478 #define CMIE PIE1_bits.CMIE
479 #define ADIE PIE1_bits.ADIE
480 #define EEIE PIE1_bits.EEIE
482 // ----- PIR1 bits --------------------
485 unsigned char T1IF:1;
488 unsigned char CMIF:1;
491 unsigned char ADIF:1;
492 unsigned char EEIF:1;
495 unsigned char TMR1IF:1;
505 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
507 #define T1IF PIR1_bits.T1IF
508 #define TMR1IF PIR1_bits.TMR1IF
509 #define CMIF PIR1_bits.CMIF
510 #define ADIF PIR1_bits.ADIF
511 #define EEIF PIR1_bits.EEIF
513 // ----- STATUS bits --------------------
519 unsigned char NOT_PD:1;
520 unsigned char NOT_TO:1;
526 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
528 #define C STATUS_bits.C
529 #define DC STATUS_bits.DC
530 #define Z STATUS_bits.Z
531 #define NOT_PD STATUS_bits.NOT_PD
532 #define NOT_TO STATUS_bits.NOT_TO
533 #define RP0 STATUS_bits.RP0
534 #define RP1 STATUS_bits.RP1
535 #define IRP STATUS_bits.IRP
537 // ----- T1CON bits --------------------
540 unsigned char TMR1ON:1;
541 unsigned char TMR1CS:1;
542 unsigned char NOT_T1SYNC:1;
543 unsigned char T1OSCEN:1;
544 unsigned char T1CKPS0:1;
545 unsigned char T1CKPS1:1;
546 unsigned char TMR1GE:1;
550 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
552 #define TMR1ON T1CON_bits.TMR1ON
553 #define TMR1CS T1CON_bits.TMR1CS
554 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
555 #define T1OSCEN T1CON_bits.T1OSCEN
556 #define T1CKPS0 T1CON_bits.T1CKPS0
557 #define T1CKPS1 T1CON_bits.T1CKPS1
558 #define TMR1GE T1CON_bits.TMR1GE
560 // ----- VRCON bits --------------------
570 unsigned char VREN:1;
575 unsigned char WREN:1;
576 unsigned char WRERR:1;
583 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
585 #define VR0 VRCON_bits.VR0
586 #define RD VRCON_bits.RD
587 #define VR1 VRCON_bits.VR1
588 #define WR VRCON_bits.WR
589 #define VR2 VRCON_bits.VR2
590 #define WREN VRCON_bits.WREN
591 #define VR3 VRCON_bits.VR3
592 #define WRERR VRCON_bits.WRERR
593 #define VRR VRCON_bits.VRR
594 #define VREN VRCON_bits.VREN