1 /*-------------------------------------------------------------------------
2 Register Declarations for the mcs51 compatible microcontrollers
4 Written By - Bela Torok / bela.torok@kssg.ch (November 2000)
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the
8 Free Software Foundation; either version 2, or (at your option) any
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 In other words, you are welcome to use, share and improve this program.
21 You are forbidden to forbid anyone else to use, share and improve
22 what you give them. Help stamp out software-hoarding!
27 Version 1.0 Nov 2, 2000 - B. Torok / bela.torok@kssg.ch
28 Initial release, supported microcontrollers:
29 8051, 8052, Atmel AT89C1051, AT89C2051, AT89C4051,
30 Infineon / Siemens SAB80515, SAB80535, SAB80515A
32 Version 1.0.1 (Nov 3, 2000)
33 SAB80515A definitions revised by Michael Schmitt / michael.schmitt@t-online.de
35 Version 1.0.2 (Nov 6, 2000)
36 T2CON bug corrected 8052 and SABX microcontrollers have different T2CONs
37 Support for for the Atmel AT89C52, AT80LV52, AT89C55, AT80LV55
38 Support for the Dallas DS80C320 and DS80C323 microcontrollers
39 microcontrollers - B. Torok / bela.torok@kssg.ch
41 Version 1.0.3 (Nov 7, 2000)
42 SAB80517 definitions added by Michael Schmitt / michael.schmitt@t-online.de
43 Dallas AT89S53 definitions added by B. Torok / bela.torok@kssg.ch
44 Dallas DS87C520 and DS83C520 definitions added by B. Torok / bela.torok@kssg.ch
46 Version 1.0.4 (Nov 9, 2000)
47 To simplify the identication of registers, a large number of definitios
48 were renamed. Long register names now (hopefully) clearly define the
49 function of the registers.
50 Dallas DS89C420 definitions added by B. Torok / bela.torok@kssg.ch
52 Version 1.0.5 (Dec 15, 2000)
53 Definitions added: #ifdef MCS51REG_EXTERNAL_ROM
54 #ifdef MCS51REG_EXTERNAL_RAM
55 #ifdef MCS51REG_DISABLE_WARNINGS
57 Version 1.0.6 (Dec 15, 2000)
58 Correction, if External Memory (RAM or ROM) ist used P2 is used for the
59 upper 8 Adressbits instead of P3
61 Adding support for additional microcontrollers:
62 -----------------------------------------------
64 1. Don't modify this file!!!
66 2. Insert your code in a separate file e.g.: mcs51reg_update.h and include
67 this after the #define HEADER_MCS51REG statement in this file
69 3. The mcs51reg_update.h file should contain following definitions:
71 a. An entry with the inventory of the register set of the
72 microcontroller in the "Describe microcontrollers" section.
74 b. If necessary add entry(s) in for registers not defined in this file
76 c. Define interrupt vectors
78 4. Send me the file mcs51reg_update.h ( bela.torok@kssg.ch ).
79 I'm going to verify/merge new definitions to this file.
82 Microcontroller support:
84 Use one of the following options:
86 1. use #include <mcs51reg.h> in your program & define MICROCONTROLLER_XXXX in your makefile.
88 2. use following definitions prior the
89 #include <mcs51reg.h> line in your program:
91 #define MICROCONTROLLER_8052 -> 8052 type microcontroller
93 #define MICROCONTROLLER_AT89CX051 -> Atmel AT89C1051, AT89C2051 and AT89C4051 microcontrollers
96 Use only one of the following definitions!!!
98 Supported Microcontrollers:
101 MICROCONTROLLER_8051 8051
102 MICROCONTROLLER_8052 8052
103 MICROCONTROLLER_AT89CX051 Atmel AT89C1051, AT89C2051 and AT89C4051
104 MICROCONTROLLER_AT89S53 Atmel AT89S53 microcontroller
105 MICROCONTROLLER_AT89X52 Atmel AT89C52 and AT80LV52 microcontrollers
106 MICROCONTROLLER_AT89X55 Atmel AT89C55 and AT80LV55 microcontrollers
107 MICROCONTROLLER_DS80C32X Dallas DS80C320 and DS80C323 microcontrollers
108 MICROCONTROLLER_DS89C420 Dallas DS89C420 microcontroller
109 MICROCONTROLLER_DS8XC520 Dallas DS87C520 and DS83C520 microcontrollers
110 MICROCONTROLLER_SAB80515 Infineon / Siemens SAB80515 & SAB80535
111 MICROCONTROLLER_SAB80515A Infineon / Siemens SAB80515A
112 MICROCONTROLLER_SAB80517 Infineon / Siemens SAB80517
114 Additional definitions (use them prior the #include mcs51reg.h statement):
116 Ports P0 & P2 are not available for the programmer if external ROM used.
117 Use statement "#define MCS51REG_EXTERNAL_RAM" to undefine P0 & P2.
119 Ports P0, P2, P3_6, WR, P3_7 & RD are not available for the programmer if
120 external RAM is used.
121 Use statement "#define MCS51REG_EXTERNAL_RAM" to undefine P0, P2,
124 #define MCS51REG_DISABLE_WARNINGS -> disables warnings
126 -----------------------------------------------------------------------*/
129 #ifndef HEADER_MCS51REG
130 #define HEADER_MCS51REG
132 ///////////////////////////////////////////////////////
133 /// Insert header here (for developers only) ///
134 /// remove "//" from the begining of the next line ///
135 //#include "mcs51reg_update.h" ///
136 ///////////////////////////////////////////////////////
138 //////////////////////////////////
139 /// Describe microcontrollers ///
140 /// (inventory of registers) ///
141 //////////////////////////////////
143 // definitions for the 8051
144 #ifdef MICROCONTROLLER_8051
145 #ifdef MICROCONTROLLER_DEFINED
146 #define MCS51REG_ERROR
148 #ifndef MICROCONTROLLER_DEFINED
149 #define MICROCONTROLLER_DEFINED
151 #ifndef MCS51REG_DISABLE_WARNINGS
152 #warning Selected HW: 8051
158 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
169 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
171 #define IP___x__x__x__PS__PT1__PX1__PT0__PX0
176 // end of definitions for the 8051
179 // definitions for the 8052 microcontroller
180 #ifdef MICROCONTROLLER_8052
181 #ifdef MICROCONTROLLER_DEFINED
182 #define MCS51REG_ERROR
184 #ifndef MICROCONTROLLER_DEFINED
185 #define MICROCONTROLLER_DEFINED
187 #ifndef MCS51REG_DISABLE_WARNINGS
188 #warning Selected HW: 8052
195 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
206 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
208 #define IP___x__x__PT2__PS__PT1__PX1__PT0__PX0
212 // 8052 specific registers
213 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
219 // end of definitions for the 8052 microcontroller
222 // definitionsons for the Atmel
223 // AT89C1051, AT89C2051 and AT89C4051 microcontrollers
224 #ifdef MICROCONTROLLER_AT89CX051
225 #ifdef MICROCONTROLLER_DEFINED
226 #define MCS51REG_ERROR
228 #ifndef MICROCONTROLLER_DEFINED
229 #define MICROCONTROLLER_DEFINED
231 #ifndef MCS51REG_DISABLE_WARNINGS
232 #warning Selected HW: Atmel AT89Cx051
234 // 8051 register set without P0 & P2
238 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
248 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
250 #define IP___x__x__x__PS__PT1__PX1__PT0__PX0
255 // end of definitionsons for the Atmel
256 // AT89C1051, AT89C2051 and AT89C4051 microcontrollers
259 // definitions for the Atmel AT89S53
260 #ifdef MICROCONTROLLER_AT89S53
261 #ifdef MICROCONTROLLER_DEFINED
262 #define MCS51REG_ERROR
264 #ifndef MICROCONTROLLER_DEFINED
265 #define MICROCONTROLLER_DEFINED
267 #ifndef MCS51REG_DISABLE_WARNINGS
268 #warning Selected HW: AT89S53
275 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
286 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
288 #define IP___x__x__PT2__PS__PT1__PX1__PT0__PX0
292 // 8052 specific registers
293 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
298 // AT89S53 specific register
300 #define P1_EXT__x__x__x__x__x__x__T2EX__T2
308 // end of definitions for the Atmel AT89S53 microcontroller
311 // definitions for the Atmel AT89C52 and AT89LV52 microcontrollers
312 #ifdef MICROCONTROLLER_AT89X52
313 #ifdef MICROCONTROLLER_DEFINED
314 #define MCS51REG_ERROR
316 #ifndef MICROCONTROLLER_DEFINED
317 #define MICROCONTROLLER_DEFINED
319 #ifndef MCS51REG_DISABLE_WARNINGS
320 #warning Selected HW: AT89C52 or AT89LV52
327 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
338 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
340 #define IP___x__x__PT2__PS__PT1__PX1__PT0__PX0
344 // 8052 specific registers
345 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
350 // AT89X55 specific register
352 #define P1_EXT__x__x__x__x__x__x__T2EX__T2
354 // end of definitions for the Atmel AT89C52 and AT89LV52 microcontrollers
357 // definitions for the Atmel AT89C55 and AT89LV55 microcontrollers
358 #ifdef MICROCONTROLLER_AT89X55
359 #ifdef MICROCONTROLLER_DEFINED
360 #define MCS51REG_ERROR
362 #ifndef MICROCONTROLLER_DEFINED
363 #define MICROCONTROLLER_DEFINED
365 #ifndef MCS51REG_DISABLE_WARNINGS
366 #warning Selected HW: AT89C55 or AT89LV55
373 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
384 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
386 #define IP___x__x__PT2__PS__PT1__PX1__PT0__PX0
390 // 8052 specific registers
391 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
396 // AT89X55 specific register
398 #define P1_EXT__x__x__x__x__x__x__T2EX__T2
400 // end of definitions for the Atmel AT89C55 and AT89LV55 microcontrollers
403 // definitions for the Dallas DS80C320 and DS80C323 microcontrollers
404 #ifdef MICROCONTROLLER_DS80C32X
405 #ifdef MICROCONTROLLER_DEFINED
406 #define MCS51REG_ERROR
408 #ifndef MICROCONTROLLER_DEFINED
409 #define MICROCONTROLLER_DEFINED
411 #ifndef MCS51REG_DISABLE_WARNINGS
412 #warning Selected HW: Dallas DS80C320 or DS80C323
419 #define PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
430 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
432 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
436 // 8052 specific registers
437 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
442 // DS80C320 specific register
445 #define DPS__x__x__x__x__x__x__x__SEL
447 #define EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
454 #define STATUS__PIP__HIP__LIP__x__x__x__x__x
457 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
462 // end of definitions for the Dallas DS80C320 and DS80C323 microcontrollers
465 // definitions for the Dallas DS89C420 microcontroller
466 #ifdef MICROCONTROLLER_DS89C420
467 #ifdef MICROCONTROLLER_DEFINED
468 #define MCS51REG_ERROR
470 #ifndef MICROCONTROLLER_DEFINED
471 #define MICROCONTROLLER_DEFINED
473 #ifndef MCS51REG_DISABLE_WARNINGS
474 #warning Selected HW: Dallas DS89C420
481 #define PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
492 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
494 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
498 // 8052 specific registers
499 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
504 // DS8XC520 specific registers
508 #define DPS__ID1__ID0__TSL__AID__x__x__x__SEL
511 #define IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
512 #define IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
513 #define EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
521 #define STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
524 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
526 #define ROMSIZE__HBPF__BPF__TE__MOVCX__PRAME__RMS2__RMS1__RMS0
531 // end of definitions for the Dallas DS89C420 microcontroller
534 // definitions for the Dallas DS87C520 and DS83C520 microcontrollers
535 #ifdef MICROCONTROLLER_DS8XC520
536 #ifdef MICROCONTROLLER_DEFINED
537 #define MCS51REG_ERROR
539 #ifndef MICROCONTROLLER_DEFINED
540 #define MICROCONTROLLER_DEFINED
542 #ifndef MCS51REG_DISABLE_WARNINGS
543 #warning Selected HW: Dallas DS87C520 or DS85C520
550 #define PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
561 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
563 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
567 // 8052 specific registers
568 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
573 // DS8XC520 specific registers
576 #define DPS__x__x__x__x__x__x__x__SEL
578 #define EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
586 #define STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
589 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
591 #define ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0
597 // end of definitions for the Dallas DS87C520 and DS83C520 microcontrollers
600 // definitions for the Infineon / Siemens SAB80515 & SAB80535
601 #ifdef MICROCONTROLLER_SAB80515
602 #ifdef MICROCONTROLLER_DEFINED
603 #define MCS51REG_ERROR
605 #ifndef MICROCONTROLLER_DEFINED
606 #define MICROCONTROLLER_DEFINED
608 #ifndef MCS51REG_DISABLE_WARNINGS
609 #warning Selected HW: Infineon / Siemens SAB80515 & SAB80535
611 // 8051 register set without IP
616 #define PCON__SMOD__x__x__x__x__x__x__x
627 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
632 // SAB80515 specific registers
633 #define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
634 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
644 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
651 #define DAPR__SAB80515
655 // end of definitions for the Infineon / Siemens SAB80515
658 // definitions for the Infineon / Siemens SAB80515A
659 #ifdef MICROCONTROLLER_SAB80515A
660 #ifdef MICROCONTROLLER_DEFINED
661 #define MCS51REG_ERROR
663 #ifndef MICROCONTROLLER_DEFINED
664 #define MICROCONTROLLER_DEFINED
666 #ifndef MCS51REG_DISABLE_WARNINGS
667 #warning Selected HW: Infineon / Siemens SAB80515A
669 // 8051 register set without IP
674 #define PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
685 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
690 // SAB80515A specific registers
691 #define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
692 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
693 #define IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
703 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
720 // end of definitions for the Infineon / Siemens SAB80515A
723 // definitions for the Infineon / Siemens SAB80517
724 #ifdef MICROCONTROLLER_SAB80517
725 #ifdef MICROCONTROLLER_DEFINED
726 #define MCS51REG_ERROR
728 #ifndef MICROCONTROLLER_DEFINED
729 #define MICROCONTROLLER_DEFINED
731 #ifndef MCS51REG_DISABLE_WARNINGS
732 #warning Selected HW: Infineon / Siemens SAB80517
734 // 8051 register set without IP, SCON & SBUF
739 #define PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
750 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
755 // SAB80517 specific registers
756 #define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
757 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
758 #define IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
760 #define IEN2__SAB80517
790 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
801 #define DAPR__SAB80517
827 // end of definitions for the Infineon / Siemens SAB80517
830 /////////////////////////////////////////////////////////
831 /// don't specify microcontrollers below this line! ///
832 /////////////////////////////////////////////////////////
835 // default microcontroller -> 8051
836 // use default if no microcontroller specified
837 #ifndef MICROCONTROLLER_DEFINED
838 #define MICROCONTROLLER_DEFINED
839 #ifndef MCS51REG_DISABLE_WARNINGS
840 #warning //////////////////////////////////
841 #warning // No microcontroller defined! //
842 #warning //////////////////////////////////
843 #warning Code will be generated for the
844 #warning 8051 (default) microcontroller.
845 #warning If you have another microcontroller
846 #warning define it in the makefile, or in the
847 #warning "C" source prior
848 #warning the #include <mcs51reg.h> statement.
849 #warning If you use a non supported
850 #warning microcontroller, mcs51reg.h can be
851 #warning easily extended to support your HW.
858 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
869 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
871 #define IP___x__x__x__PS__PT1__PX1__PT0__PX0
876 // end of definitions for the default microcontroller
879 #ifdef MCS51REG_ERROR
880 #error Two or more microcontrollers defined!
883 #ifdef MCS51REG_EXTERNAL_ROM
884 #ifndef MCS51REG_UNDEFINE_P0
885 #define MCS51REG_UNDEFINE_P0
887 #ifndef MCS51REG_UNDEFINE_P2
888 #define MCS51REG_UNDEFINE_P2
892 #ifdef MCS51REG_EXTERNAL_RAM
893 #ifndef MCS51REG_UNDEFINE_P0
894 #define MCS51REG_UNDEFINE_P0
896 #ifndef MCS51REG_UNDEFINE_P2
897 #define MCS51REG_UNDEFINE_P2
901 #ifdef MCS51REG_UNDEFINE_P0
905 #ifdef MCS51REG_UNDEFINE_P2
909 ////////////////////////////////
910 /// Register definitions ///
911 /// (In alphabetical order) ///
912 ////////////////////////////////
921 sfr at 0x9D ACON ; // DS89C420 specific
930 sfr at 0xD8 ADCON ; // A/D-converter control register SAB80515 specific
941 // ADCON0 ... Infineon / Siemens also called this register ADCON in the User Manual
944 sfr at 0xD8 ADCON0 ; // A/D-converter control register 0 SAB80515A &
945 // Bit registers // SAB80517 specific
954 // Not directly accessible ADCON0
955 #define ADCON0_MX0 0x01
956 #define ADCON0_MX1 0x02
957 #define ADCON0_MX2 0x04
958 #define ADCON0_ADM 0x08
959 #define ADCON0_BSY 0x10
960 #define ADCON0_ADEX 0x20
961 #define ADCON0_CLK 0x40
962 #define ADCON0_BD 0x80
967 sfr at 0xDC ADCON1 ; // A/D-converter control register 1 SAB80515A & SAB80517 specific
968 // Not directly accessible ADCON1
969 #define ADCON1_MX0 0x01
970 #define ADCON1_MX1 0x02
971 #define ADCON1_MX2 0x04
972 #define ADCON1_ADCL 0x80
977 sfr at 0xD9 ADDAT ; // A/D-converter data register SAB80515 specific
982 sfr at 0xD9 ADDATH ; // A/D data high byte SAB80515A specific
987 sfr at 0xDA ADDATL ; // A/D data low byte SAB80515A specific
992 sfr at 0xEF ARCON ; // arithmetic control register SAB80517
999 sbit at 0xF0 BREG_F0 ;
1000 sbit at 0xF1 BREG_F1 ;
1001 sbit at 0xF2 BREG_F2 ;
1002 sbit at 0xF3 BREG_F3 ;
1003 sbit at 0xF4 BREG_F4 ;
1004 sbit at 0xF5 BREG_F5 ;
1005 sbit at 0xF6 BREG_F6 ;
1006 sbit at 0xF7 BREG_F7 ;
1012 // Not directly accessible bits
1023 sfr at 0xC9 CC4EN ; // compare/capture 4 enable register SAB80517 specific
1028 sfr at 0xC1 CCEN ; // compare/capture enable register SAB80515 specific
1033 sfr at 0xC3 CCH1 ; // compare/capture register 1, high byte SAB80515 specific
1038 sfr at 0xC5 CCH2 ; // compare/capture register 2, high byte SAB80515 specific
1043 sfr at 0xC7 CCH3 ; // compare/capture register 3, high byte SAB80515 specific
1048 sfr at 0xCF CCH4 ; // compare/capture register 4, high byte SAB80515 specific
1053 sfr at 0xC2 CCL1 ; // compare/capture register 1, low byte SAB80515 specific
1058 sfr at 0xC4 CCL2 ; // compare/capture register 2, low byte SAB80515 specific
1063 sfr at 0xC6 CCL3 ; // compare/capture register 3, low byte SAB80515 specific
1068 sfr at 0xCE CCL4 ; // compare/capture register 4, low byte SAB80515 specific
1073 sfr at 0x8E CKCON ; // DS80C320 specific
1074 // Not directly accessible Bits. DS80C320 specific
1087 sfr at 0x96 CKMOD ; // DS89C420 specific
1088 // Not directly accessible Bits.
1096 sfr at 0xF6 CMEN ; // compare enable register SAB80517 specific
1101 sfr at 0xD3 CMH0 ; // compare register 0 high byte SAB80517 specific
1106 sfr at 0xD5 CMH1 ; // compare register 1 high byte SAB80517 specific
1111 sfr at 0xD7 CMH2 ; // compare register 2 high byte SAB80517 specific
1116 sfr at 0xE3 CMH3 ; // compare register 3 high byte SAB80517 specific
1121 sfr at 0xE5 CMH4 ; // compare register 4 high byte SAB80517 specific
1126 sfr at 0xE7 CMH5 ; // compare register 5 high byte SAB80517 specific
1131 sfr at 0xF3 CMH6 ; // compare register 6 high byte SAB80517 specific
1136 sfr at 0xF5 CMH7 ; // compare register 7 high byte SAB80517 specific
1141 sfr at 0xD2 CML0 ; // compare register 0 low byte SAB80517 specific
1146 sfr at 0xD4 CML1 ; // compare register 1 low byte SAB80517 specific
1151 sfr at 0xD6 CML2 ; // compare register 2 low byte SAB80517 specific
1156 sfr at 0xE2 CML3 ; // compare register 3 low byte SAB80517 specific
1161 sfr at 0xE4 CML4 ; // compare register 4 low byte SAB80517 specific
1166 sfr at 0xE6 CML5 ; // compare register 5 low byte SAB80517 specific
1171 sfr at 0xF2 CML6 ; // compare register 6 low byte SAB80517 specific
1176 sfr at 0xF4 CML7 ; // compare register 7 low byte SAB80517 specific
1181 sfr at 0xF7 CMSEL ; // compare input select SAB80517
1186 sfr at 0xCB CRCH ; // compare/reload/capture register, high byte SAB80515 specific
1191 sfr at 0xCA CRCL ; // compare/reload/capture register, low byte SAB80515 specific
1196 sfr at 0xE1 CTCON ; // com.timer control register SAB80517
1201 sfr at 0xDF CTRELH ; // com.timer rel register high byte SAB80517
1206 sfr at 0xDE CTRELL ; // com.timer rel register low byte SAB80517
1209 #ifdef DAPR__SAB80515
1210 #undef DAPR__SAB80515
1211 sfr at 0xD8 DAPR ; // D/A-converter program register SAB80515 specific
1214 #ifdef DAPR__SAB80517
1215 #undef DAPR__SAB80517
1216 sfr at 0xDA DAPR ; // D/A-converter program register SAB80517 specific
1222 sfr at 0x83 DP0H ; // Alternate name for AT89S53
1227 sfr at 0x85 DPH1 ; // DS80C320 specific
1228 sfr at 0x85 DP1H ; // Alternate name for AT89S53
1233 sfr at 0x82 DPL ; // Alternate name for AT89S53
1239 sfr at 0x84 DPL1 ; // DS80C320 specific
1240 sfr at 0x84 DP1L ; // Alternate name for AT89S53
1243 #ifdef DPS__x__x__x__x__x__x__x__SEL
1244 #undef DPS__x__x__x__x__x__x__x__SEL
1246 // Not directly accessible DPS Bit. DS80C320 & DPS8XC520 specific
1250 #ifdef DPS__ID1__ID0__TSL__AID__x__x__x__SEL
1251 #undef DPS__ID1__ID0__TSL__AID__x__x__x__SEL
1253 // Not directly accessible DPS Bit. DS89C420 specific
1263 sfr at 0x92 DPSEL ; // data pointer select register SAB80517
1269 // Bit registers DS80C320 specific
1280 // Bit registers DS80C320 specific
1288 #ifdef EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
1289 #undef EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
1291 // Not directly accessible EXIF Bits DS80C320 specific
1301 #ifdef EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
1302 #undef EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
1304 // Not directly accessible EXIF Bits DS87C520 specific
1315 #ifdef EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
1316 #undef EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
1318 // Not directly accessible EXIF Bits DS89C420 specific
1329 #ifdef IE__EA__x__x__ES__ET1__EX1__ET0__EX0
1330 #undef IE__EA__x__x__ES__ET1__EX1__ET0__EX0
1341 #ifdef IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
1342 #undef IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
1350 sbit at 0xAD ET2 ; // Enable timer2 interrupt
1354 #ifdef IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
1355 #undef IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
1363 sbit at 0xAC ES0 ; // Alternate name
1364 sbit at 0xAD ET2 ; // Enable timer2 interrupt
1369 #ifdef IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
1370 #undef IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
1372 sfr at 0xA8 IEN0 ; // Alternate name
1373 // Bit registers for the SAB80515 and compatible IE
1380 sbit at 0xAD ET2 ; // Enable timer 2 overflow SAB80515 specific
1381 sbit at 0xAE WDT ; // watchdog timer reset - SAB80515 specific
1383 sbit at 0xAF EAL ; // EA as called by Infineon / Siemens
1388 sfr at 0xB8 IEN1 ; // interrupt enable register - SAB80515 specific
1390 sbit at 0xB8 EADC ; // A/D converter interrupt enable
1396 sbit at 0xBE SWDT ; // watchdog timer start/reset
1397 sbit at 0xBF EXEN2 ; // timer2 external reload interrupt enable
1400 #ifdef IEN2__SAB80517
1401 #undef IEN2__SAB80517
1402 sfr at 0x9A IEN2 ; // interrupt enable register 2 SAB80517
1405 #ifdef IP___x__x__x__PS__PT1__PX1__PT0__PX0
1406 #undef IP___x__x__x__PS__PT1__PX1__PT0__PX0
1416 #ifdef IP___x__x__PT2__PS__PT1__PX1__PT0__PX0
1417 #undef IP___x__x__PT2__PS__PT1__PX1__PT0__PX0
1428 #ifdef IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
1429 #undef IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
1441 #ifdef IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
1442 #undef IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
1443 sfr at 0xA9 IP0 ; // interrupt priority register SAB80515 specific
1444 // Not directly accessible IP0 bits
1454 #ifdef IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
1455 #undef IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
1456 sfr at 0xB8 IP0 ; // interrupt priority register DS89C420 specific
1457 // Not directly accessible IP0 bits
1467 #ifdef IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
1468 #undef IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
1469 sfr at 0xB9 IP1 ; // interrupt priority register SAB80515 specific
1470 // Not directly accessible IP1 bits
1479 #ifdef IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
1480 #undef IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
1481 sfr at 0xB1 IP1 ; // interrupt priority register DS89C420 specific
1482 // Not directly accessible IP0 bits
1494 sfr at 0xC0 IRCON ; // interrupt control register - SAB80515 specific
1496 sbit at 0xC0 IADC ; // A/D converter irq flag
1497 sbit at 0xC1 IEX2 ; // external interrupt edge detect flag
1502 sbit at 0xC6 TF2 ; // timer 2 owerflow flag
1503 sbit at 0xC7 EXF2 ; // timer2 reload flag
1508 sfr at 0xC0 IRCON0 ; // interrupt control register - SAB80515 specific
1510 sbit at 0xC0 IADC ; // A/D converter irq flag
1511 sbit at 0xC1 IEX2 ; // external interrupt edge detect flag
1516 sbit at 0xC6 TF2 ; // timer 2 owerflow flag
1517 sbit at 0xC7 EXF2 ; // timer2 reload flag
1522 sfr at 0xD1 IRCON1 ; // interrupt control register - SAB80515 specific
1527 sfr at 0xE9 MD0 ; // MUL / DIV register 0 SAB80517
1532 sfr at 0xEA MD1 ; // MUL / DIV register 1 SAB80517
1537 sfr at 0xEB MD2 ; // MUL / DIV register 2 SAB80517
1542 sfr at 0xEC MD3 ; // MUL / DIV register 3 SAB80517
1547 sfr at 0xED MD4 ; // MUL / DIV register 4 SAB80517
1552 sfr at 0xEE MD5 ; // MUL / DIV register 5 SAB80517
1583 #ifdef P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
1584 #undef P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
1585 // P1 alternate functions
1596 #ifdef P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
1597 sbit at 0x90 INT3_CC0 ; // P1 alternate functions - SAB80515 specific
1598 sbit at 0x91 INT4_CC1 ;
1599 sbit at 0x92 INT5_CC2 ;
1600 sbit at 0x93 INT6_CC3 ;
1603 sbit at 0x96 CLKOUT ;
1607 #ifdef P1_EXT__x__x__x__x__x__x__T2EX__T2
1608 #undef P1_EXT__x__x__x__x__x__x__T2EX__T2
1609 // P1 alternate functions
1638 #ifndef MCS51REG_EXTERNAL_RAM
1649 #ifndef MCS51REG_EXTERNAL_RAM
1657 sfr at 0xE8 P4 ; // Port 4 - SAB80515 & compatible microcontrollers
1671 sfr at 0xF8 P5 ; // Port 5 - SAB80515 & compatible microcontrollers
1685 sfr at 0xDB P6 ; // Port 6 - SAB80515 & compatible microcontrollers
1690 sfr at 0xFA P6 ; // Port 6 - SAB80517 specific
1695 sfr at 0xDB P7 ; // Port 7 - SAB80517 specific
1700 sfr at 0xDD P8 ; // Port 6 - SAB80517 specific
1703 #ifdef PCON__SMOD__x__x__x__x__x__x__x
1704 #undef PCON__SMOD__x__x__x__x__x__x__x
1706 // Not directly accessible PCON bits
1710 #ifdef PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
1711 #undef PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
1713 // Not directly accessible PCON bits
1721 #ifdef PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
1722 #undef PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
1724 // Not directly accessible PCON bits
1726 #define IDLE 0x01 ; same as IDL
1728 #define PDE 0x02 ; same as PD
1733 #define PCON_IDLE 0x01
1734 #define PCON_PDE 0x02
1735 #define PCON_GF0 0x04
1736 #define PCON_GF1 0x08
1737 #define PCON_IDLS 0x20
1738 #define PCON_PDS 0x40
1739 #define PCON_SMOD 0x80
1742 #ifdef PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
1743 #undef PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
1745 // Not directly accessible PCON bits
1747 #define IDLE 0x01 ; same as IDL
1755 #ifdef PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
1756 #undef PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
1758 // Not directly accessible PCON bits
1760 #define IDLE 0x01 ; same as IDL
1772 sfr at 0xC4 PMR ; // DS87C520, DS83C520
1773 // Not directly accessible bits
1799 sfr at 0xCB RCAP2H ;
1804 sfr at 0xCA RCAP2L ;
1807 #ifdef ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0
1808 #undef ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0
1809 sfr at 0xC2 ROMSIZE ; // DS87C520, DS83C520
1810 // Not directly accessible bits
1816 #ifdef ROMSIZE__HBPF__BPF__TE__MOVCX__PRAME__RMS2__RMS1__RMS0
1817 #undef ROMSIZE__HBPF__BPF__TE__MOVCX__PRAME__RMS2__RMS1__RMS0
1818 sfr at 0xC2 ROMSIZE ; // DS87C520, DS83C520
1819 // Not directly accessible bits
1832 sfr at 0x99 S0BUF ; // serial channel 0 buffer register SAB80517 specific
1837 sfr at 0x98 S0CON ; // serial channel 0 control register SAB80517 specific
1839 sbit at 0x98 RI0 ; // S0CON.0: receiver0 interrupt flag
1840 sbit at 0x99 TI0 ; // S0CON.1: transmitter0 interrupt flag
1841 sbit at 0x9A RB80 ; // S0CON.2: receiver0 bit8
1842 sbit at 0x9B TB80 ; // S0CON.3: transmitter0 bit 8
1843 sbit at 0x9C REN0 ; // S0CON.4: receiver0 enable
1844 sbit at 0x9D SM20 ; // S0CON.5: multiprocessor feature
1845 sbit at 0x9E SM1 ; // S0CON.6: | select serial mode
1846 sbit at 0x9F SM0 ; // S0CON.7: |
1851 sfr at 0xAA S0RELL ; // serial channel 0 reload register low byte SAB80517 specific
1856 sfr at 0xBA S0RELH ; // serial channel 0 reload register high byte SAB80517 specific
1861 sfr at 0x9C S1BUF ; // serial channel 1 buffer register SAB80517 specific
1866 sfr at 0x9B S1CON ; // serial channel 1 control register SAB80517 specific
1871 sfr at 0x9D S1RELL ; // serial channel 1 reload register low byte SAB80517 specific
1876 sfr at 0xBB S1RELH ; // serial channel 1 reload register high byte SAB80517 specific
1881 // DS80C320 specific
1882 sfr at 0xA9 SADDR0 ;
1887 // DS80C320 specific
1888 sfr at 0xAA SADDR1 ;
1893 // DS80C320 specific
1894 sfr at 0xB9 SADEN0 ;
1899 // DS80C320 specific
1900 sfr at 0xBA SADEN1 ;
1910 // DS80C320 specific
1930 // DS80C320 specific
1935 sbit at 0xCA RB8_1 ;
1936 sbit at 0xCB TB8_1 ;
1937 sbit at 0xCC REN_1 ;
1938 sbit at 0xCD SM2_1 ;
1939 sbit at 0xCE SM1_1 ;
1940 sbit at 0xCF SM0_1 ;
1942 sbit at 0xCF SM0_FE_1 ;
1952 sfr at 0xD5 SPCR ; // AT89S53 specific
1953 // Not directly accesible bits
1966 sfr at 0x86 SPDR ; // AT89S53 specific
1967 // Not directly accesible bits
1980 sfr at 0xAA SPSR ; // AT89S53 specific
1981 // Not directly accesible bits
1988 sfr at 0xBA SRELH ; // Baudrate generator reload high
1993 sfr at 0xAA SRELL ; // Baudrate generator reload low
1996 #ifdef STATUS__PIP__HIP__LIP__x__x__x__x__x
1997 #undef STATUS__PIP__HIP__LIP__x__x__x__x__x
1998 // DS80C320 specific
1999 sfr at 0xC5 STATUS ;
2000 // Not directly accessible Bits. DS80C320 specific
2006 #ifdef STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
2007 #undef STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
2008 sfr at 0xC5 STATUS ; // DS87C520 & DS83520specific
2009 // Not directly accessible Bits.
2022 sfr at 0xB1 SYSCON ; // XRAM Controller Access Control
2024 #define SYSCON_XMAP0 0x01
2025 #define SYSCON_XMAP1 0x02
2026 #define SYSCON_RMAP 0x10
2027 #define SYSCON_EALE 0x20
2030 #ifdef T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
2031 #undef T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
2033 // Definitions for the 8052 compatible microcontrollers.
2035 sbit at 0xC8 CP_RL2 ;
2038 sbit at 0xCB EXEN2 ;
2044 sbit at 0xC8 T2CON_0 ;
2045 sbit at 0xC9 T2CON_1 ;
2046 sbit at 0xCA T2CON_2 ;
2047 sbit at 0xCB T2CON_3 ;
2048 sbit at 0xCC T2CON_4 ;
2049 sbit at 0xCD T2CON_5 ;
2050 sbit at 0xCE T2CON_6 ;
2051 sbit at 0xCF T2CON_7 ;
2054 #ifdef T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
2055 #undef T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
2057 // Definitions for the Infineon / Siemens SAB80515, SAB80515A, SAB80517
2068 sbit at 0xC8 T2CON_0 ;
2069 sbit at 0xC9 T2CON_1 ;
2070 sbit at 0xCA T2CON_2 ;
2071 sbit at 0xCB T2CON_3 ;
2072 sbit at 0xCC T2CON_4 ;
2073 sbit at 0xCD T2CON_5 ;
2074 sbit at 0xCE T2CON_6 ;
2075 sbit at 0xCF T2CON_7 ;
2080 // Definitions for the timer/counter 2 of the Atmel 89x52 microcontroller
2082 // Not not directly accessible T2MOD bits
2092 // DS80C320 specific
2143 // Not directly accessible TMOD bits
2147 #define T0_GATE 0x08
2151 #define T1_GATE 0x80
2153 #define T0_MASK 0x0F
2154 #define T1_MASK 0xF0
2159 sfr at 0x96 WCON ; // AT89S53 specific
2160 // Not directly accesible bits
2171 // DS80C320 specific
2173 // Not directly accessible bits
2174 #define RWT 0x01 /* Timed-Access protected */
2175 #define EWT 0x02 /* Timed-Access protected */
2177 #define WDIF 0x08 /* Timed-Access protected */
2180 #define POR 0x40 /* Timed-Access protected */
2186 sfr at 0x86 WDTREL ; // Watchdof Timer reload register
2191 sfr at 0x91 XPAGE ; // Page Address Register for Extended On-Chip Ram - Infineon / Siemens SAB80515A specific
2195 /////////////////////////
2196 /// Interrupt vectors ///
2197 /////////////////////////
2199 // Interrupt numbers: address = (number * 8) + 3
2200 #define IE0_VECTOR 0 // 0x03 external interrupt 0
2201 #define TF0_VECTOR 1 // 0x0b timer 0
2202 #define IE1_VECTOR 2 // 0x13 external interrupt 1
2203 #define TF1_VECTOR 3 // 0x1b timer 1
2204 #define SI0_VECTOR 4 // 0x23 serial port 0
2206 #ifdef MICROCONTROLLER_AT89S53
2207 #define TF2_VECTOR 5 /* 0x2B timer 2 */
2208 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
2211 #ifdef MICROCONTROLLER_AT89X52
2212 #define TF2_VECTOR 5 /* 0x2B timer 2 */
2213 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
2216 #ifdef MICROCONTROLLER_AT89X55
2217 #define TF2_VECTOR 5 /* 0x2B timer 2 */
2218 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
2221 #ifdef MICROCONTROLLER_DS80C32X
2222 #define TF2_VECTOR 5 /* 0x2B */
2223 #define PFI_VECTOR 6 /* 0x33 */
2224 #define SIO1_VECTOR 7 /* 0x3B */
2225 #define IE2_VECTOR 8 /* 0x43 */
2226 #define IE3_VECTOR 9 /* 0x4B */
2227 #define IE4_VECTOR 10 /* 0x53 */
2228 #define IE5_VECTOR 11 /* 0x5B */
2229 #define WDI_VECTOR 12 /* 0x63 */
2232 #ifdef MICROCONTROLLER_DS8XC520
2233 #define TF2_VECTOR 5 /* 0x2B */
2234 #define PFI_VECTOR 6 /* 0x33 */
2235 #define SIO1_VECTOR 7 /* 0x3B */
2236 #define IE2_VECTOR 8 /* 0x43 */
2237 #define IE3_VECTOR 9 /* 0x4B */
2238 #define IE4_VECTOR 10 /* 0x53 */
2239 #define IE5_VECTOR 11 /* 0x5B */
2240 #define WDI_VECTOR 12 /* 0x63 */
2243 #ifdef MICROCONTROLLER_SAB80515
2244 #define TF2_VECTOR 5 // 0x2B timer 2
2245 #define EX2_VECTOR 5 // 0x2B external interrupt 2
2246 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt
2247 #define IEX2_VECTOR 9 // 0x4B external interrupt 2
2248 #define IEX3_VECTOR 10 // 0x53 external interrupt 3
2249 #define IEX4_VECTOR 11 // 0x5B external interrupt 4
2250 #define IEX5_VECTOR 12 // 0x63 external interrupt 5
2251 #define IEX6_VECTOR 13 // 0x6B external interrupt 6
2254 #ifdef MICROCONTROLLER_SAB80515A
2255 #define TF2_VECTOR 5 // 0x2B timer 2
2256 #define EX2_VECTOR 5 // 0x2B external interrupt 2
2257 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt
2258 #define IEX2_VECTOR 9 // 0x4B external interrupt 2
2259 #define IEX3_VECTOR 10 // 0x53 external interrupt 3
2260 #define IEX4_VECTOR 11 // 0x5B external interrupt 4
2261 #define IEX5_VECTOR 12 // 0x63 external interrupt 5
2262 #define IEX6_VECTOR 13 // 0x6B external interrupt 6
2265 #ifdef MICROCONTROLLER_SAB80517
2266 #define TF2_VECTOR 5 // 0x2B timer 2
2267 #define EX2_VECTOR 5 // 0x2B external interrupt 2
2268 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt
2269 #define IEX2_VECTOR 9 // 0x4B external interrupt 2
2270 #define IEX3_VECTOR 10 // 0x53 external interrupt 3
2271 #define IEX4_VECTOR 11 // 0x5B external interrupt 4
2272 #define IEX5_VECTOR 12 // 0x63 external interrupt 5
2273 #define IEX6_VECTOR 13 // 0x6B external interrupt 6
2276 #define SI1_VECTOR 16 // 0x83 serial port 1
2279 #define COMPARE_VECTOR 19 // 0x9B compare
2282 #endif // End of the header -> #ifndef MCS51REG_H