1 /*-------------------------------------------------------------------------
2 Register Declarations for the mcs51 compatible microcontrollers
4 Written By - Bela Torok / bela.torok@kssg.ch (November 2000)
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the
8 Free Software Foundation; either version 2, or (at your option) any
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 In other words, you are welcome to use, share and improve this program.
21 You are forbidden to forbid anyone else to use, share and improve
22 what you give them. Help stamp out software-hoarding!
27 Version 1.0 Nov 2, 2000 - B. Torok / bela.torok@kssg.ch
28 Initial release, supported microcontrollers:
29 8051, 8052, Atmel AT89C1051, AT89C2051, AT89C4051,
30 Infineon / Siemens SAB80515, SAB80535, SAB80515A
32 Version 1.0.1 (Nov 3, 2000)
33 SAB80515A definitions revised by Michael Schmitt / michael.schmitt@t-online.de
35 Version 1.0.2 (Nov 6, 2000)
36 T2CON bug corrected 8052 and SABX microcontrollers have different T2CONs
37 Support for the Atmel AT89C52, AT80LV52, AT89C55, AT80LV55
38 Support for the Dallas DS80C320 and DS80C323
39 B. Torok / bela.torok@kssg.ch
41 Version 1.0.3 (Nov 7, 2000)
42 SAB80517 definitions added by Michael Schmitt / michael.schmitt@t-online.de
43 Dallas AT89S53 definitions added by B. Torok / bela.torok@kssg.ch
44 Dallas DS87C520 and DS83C520 definitions added by B. Torok / bela.torok@kssg.ch
46 Version 1.0.4 (Nov 9, 2000)
47 To simplify the identication of registers, a large number of definitios
48 were renamed. Long register names now (hopefully) clearly define the
49 function of the registers.
50 Dallas DS89C420 definitions added by B. Torok / bela.torok@kssg.ch
52 Version 1.0.5 (Dec 15, 2000)
53 Definitions added: #ifdef MCS51REG_EXTERNAL_ROM
54 #ifdef MCS51REG_EXTERNAL_RAM
55 #ifdef MCS51REG_DISABLE_WARNINGS
58 Version 1.0.6 (March 10, 2001)
59 Support for the Dallas DS5000 & DS2250
60 Support for the Dallas DS5001 & DS2251
61 Support for the Dallas DS80C390
62 microcontrollers - B. Torok / bela.torok@kssg.ch
64 Adding support for additional microcontrollers:
65 -----------------------------------------------
67 1. Don't modify this file!!!
69 2. Insert your code in a separate file e.g.: mcs51reg_update.h and include
70 this after the #define HEADER_MCS51REG statement in this file
72 3. The mcs51reg_update.h file should contain following definitions:
74 a. An entry with the inventory of the register set of the
75 microcontroller in the "Describe microcontrollers" section.
77 b. If necessary add entry(s) in for registers not defined in this file
79 c. Define interrupt vectors
81 4. Send me the file mcs51reg_update.h ( bela.torok@kssg.ch ).
82 I'm going to verify/merge new definitions to this file.
85 Microcontroller support:
87 Use one of the following options:
89 1. use #include <mcs51reg.h> in your program & define MICROCONTROLLER_XXXX in your makefile.
91 2. use following definitions prior the
92 #include <mcs51reg.h> line in your program:
94 #define MICROCONTROLLER_8052 -> 8052 type microcontroller
96 #define MICROCONTROLLER_AT89CX051 -> Atmel AT89C1051, AT89C2051 and AT89C4051 microcontrollers
99 Use only one of the following definitions!!!
101 Supported Microcontrollers:
104 MICROCONTROLLER_8051 8051
105 MICROCONTROLLER_8052 8052
106 MICROCONTROLLER_AT89CX051 Atmel AT89C1051, AT89C2051 and AT89C4051
107 MICROCONTROLLER_AT89S53 Atmel AT89S53 microcontroller
108 MICROCONTROLLER_AT89X52 Atmel AT89C52 and AT80LV52 microcontrollers
109 MICROCONTROLLER_AT89X55 Atmel AT89C55 and AT80LV55 microcontrollers
110 MICROCONTROLLER_DS5000 Dallas DS5000 & DS2250 microcontroller
111 MICROCONTROLLER_DS5001 Dallas DS5001 & DS2251 microcontroller
112 MICROCONTROLLER_DS80C32X Dallas DS80C320 and DS80C323 microcontrollers
113 MICROCONTROLLER_DS80C390 Dallas DS80C390 microcontroller
114 MICROCONTROLLER_DS89C420 Dallas DS89C420 microcontroller
115 MICROCONTROLLER_DS8XC520 Dallas DS87C520 and DS83C520 microcontrollers
116 MICROCONTROLLER_SAB80515 Infineon / Siemens SAB80515 & SAB80535
117 MICROCONTROLLER_SAB80515A Infineon / Siemens SAB80515A
118 MICROCONTROLLER_SAB80517 Infineon / Siemens SAB80517
120 Additional definitions (use them prior the #include mcs51reg.h statement):
122 Ports P0 & P2 are not available for the programmer if external ROM used.
123 Use statement "#define MCS51REG_EXTERNAL_RAM" to undefine P0 & P2.
125 Ports P0, P2, P3_6, WR, P3_7 & RD are not available for the programmer if
126 external RAM is used.
127 Use statement "#define MCS51REG_EXTERNAL_RAM" to undefine P0, P2,
130 #define MCS51REG_DISABLE_WARNINGS -> disables warnings
132 -----------------------------------------------------------------------*/
135 #ifndef HEADER_MCS51REG
136 #define HEADER_MCS51REG
138 ///////////////////////////////////////////////////////
139 /// Insert header here (for developers only) ///
140 /// remove "//" from the begining of the next line ///
141 //#include "mcs51reg_update.h" ///
142 ///////////////////////////////////////////////////////
144 //////////////////////////////////
145 /// Describe microcontrollers ///
146 /// (inventory of registers) ///
147 //////////////////////////////////
149 // definitions for the 8051
150 #ifdef MICROCONTROLLER_8051
151 #ifdef MICROCONTROLLER_DEFINED
152 #define MCS51REG_ERROR
154 #ifndef MICROCONTROLLER_DEFINED
155 #define MICROCONTROLLER_DEFINED
157 #ifndef MCS51REG_DISABLE_WARNINGS
158 #warning Selected HW: 8051
164 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
175 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
177 #define IP__x__x__x__PS__PT1__PX1__PT0__PX0
182 // end of definitions for the 8051
185 // definitions for the 8052 microcontroller
186 #ifdef MICROCONTROLLER_8052
187 #ifdef MICROCONTROLLER_DEFINED
188 #define MCS51REG_ERROR
190 #ifndef MICROCONTROLLER_DEFINED
191 #define MICROCONTROLLER_DEFINED
193 #ifndef MCS51REG_DISABLE_WARNINGS
194 #warning Selected HW: 8052
201 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
212 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
214 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
218 // 8052 specific registers
219 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
225 // end of definitions for the 8052 microcontroller
228 // definitionsons for the Atmel
229 // AT89C1051, AT89C2051 and AT89C4051 microcontrollers
230 #ifdef MICROCONTROLLER_AT89CX051
231 #ifdef MICROCONTROLLER_DEFINED
232 #define MCS51REG_ERROR
234 #ifndef MICROCONTROLLER_DEFINED
235 #define MICROCONTROLLER_DEFINED
237 #ifndef MCS51REG_DISABLE_WARNINGS
238 #warning Selected HW: Atmel AT89Cx051
240 // 8051 register set without P0 & P2
244 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
254 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
256 #define IP__x__x__x__PS__PT1__PX1__PT0__PX0
261 // end of definitionsons for the Atmel
262 // AT89C1051, AT89C2051 and AT89C4051 microcontrollers
265 // definitions for the Atmel AT89S53
266 #ifdef MICROCONTROLLER_AT89S53
267 #ifdef MICROCONTROLLER_DEFINED
268 #define MCS51REG_ERROR
270 #ifndef MICROCONTROLLER_DEFINED
271 #define MICROCONTROLLER_DEFINED
273 #ifndef MCS51REG_DISABLE_WARNINGS
274 #warning Selected HW: AT89S53
281 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
292 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
294 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
298 // 8052 specific registers
299 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
304 // AT89S53 specific register
305 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
306 #define P1_EXT__x__x__x__x__x__x__T2EX__T2
314 // end of definitions for the Atmel AT89S53 microcontroller
317 // definitions for the Atmel AT89C52 and AT89LV52 microcontrollers
318 #ifdef MICROCONTROLLER_AT89X52
319 #ifdef MICROCONTROLLER_DEFINED
320 #define MCS51REG_ERROR
322 #ifndef MICROCONTROLLER_DEFINED
323 #define MICROCONTROLLER_DEFINED
325 #ifndef MCS51REG_DISABLE_WARNINGS
326 #warning Selected HW: AT89C52 or AT89LV52
333 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
344 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
346 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
350 // 8052 specific registers
351 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
356 // AT89X55 specific register
357 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
358 #define P1_EXT__x__x__x__x__x__x__T2EX__T2
360 // end of definitions for the Atmel AT89C52 and AT89LV52 microcontrollers
363 // definitions for the Atmel AT89C55 and AT89LV55 microcontrollers
364 #ifdef MICROCONTROLLER_AT89X55
365 #ifdef MICROCONTROLLER_DEFINED
366 #define MCS51REG_ERROR
368 #ifndef MICROCONTROLLER_DEFINED
369 #define MICROCONTROLLER_DEFINED
371 #ifndef MCS51REG_DISABLE_WARNINGS
372 #warning Selected HW: AT89C55 or AT89LV55
379 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
390 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
392 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
396 // 8052 specific registers
397 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
402 // AT89X55 specific register
403 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
404 #define P1_EXT__x__x__x__x__x__x__T2EX__T2
406 // end of definitions for the Atmel AT89C55 and AT89LV55 microcontrollers
409 // definitions for the Dallas DS5000
410 #ifdef MICROCONTROLLER_DS5000
411 #ifdef MICROCONTROLLER_DEFINED
412 #define MCS51REG_ERROR
414 #ifndef MICROCONTROLLER_DEFINED
415 #define MICROCONTROLLER_DEFINED
417 #ifndef MCS51REG_DISABLE_WARNINGS
418 #warning Selected HW: DS5000
424 #define PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
435 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
437 #define IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
438 #define MCON__SL__PAA__ECE2__RA32_8__PA0__PA1__PA2__PA3
444 // end of definitions for the Dallas DS5000
447 // definitions for the Dallas DS5001
448 #ifdef MICROCONTROLLER_DS5001
449 #ifdef MICROCONTROLLER_DEFINED
450 #define MCS51REG_ERROR
452 #ifndef MICROCONTROLLER_DEFINED
453 #define MICROCONTROLLER_DEFINED
455 #ifndef MCS51REG_DISABLE_WARNINGS
456 #warning Selected HW: DS5001
462 #define PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
473 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
475 #define IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
479 #define MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL
484 #define STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF
488 // end of definitions for the Dallas DS5001
491 // definitions for the Dallas DS80C320 and DS80C323 microcontrollers
492 #ifdef MICROCONTROLLER_DS80C32X
493 #ifdef MICROCONTROLLER_DEFINED
494 #define MCS51REG_ERROR
496 #ifndef MICROCONTROLLER_DEFINED
497 #define MICROCONTROLLER_DEFINED
499 #ifndef MCS51REG_DISABLE_WARNINGS
500 #warning Selected HW: Dallas DS80C320 or DS80C323
507 #define PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
519 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
521 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
525 // 8052 specific registers
526 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
531 // DS80C320 specific register
534 #define DPS__x__x__x__x__x__x__x__SEL
536 #define EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
543 #define STATUS__PIP__HIP__LIP__x__x__x__x__x
545 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
546 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
548 #define EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
549 #define EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
551 // end of definitions for the Dallas DS80C320 and DS80C323 microcontrollers
554 // definitions for the Dallas DS80C390
555 #ifdef MICROCONTROLLER_DS80C390
556 #ifdef MICROCONTROLLER_DEFINED
557 #define MCS51REG_ERROR
559 #ifndef MICROCONTROLLER_DEFINED
560 #define MICROCONTROLLER_DEFINED
562 #ifndef MCS51REG_DISABLE_WARNINGS
563 #warning Selected HW: Dallas DS80C390
570 #define PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
582 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
584 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
588 // 8052 specific registers
589 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
594 // DS80C390 specific register
598 #define DPS__ID1__ID0__TSL__x__x__x__x__SEL
600 #define EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
608 #define ACON__x__x__x__x__x__SA__AM1__AM0
639 #define PMR__CD1__CD0__SWB__CTM__4X_2X__ALEOFF__x__x
640 #define STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
641 #define MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0
643 #define T2MOD__x__x__x__D13T1__D13T2__x__T2OE__DCEN
660 #define EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2
671 #define EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
678 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
680 // end of definitions for the Dallas DS80C390
683 // definitions for the Dallas DS89C420 microcontroller
684 #ifdef MICROCONTROLLER_DS89C420
685 #ifdef MICROCONTROLLER_DEFINED
686 #define MCS51REG_ERROR
688 #ifndef MICROCONTROLLER_DEFINED
689 #define MICROCONTROLLER_DEFINED
691 #ifndef MCS51REG_DISABLE_WARNINGS
692 #warning Selected HW: Dallas DS89C420
699 #define PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
711 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
713 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
717 // 8052 specific registers
718 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
723 // DS8XC420 specific registers
724 #define ACON__PAGEE__PAGES__PAGE0__x__x__x__x__x
727 #define DPS__ID1__ID0__TSL__AID__x__x__x__SEL
730 #define IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
731 #define IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
732 #define EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
733 #define PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1_DME0
740 #define STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
743 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
744 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
746 #define ROMSIZE__HBPF__BPF__TE__MOVCX__PRAME__RMS2__RMS1__RMS0
748 #define EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
749 #define EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
751 // end of definitions for the Dallas DS89C420 microcontroller
754 // definitions for the Dallas DS87C520 and DS83C520 microcontrollers
755 #ifdef MICROCONTROLLER_DS8XC520
756 #ifdef MICROCONTROLLER_DEFINED
757 #define MCS51REG_ERROR
759 #ifndef MICROCONTROLLER_DEFINED
760 #define MICROCONTROLLER_DEFINED
762 #ifndef MCS51REG_DISABLE_WARNINGS
763 #warning Selected HW: Dallas DS87C520 or DS85C520
770 #define PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
782 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
784 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
788 // 8052 specific registers
789 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
794 // DS8XC520 specific registers
797 #define DPS__x__x__x__x__x__x__x__SEL
799 #define EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
800 #define PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1_DME0
807 #define STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
809 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
810 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
812 #define ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0
815 #define EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
816 #define EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
818 // end of definitions for the Dallas DS87C520 and DS83C520 microcontrollers
821 // definitions for the Infineon / Siemens SAB80515 & SAB80535
822 #ifdef MICROCONTROLLER_SAB80515
823 #ifdef MICROCONTROLLER_DEFINED
824 #define MCS51REG_ERROR
826 #ifndef MICROCONTROLLER_DEFINED
827 #define MICROCONTROLLER_DEFINED
829 #ifndef MCS51REG_DISABLE_WARNINGS
830 #warning Selected HW: Infineon / Siemens SAB80515 & SAB80535
832 // 8051 register set without IP
837 #define PCON__SMOD__x__x__x__x__x__x__x
848 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
853 // SAB80515 specific registers
854 #define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
855 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
865 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
872 #define DAPR__SAB80515
876 // end of definitions for the Infineon / Siemens SAB80515
879 // definitions for the Infineon / Siemens SAB80515A
880 #ifdef MICROCONTROLLER_SAB80515A
881 #ifdef MICROCONTROLLER_DEFINED
882 #define MCS51REG_ERROR
884 #ifndef MICROCONTROLLER_DEFINED
885 #define MICROCONTROLLER_DEFINED
887 #ifndef MCS51REG_DISABLE_WARNINGS
888 #warning Selected HW: Infineon / Siemens SAB80515A
890 // 8051 register set without IP
895 #define PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
906 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
911 // SAB80515A specific registers
912 #define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
913 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
914 #define IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
924 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
941 // end of definitions for the Infineon / Siemens SAB80515A
944 // definitions for the Infineon / Siemens SAB80517
945 #ifdef MICROCONTROLLER_SAB80517
946 #ifdef MICROCONTROLLER_DEFINED
947 #define MCS51REG_ERROR
949 #ifndef MICROCONTROLLER_DEFINED
950 #define MICROCONTROLLER_DEFINED
952 #ifndef MCS51REG_DISABLE_WARNINGS
953 #warning Selected HW: Infineon / Siemens SAB80517
955 // 8051 register set without IP, SCON & SBUF
960 #define PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
971 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
976 // SAB80517 specific registers
977 #define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
978 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
979 #define IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
981 #define IEN2__SAB80517
1011 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
1022 #define DAPR__SAB80517
1048 // end of definitions for the Infineon / Siemens SAB80517
1051 /////////////////////////////////////////////////////////
1052 /// don't specify microcontrollers below this line! ///
1053 /////////////////////////////////////////////////////////
1056 // default microcontroller -> 8051
1057 // use default if no microcontroller specified
1058 #ifndef MICROCONTROLLER_DEFINED
1059 #define MICROCONTROLLER_DEFINED
1060 #ifndef MCS51REG_DISABLE_WARNINGS
1061 #warning //////////////////////////////////
1062 #warning // No microcontroller defined! //
1063 #warning //////////////////////////////////
1064 #warning Code will be generated for the
1065 #warning 8051 (default) microcontroller.
1066 #warning If you have another microcontroller
1067 #warning define it in the makefile, or in the
1068 #warning "C" source prior
1069 #warning the #include <mcs51reg.h> statement.
1070 #warning If you use a non supported
1071 #warning microcontroller, mcs51reg.h can be
1072 #warning easily extended to support your HW.
1074 // 8051 register set
1079 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
1090 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
1092 #define IP__x__x__x__PS__PT1__PX1__PT0__PX0
1097 // end of definitions for the default microcontroller
1100 #ifdef MCS51REG_ERROR
1101 #error Two or more microcontrollers defined!
1104 #ifdef MCS51REG_EXTERNAL_ROM
1105 #ifndef MCS51REG_UNDEFINE_P0
1106 #define MCS51REG_UNDEFINE_P0
1108 #ifndef MCS51REG_UNDEFINE_P2
1109 #define MCS51REG_UNDEFINE_P2
1113 #ifdef MCS51REG_EXTERNAL_RAM
1114 #ifndef MCS51REG_UNDEFINE_P0
1115 #define MCS51REG_UNDEFINE_P0
1117 #ifndef MCS51REG_UNDEFINE_P2
1118 #define MCS51REG_UNDEFINE_P2
1122 #ifdef MCS51REG_UNDEFINE_P0
1126 #ifdef MCS51REG_UNDEFINE_P2
1130 ////////////////////////////////
1131 /// Register definitions ///
1132 /// (In alphabetical order) ///
1133 ////////////////////////////////
1140 #ifdef ACON__PAGEE__PAGES__PAGE0__x__x__x__x__x
1141 #undef ACON__PAGEE__PAGES__PAGE0__x__x__x__x__x
1142 sfr at 0x9D ACON ; // DS89C420 specific
1143 // Not directly accessible bits
1149 #ifdef ACON__x__x__x__x__x__SA__AM1__AM0
1150 #undef ACON__x__x__x__x__x__SA__AM1__AM0
1151 sfr at 0x9D ACON ; // DS89C390 specific
1152 // Not directly accessible bits
1160 sfr at 0xD8 ADCON ; // A/D-converter control register SAB80515 specific
1171 // ADCON0 ... Infineon / Siemens also called this register ADCON in the User Manual
1174 sfr at 0xD8 ADCON0 ; // A/D-converter control register 0 SAB80515A &
1175 // Bit registers // SAB80517 specific
1184 // Not directly accessible ADCON0
1185 #define ADCON0_MX0 0x01
1186 #define ADCON0_MX1 0x02
1187 #define ADCON0_MX2 0x04
1188 #define ADCON0_ADM 0x08
1189 #define ADCON0_BSY 0x10
1190 #define ADCON0_ADEX 0x20
1191 #define ADCON0_CLK 0x40
1192 #define ADCON0_BD 0x80
1197 sfr at 0xDC ADCON1 ; // A/D-converter control register 1 SAB80515A & SAB80517 specific
1198 // Not directly accessible ADCON1
1199 #define ADCON1_MX0 0x01
1200 #define ADCON1_MX1 0x02
1201 #define ADCON1_MX2 0x04
1202 #define ADCON1_ADCL 0x80
1207 sfr at 0xD9 ADDAT ; // A/D-converter data register SAB80515 specific
1212 sfr at 0xD9 ADDATH ; // A/D data high byte SAB80515A specific
1217 sfr at 0xDA ADDATL ; // A/D data low byte SAB80515A specific
1222 sfr at 0xEF ARCON ; // arithmetic control register SAB80517
1227 sfr at 0x9C AP ; // DS80C390
1234 sbit at 0xF0 BREG_F0 ;
1235 sbit at 0xF1 BREG_F1 ;
1236 sbit at 0xF2 BREG_F2 ;
1237 sbit at 0xF3 BREG_F3 ;
1238 sbit at 0xF4 BREG_F4 ;
1239 sbit at 0xF5 BREG_F5 ;
1240 sbit at 0xF6 BREG_F6 ;
1241 sbit at 0xF7 BREG_F7 ;
1247 // Not directly accessible bits
1258 sfr at 0xA3 C0C ; // DS80C390 specific
1259 // Not directly accessible bits
1272 sfr at 0xA5 C0IR ; // DS80C390 specific
1273 // Not directly accessible bits
1286 sfr at 0xAB C0M1C ; // DS80C390 specific
1287 // Not directly accessible bits
1289 #define ROW_TIH 0x02
1300 sfr at 0xAC C0M2C ; // DS80C390 specific
1305 sfr at 0xAD C0M3C ; // DS80C390 specific
1310 sfr at 0xAE C0M4C ; // DS80C390 specific
1315 sfr at 0xAF C0M5C ; // DS80C390 specific
1320 sfr at 0xB3 C0M6C ; // DS80C390 specific
1325 sfr at 0xB4 C0M7C ; // DS80C390 specific
1330 sfr at 0xB5 C0M8C ; // DS80C390 specific
1335 sfr at 0xB6 C0M9C ; // DS80C390 specific
1340 sfr at 0xB7 C0M10C ; // DS80C390 specific
1345 sfr at 0xBB C0M11C ; // DS80C390 specific
1350 sfr at 0xBC C0M12C ; // DS80C390 specific
1355 sfr at 0xBD C0M13C ; // DS80C390 specific
1360 sfr at 0xBE C0M14C ; // DS80C390 specific
1365 sfr at 0xBF C0M15C ; // DS80C390 specific
1370 sfr at 0xA7 C0RE ; // DS80C390 specific
1375 sfr at 0x96 C0RMS0 ; // DS80C390 specific
1380 sfr at 0x97 C0RMS1 ; // DS80C390 specific
1385 sfr at 0xA4 C0S ; // DS80C390 specific
1386 // Not directly accessible bits
1393 #define EC96_128 0x40
1399 sfr at 0xA6 C0TE ; // DS80C390 specific
1404 sfr at 0x9E C0TMA0 ; // DS80C390 specific
1409 sfr at 0x9F C0TMA1 ; // DS80C390 specific
1414 sfr at 0xE3 C1C ; // DS80C390 specific
1415 // Not directly accessible bits
1428 sfr at 0xE5 C1IR ; // DS80C390 specific
1429 // Not directly accessible bits
1442 sfr at 0xE7 C1RE ; // DS80C390 specific
1447 sfr at 0xEB C1M1C ; // DS80C390 specific
1452 sfr at 0xEC C1M2C ; // DS80C390 specific
1457 sfr at 0xED C1M3C ; // DS80C390 specific
1462 sfr at 0xEE C1M4C ; // DS80C390 specific
1467 sfr at 0xEF C1M5C ; // DS80C390 specific
1472 sfr at 0xF3 C1M6C ; // DS80C390 specific
1477 sfr at 0xF4 C1M7C ; // DS80C390 specific
1482 sfr at 0xF5 C1M8C ; // DS80C390 specific
1487 sfr at 0xF6 C1M9C ; // DS80C390 specific
1492 sfr at 0xF7 C1M10C ; // DS80C390 specific
1497 sfr at 0xFB C1M11C ; // DS80C390 specific
1502 sfr at 0xFC C1M12C ; // DS80C390 specific
1507 sfr at 0xFD C1M13C ; // DS80C390 specific
1512 sfr at 0xFE C1M14C ; // DS80C390 specific
1517 sfr at 0xFF C1M15C ; // DS80C390 specific
1522 sfr at 0xE4 C1S ; // DS80C390 specific
1523 // Not directly accessible bits
1536 sfr at 0xE6 C1TE ; // DS80C390 specific
1541 sfr at 0xD6 C1RSM0 ; // DS80C390 specific
1546 sfr at 0xD7 C1RSM1 ; // DS80C390 specific
1551 sfr at 0xDE C1TMA0 ; // DS80C390 specific
1556 sfr at 0xDF C1TMA1 ; // DS80C390 specific
1561 sfr at 0xC9 CC4EN ; // compare/capture 4 enable register SAB80517 specific
1566 sfr at 0xC1 CCEN ; // compare/capture enable register SAB80515 specific
1571 sfr at 0xC3 CCH1 ; // compare/capture register 1, high byte SAB80515 specific
1576 sfr at 0xC5 CCH2 ; // compare/capture register 2, high byte SAB80515 specific
1581 sfr at 0xC7 CCH3 ; // compare/capture register 3, high byte SAB80515 specific
1586 sfr at 0xCF CCH4 ; // compare/capture register 4, high byte SAB80515 specific
1591 sfr at 0xC2 CCL1 ; // compare/capture register 1, low byte SAB80515 specific
1596 sfr at 0xC4 CCL2 ; // compare/capture register 2, low byte SAB80515 specific
1601 sfr at 0xC6 CCL3 ; // compare/capture register 3, low byte SAB80515 specific
1606 sfr at 0xCE CCL4 ; // compare/capture register 4, low byte SAB80515 specific
1611 sfr at 0x8E CKCON ; // DS80C320 & DS80C390 specific
1612 // Not directly accessible Bits.
1625 sfr at 0x96 CKMOD ; // DS89C420 specific
1626 // Not directly accessible Bits.
1634 sfr at 0xF6 CMEN ; // compare enable register SAB80517 specific
1639 sfr at 0xD3 CMH0 ; // compare register 0 high byte SAB80517 specific
1644 sfr at 0xD5 CMH1 ; // compare register 1 high byte SAB80517 specific
1649 sfr at 0xD7 CMH2 ; // compare register 2 high byte SAB80517 specific
1654 sfr at 0xE3 CMH3 ; // compare register 3 high byte SAB80517 specific
1659 sfr at 0xE5 CMH4 ; // compare register 4 high byte SAB80517 specific
1664 sfr at 0xE7 CMH5 ; // compare register 5 high byte SAB80517 specific
1669 sfr at 0xF3 CMH6 ; // compare register 6 high byte SAB80517 specific
1674 sfr at 0xF5 CMH7 ; // compare register 7 high byte SAB80517 specific
1679 sfr at 0xD2 CML0 ; // compare register 0 low byte SAB80517 specific
1684 sfr at 0xD4 CML1 ; // compare register 1 low byte SAB80517 specific
1689 sfr at 0xD6 CML2 ; // compare register 2 low byte SAB80517 specific
1694 sfr at 0xE2 CML3 ; // compare register 3 low byte SAB80517 specific
1699 sfr at 0xE4 CML4 ; // compare register 4 low byte SAB80517 specific
1704 sfr at 0xE6 CML5 ; // compare register 5 low byte SAB80517 specific
1709 sfr at 0xF2 CML6 ; // compare register 6 low byte SAB80517 specific
1714 sfr at 0xF4 CML7 ; // compare register 7 low byte SAB80517 specific
1719 sfr at 0xF7 CMSEL ; // compare input select SAB80517
1724 sfr at 0xCE COR ; // Dallas DS80C390 specific
1737 sfr at 0xC1 CRC ; // Dallas DS5001 specific
1748 sfr at 0xCB CRCH ; // compare/reload/capture register, high byte SAB80515 specific
1753 sfr at 0xC3 CRCHIGH ; // DS5001 specific
1758 sfr at 0xCA CRCL ; // compare/reload/capture register, low byte SAB80515 specific
1763 sfr at 0xC2 CRCLOW ; // DS5001 specific
1768 sfr at 0xE1 CTCON ; // com.timer control register SAB80517
1773 sfr at 0xDF CTRELH ; // com.timer rel register high byte SAB80517
1778 sfr at 0xDE CTRELL ; // com.timer rel register low byte SAB80517
1781 #ifdef DAPR__SAB80515
1782 #undef DAPR__SAB80515
1783 sfr at 0xD8 DAPR ; // D/A-converter program register SAB80515 specific
1786 #ifdef DAPR__SAB80517
1787 #undef DAPR__SAB80517
1788 sfr at 0xDA DAPR ; // D/A-converter program register SAB80517 specific
1794 sfr at 0x83 DP0H ; // Alternate name for AT89S53
1799 sfr at 0x85 DPH1 ; // DS80C320 specific
1800 sfr at 0x85 DP1H ; // Alternate name for AT89S53
1805 sfr at 0x82 DPL ; // Alternate name for AT89S53
1811 sfr at 0x84 DPL1 ; // DS80C320 specific
1812 sfr at 0x84 DP1L ; // Alternate name for AT89S53
1815 #ifdef DPS__x__x__x__x__x__x__x__SEL
1816 #undef DPS__x__x__x__x__x__x__x__SEL
1818 // Not directly accessible DPS Bit. DS80C320 & DPS8XC520 specific
1822 #ifdef DPS__ID1__ID0__TSL__x__x__x__x__SEL
1823 #undef DPS__ID1__ID0__TSL__x__x__x__x__SEL
1825 // Not directly accessible DPS Bit. DS89C390 specific
1832 #ifdef DPS__ID1__ID0__TSL__AID__x__x__x__SEL
1833 #undef DPS__ID1__ID0__TSL__AID__x__x__x__SEL
1835 // Not directly accessible DPS Bit. DS89C420 specific
1845 sfr at 0x92 DPSEL ; // data pointer select register SAB80517
1850 sfr at 0x93 DPX1 ; // DS80C390 specific
1855 sfr at 0x95 DPX1 ; // DS80C390 specific
1858 #ifdef EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
1859 #undef EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
1861 // Bit registers DS80C320 specific
1869 #ifdef EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2
1870 #undef EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2
1872 // Bit registers DS80C390 specific
1880 sbit at 0xEF CANBIE ;
1883 #ifdef EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
1884 #undef EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
1886 // Bit registers DS80C320 specific
1894 #ifdef EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
1895 #undef EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
1897 // Bit registers DS80C320 specific
1905 sbit at 0xFF CANBIP ;
1911 // Not directly accessible Bits DS80C390 specific
1916 #ifdef EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
1917 #undef EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
1919 // Not directly accessible EXIF Bits DS80C320 specific
1929 #ifdef EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
1930 #undef EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
1932 // Not directly accessible EXIF Bits DS87C520 specific
1943 #ifdef EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
1944 #undef EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
1946 // Not directly accessible EXIF Bits DS80C390 & DS89C420 specific
1957 #ifdef IE__EA__x__x__ES__ET1__EX1__ET0__EX0
1958 #undef IE__EA__x__x__ES__ET1__EX1__ET0__EX0
1969 #ifdef IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
1970 #undef IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
1978 sbit at 0xAD ET2 ; // Enable timer2 interrupt
1982 #ifdef IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
1983 #undef IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
1991 sbit at 0xAC ES0 ; // Alternate name
1992 sbit at 0xAD ET2 ; // Enable timer2 interrupt
1997 #ifdef IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
1998 #undef IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
2000 sfr at 0xA8 IEN0 ; // Alternate name
2001 // Bit registers for the SAB80515 and compatible IE
2008 sbit at 0xAD ET2 ; // Enable timer 2 overflow SAB80515 specific
2009 sbit at 0xAE WDT ; // watchdog timer reset - SAB80515 specific
2011 sbit at 0xAF EAL ; // EA as called by Infineon / Siemens
2016 sfr at 0xB8 IEN1 ; // interrupt enable register - SAB80515 specific
2018 sbit at 0xB8 EADC ; // A/D converter interrupt enable
2024 sbit at 0xBE SWDT ; // watchdog timer start/reset
2025 sbit at 0xBF EXEN2 ; // timer2 external reload interrupt enable
2028 #ifdef IEN2__SAB80517
2029 #undef IEN2__SAB80517
2030 sfr at 0x9A IEN2 ; // interrupt enable register 2 SAB80517
2033 #ifdef IP__x__x__x__PS__PT1__PX1__PT0__PX0
2034 #undef IP__x__x__x__PS__PT1__PX1__PT0__PX0
2044 #ifdef IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
2045 #undef IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
2053 sbit at 0xBC PS0 ; // alternate name
2057 #ifdef IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
2058 #undef IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
2070 #ifdef IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
2071 #undef IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
2082 #ifdef IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
2083 #undef IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
2084 sfr at 0xA9 IP0 ; // interrupt priority register SAB80515 specific
2085 // Not directly accessible IP0 bits
2095 #ifdef IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
2096 #undef IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
2097 sfr at 0xB8 IP0 ; // interrupt priority register DS89C420 specific
2098 // Not directly accessible IP0 bits
2108 #ifdef IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
2109 #undef IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
2110 sfr at 0xB9 IP1 ; // interrupt priority register SAB80515 specific
2111 // Not directly accessible IP1 bits
2120 #ifdef IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
2121 #undef IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
2122 sfr at 0xB1 IP1 ; // interrupt priority register DS89C420 specific
2123 // Not directly accessible IP0 bits
2135 sfr at 0xC0 IRCON ; // interrupt control register - SAB80515 specific
2137 sbit at 0xC0 IADC ; // A/D converter irq flag
2138 sbit at 0xC1 IEX2 ; // external interrupt edge detect flag
2143 sbit at 0xC6 TF2 ; // timer 2 owerflow flag
2144 sbit at 0xC7 EXF2 ; // timer2 reload flag
2149 sfr at 0xC0 IRCON0 ; // interrupt control register - SAB80515 specific
2151 sbit at 0xC0 IADC ; // A/D converter irq flag
2152 sbit at 0xC1 IEX2 ; // external interrupt edge detect flag
2157 sbit at 0xC6 TF2 ; // timer 2 owerflow flag
2158 sbit at 0xC7 EXF2 ; // timer2 reload flag
2163 sfr at 0xD1 IRCON1 ; // interrupt control register - SAB80515 specific
2168 sfr at 0xD3 MA ; // DS80C390
2173 sfr at 0xD4 MB ; // DS80C390
2178 sfr at 0xD5 MC ; // DS80C390
2183 sfr at 0xD1 MCNT0 ; // DS80C390
2196 sfr at 0xD2 MCNT1 ; // DS80C390
2202 #ifdef MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0
2203 #undef MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0
2204 sfr at 0xC6 MCON ; // DS80C390
2214 #ifdef MCON__PA3__PA2__PA1__PA0__RA32_8__ECE2__PAA__SL
2215 #undef MCON__PA3__PA2__PA1__PA0__RA32_8__ECE2__PAA__SL
2216 sfr at 0xC6 MCON ; // DS5000
2227 #ifdef MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL
2228 #undef MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL
2229 sfr at 0xC6 MCON ; // DS5001
2242 sfr at 0xE9 MD0 ; // MUL / DIV register 0 SAB80517
2247 sfr at 0xEA MD1 ; // MUL / DIV register 1 SAB80517
2252 sfr at 0xEB MD2 ; // MUL / DIV register 2 SAB80517
2257 sfr at 0xEC MD3 ; // MUL / DIV register 3 SAB80517
2262 sfr at 0xED MD4 ; // MUL / DIV register 4 SAB80517
2267 sfr at 0xEE MD5 ; // MUL / DIV register 5 SAB80517
2272 sfr at 0xEA MXAX ; // Dallas DS80C390
2303 #ifdef P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
2304 #undef P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
2305 // P1 alternate functions
2316 #ifdef P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
2317 sbit at 0x90 INT3_CC0 ; // P1 alternate functions - SAB80515 specific
2318 sbit at 0x91 INT4_CC1 ;
2319 sbit at 0x92 INT5_CC2 ;
2320 sbit at 0x93 INT6_CC3 ;
2323 sbit at 0x96 CLKOUT ;
2327 #ifdef P1_EXT__x__x__x__x__x__x__T2EX__T2
2328 #undef P1_EXT__x__x__x__x__x__x__T2EX__T2
2329 // P1 alternate functions
2358 #ifndef MCS51REG_EXTERNAL_RAM
2371 #ifndef MCS51REG_EXTERNAL_RAM
2379 sfr at 0x80 P4 ; // Port 4 - DS80C390
2393 sfr at 0xE8 P4 ; // Port 4 - SAB80515 & compatible microcontrollers
2407 sfr at 0x92 P4CNT ; // DS80C390
2408 // Not directly accessible bits
2409 #define P4CNT_0 0x01
2410 #define P4CNT_1 0x02
2411 #define P4CNT_2 0x04
2412 #define P4CNT_3 0x08
2413 #define P4CNT_4 0x10
2414 #define P4CNT_5 0x20
2420 sfr at 0xA1 P5 ; // Port 5 - DS80C390
2425 sfr at 0xA2 P5CNT ; // DS80C390
2426 // Not directly accessible bits
2427 #define P5CNT_0 0x01
2428 #define P5CNT_1 0x02
2429 #define P5CNT_2 0x04
2433 #define SBCAN0BA 0x40
2434 #define SBCAN1BA 0x80
2439 sfr at 0xF8 P5 ; // Port 5 - SAB80515 & compatible microcontrollers
2453 sfr at 0xDB P6 ; // Port 6 - SAB80515 & compatible microcontrollers
2458 sfr at 0xFA P6 ; // Port 6 - SAB80517 specific
2463 sfr at 0xDB P7 ; // Port 7 - SAB80517 specific
2468 sfr at 0xDD P8 ; // Port 6 - SAB80517 specific
2471 #ifdef PCON__SMOD__x__x__x__x__x__x__x
2472 #undef PCON__SMOD__x__x__x__x__x__x__x
2474 // Not directly accessible PCON bits
2478 #ifdef PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
2479 #undef PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
2481 // Not directly accessible PCON bits
2489 #ifdef PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
2490 #undef PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
2492 // Not directly accessible PCON bits
2494 #define IDLE 0x01 ; same as IDL
2496 #define PDE 0x02 ; same as PD
2501 #define PCON_IDLE 0x01
2502 #define PCON_PDE 0x02
2503 #define PCON_GF0 0x04
2504 #define PCON_GF1 0x08
2505 #define PCON_IDLS 0x20
2506 #define PCON_PDS 0x40
2507 #define PCON_SMOD 0x80
2510 #ifdef PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
2511 #undef PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
2513 // Not directly accessible PCON bits
2515 #define IDLE 0x01 ; same as IDL
2525 #ifdef PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
2526 #undef PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
2528 // Not directly accessible PCON bits
2530 #define IDLE 0x01 ; same as IDL
2538 #ifdef PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
2539 #undef PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
2541 // Not directly accessible PCON bits
2543 #define IDLE 0x01 ; same as IDL
2551 #define SMOD_0 0x80 ; same as SMOD
2554 #ifdef PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1_DME0
2555 #undef PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1_DME0
2556 sfr at 0xC4 PMR ; // DS87C520, DS83C520
2557 // Not directly accessible bits
2567 #ifdef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEOFF__x__x
2568 #undef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEOFF__x__x
2569 sfr at 0xC4 PMR ; // DS80C390
2570 // Not directly accessible bits
2595 sfr at 0xCB RCAP2H ;
2600 sfr at 0xCA RCAP2L ;
2608 #ifdef ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0
2609 #undef ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0
2610 sfr at 0xC2 ROMSIZE ; // DS87C520, DS83C520
2611 // Not directly accessible bits
2617 #ifdef ROMSIZE__HBPF__BPF__TE__MOVCX__PRAME__RMS2__RMS1__RMS0
2618 #undef ROMSIZE__HBPF__BPF__TE__MOVCX__PRAME__RMS2__RMS1__RMS0
2619 sfr at 0xC2 ROMSIZE ; // DS87C520, DS83C520
2620 // Not directly accessible bits
2633 sfr at 0xD8 RPCTL ; // Dallas DS5001 specific
2635 sbit at 0xD9 RPCON ;
2640 sbit at 0xDF RNR_FLAG ;
2645 sfr at 0x99 S0BUF ; // serial channel 0 buffer register SAB80517 specific
2650 sfr at 0x98 S0CON ; // serial channel 0 control register SAB80517 specific
2652 sbit at 0x98 RI0 ; // S0CON.0: receiver0 interrupt flag
2653 sbit at 0x99 TI0 ; // S0CON.1: transmitter0 interrupt flag
2654 sbit at 0x9A RB80 ; // S0CON.2: receiver0 bit8
2655 sbit at 0x9B TB80 ; // S0CON.3: transmitter0 bit 8
2656 sbit at 0x9C REN0 ; // S0CON.4: receiver0 enable
2657 sbit at 0x9D SM20 ; // S0CON.5: multiprocessor feature
2658 sbit at 0x9E SM1 ; // S0CON.6: | select serial mode
2659 sbit at 0x9F SM0 ; // S0CON.7: |
2664 sfr at 0xAA S0RELL ; // serial channel 0 reload register low byte SAB80517 specific
2669 sfr at 0xBA S0RELH ; // serial channel 0 reload register high byte SAB80517 specific
2674 sfr at 0x9C S1BUF ; // serial channel 1 buffer register SAB80517 specific
2679 sfr at 0x9B S1CON ; // serial channel 1 control register SAB80517 specific
2684 sfr at 0x9D S1RELL ; // serial channel 1 reload register low byte SAB80517 specific
2689 sfr at 0xBB S1RELH ; // serial channel 1 reload register high byte SAB80517 specific
2694 // DS80C320 specific
2695 sfr at 0xA9 SADDR0 ;
2700 // DS80C320 specific
2701 sfr at 0xAA SADDR1 ;
2706 // DS80C320 & DS80C390 specific
2707 sfr at 0xB9 SADEN0 ;
2712 // DS80C320 & DS80C390 specific
2713 sfr at 0xBA SADEN1 ;
2724 // DS80C320 & DS80C390 specific
2748 sbit at 0x9A RB8_0 ;
2749 sbit at 0x9B TB8_0 ;
2750 sbit at 0x9C REN_0 ;
2751 sbit at 0x9D SM2_0 ;
2752 sbit at 0x9E SM1_0 ;
2753 sbit at 0x9F SM0_0 ;
2755 sbit at 0x9F SM0_FE_0 ;
2760 // DS80C320 - 80C390 specific
2765 sbit at 0xC2 RB8_1 ;
2766 sbit at 0xC3 TB8_1 ;
2767 sbit at 0xC4 REN_1 ;
2768 sbit at 0xC5 SM2_1 ;
2769 sbit at 0xC6 SM1_1 ;
2770 sbit at 0xC7 SM0_1 ;
2772 sbit at 0xC7 SM0_FE_1 ;
2782 sfr at 0xD5 SPCR ; // AT89S53 specific
2783 // Not directly accesible bits
2796 sfr at 0x86 SPDR ; // AT89S53 specific
2797 // Not directly accesible bits
2810 sfr at 0xAA SPSR ; // AT89S53 specific
2811 // Not directly accesible bits
2818 sfr at 0xBA SRELH ; // Baudrate generator reload high
2823 sfr at 0xAA SRELL ; // Baudrate generator reload low
2826 #ifdef STATUS__PIP__HIP__LIP__x__x__x__x__x
2827 #undef STATUS__PIP__HIP__LIP__x__x__x__x__x
2828 // DS80C320 specific
2829 sfr at 0xC5 STATUS ;
2830 // Not directly accessible Bits. DS80C320 specific
2836 #ifdef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
2837 #undef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
2838 sfr at 0xC5 STATUS ; // DS80C390 specific
2839 // Not directly accessible Bits.
2849 #ifdef STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
2850 #undef STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
2851 sfr at 0xC5 STATUS ; // DS87C520 & DS83520specific
2852 // Not directly accessible Bits.
2863 #ifdef STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF
2864 #undef STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF
2865 sfr at 0xDA STATUS ; // DS5001specific
2866 // Not directly accessible Bits.
2879 sfr at 0xB1 SYSCON ; // XRAM Controller Access Control
2881 #define SYSCON_XMAP0 0x01
2882 #define SYSCON_XMAP1 0x02
2883 #define SYSCON_RMAP 0x10
2884 #define SYSCON_EALE 0x20
2887 #ifdef T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
2888 #undef T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
2890 // Definitions for the 8052 compatible microcontrollers.
2892 sbit at 0xC8 CP_RL2 ;
2895 sbit at 0xCB EXEN2 ;
2901 sbit at 0xC8 T2CON_0 ;
2902 sbit at 0xC9 T2CON_1 ;
2903 sbit at 0xCA T2CON_2 ;
2904 sbit at 0xCB T2CON_3 ;
2905 sbit at 0xCC T2CON_4 ;
2906 sbit at 0xCD T2CON_5 ;
2907 sbit at 0xCE T2CON_6 ;
2908 sbit at 0xCF T2CON_7 ;
2911 #ifdef T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
2912 #undef T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
2914 // Definitions for the Infineon / Siemens SAB80515, SAB80515A, SAB80517
2925 sbit at 0xC8 T2CON_0 ;
2926 sbit at 0xC9 T2CON_1 ;
2927 sbit at 0xCA T2CON_2 ;
2928 sbit at 0xCB T2CON_3 ;
2929 sbit at 0xCC T2CON_4 ;
2930 sbit at 0xCD T2CON_5 ;
2931 sbit at 0xCE T2CON_6 ;
2932 sbit at 0xCF T2CON_7 ;
2935 #ifdef T2MOD__x__x__x__D13T1__D13T2__x__T2OE__DCEN
2936 #undef T2MOD__x__x__x__D13T1__D13T2__x__T2OE__DCEN
2937 // Definitions for the timer/counter 2 of the Atmel & Dallas microcontrollers
2939 // Not not directly accessible T2MOD bits
2946 #ifdef T2MOD__x__x__x__x__x__x__T2OE__DCEN
2947 #undef T2MOD__x__x__x__x__x__x__T2OE__DCEN
2948 // Definitions for the timer/counter 2 of the Atmel 89x52 microcontroller
2950 // Not not directly accessible T2MOD bits
2960 // DS500x, DS80C320 & DS80C390 specific
3011 // Not directly accessible TMOD bits
3015 #define T0_GATE 0x08
3019 #define T1_GATE 0x80
3021 #define T0_MASK 0x0F
3022 #define T1_MASK 0xF0
3027 sfr at 0x96 WCON ; // AT89S53 specific
3028 // Not directly accesible bits
3039 // DS80C320 - 390 specific
3049 sbit at 0xDF SMOD_1 ;
3054 sfr at 0x86 WDTREL ; // Watchdof Timer reload register
3059 sfr at 0x91 XPAGE ; // Page Address Register for Extended On-Chip Ram - Infineon / Siemens SAB80515A specific
3063 /////////////////////////
3064 /// Interrupt vectors ///
3065 /////////////////////////
3067 // Interrupt numbers: address = (number * 8) + 3
3068 #define IE0_VECTOR 0 // 0x03 external interrupt 0
3069 #define TF0_VECTOR 1 // 0x0b timer 0
3070 #define IE1_VECTOR 2 // 0x13 external interrupt 1
3071 #define TF1_VECTOR 3 // 0x1b timer 1
3072 #define SI0_VECTOR 4 // 0x23 serial port 0
3074 #ifdef MICROCONTROLLER_AT89S53
3075 #define TF2_VECTOR 5 /* 0x2B timer 2 */
3076 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
3079 #ifdef MICROCONTROLLER_AT89X52
3080 #define TF2_VECTOR 5 /* 0x2B timer 2 */
3081 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
3084 #ifdef MICROCONTROLLER_AT89X55
3085 #define TF2_VECTOR 5 /* 0x2B timer 2 */
3086 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
3089 #ifdef MICROCONTROLLER_DS5000
3090 #define PFW_VECTOR 5 /* 0x2B */
3093 #ifdef MICROCONTROLLER_DS5001
3094 #define PFW_VECTOR 5 /* 0x2B */
3097 #ifdef MICROCONTROLLER_DS80C32X
3098 #define TF2_VECTOR 5 /* 0x2B */
3099 #define PFI_VECTOR 6 /* 0x33 */
3100 #define SIO1_VECTOR 7 /* 0x3B */
3101 #define IE2_VECTOR 8 /* 0x43 */
3102 #define IE3_VECTOR 9 /* 0x4B */
3103 #define IE4_VECTOR 10 /* 0x53 */
3104 #define IE5_VECTOR 11 /* 0x5B */
3105 #define WDI_VECTOR 12 /* 0x63 */
3108 #ifdef MICROCONTROLLER_DS8XC520
3109 #define TF2_VECTOR 5 /* 0x2B */
3110 #define PFI_VECTOR 6 /* 0x33 */
3111 #define SIO1_VECTOR 7 /* 0x3B */
3112 #define IE2_VECTOR 8 /* 0x43 */
3113 #define IE3_VECTOR 9 /* 0x4B */
3114 #define IE4_VECTOR 10 /* 0x53 */
3115 #define IE5_VECTOR 11 /* 0x5B */
3116 #define WDI_VECTOR 12 /* 0x63 */
3119 #ifdef MICROCONTROLLER_SAB80515
3120 #define TF2_VECTOR 5 // 0x2B timer 2
3121 #define EX2_VECTOR 5 // 0x2B external interrupt 2
3122 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt
3123 #define IEX2_VECTOR 9 // 0x4B external interrupt 2
3124 #define IEX3_VECTOR 10 // 0x53 external interrupt 3
3125 #define IEX4_VECTOR 11 // 0x5B external interrupt 4
3126 #define IEX5_VECTOR 12 // 0x63 external interrupt 5
3127 #define IEX6_VECTOR 13 // 0x6B external interrupt 6
3130 #ifdef MICROCONTROLLER_SAB80515A
3131 #define TF2_VECTOR 5 // 0x2B timer 2
3132 #define EX2_VECTOR 5 // 0x2B external interrupt 2
3133 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt
3134 #define IEX2_VECTOR 9 // 0x4B external interrupt 2
3135 #define IEX3_VECTOR 10 // 0x53 external interrupt 3
3136 #define IEX4_VECTOR 11 // 0x5B external interrupt 4
3137 #define IEX5_VECTOR 12 // 0x63 external interrupt 5
3138 #define IEX6_VECTOR 13 // 0x6B external interrupt 6
3141 #ifdef MICROCONTROLLER_SAB80517
3142 #define TF2_VECTOR 5 // 0x2B timer 2
3143 #define EX2_VECTOR 5 // 0x2B external interrupt 2
3144 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt
3145 #define IEX2_VECTOR 9 // 0x4B external interrupt 2
3146 #define IEX3_VECTOR 10 // 0x53 external interrupt 3
3147 #define IEX4_VECTOR 11 // 0x5B external interrupt 4
3148 #define IEX5_VECTOR 12 // 0x63 external interrupt 5
3149 #define IEX6_VECTOR 13 // 0x6B external interrupt 6
3152 #define SI1_VECTOR 16 // 0x83 serial port 1
3155 #define COMPARE_VECTOR 19 // 0x9B compare
3158 #endif // End of the header -> #ifndef MCS51REG_H