1 /*-------------------------------------------------------------------------
2 Register Declarations for the mcs51 compatible microcontrollers
4 Written By - Bela Torok / bela.torok@kssg.ch (November 2000)
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the
8 Free Software Foundation; either version 2, or (at your option) any
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 In other words, you are welcome to use, share and improve this program.
21 You are forbidden to forbid anyone else to use, share and improve
22 what you give them. Help stamp out software-hoarding!
27 Version 1.0 Nov 2, 2000 - B. Torok / bela.torok@kssg.ch
28 Initial release, supported microcontrollers:
29 8051, 8052, Atmel AT89C1051, AT89C2051, AT89C4051,
30 Infineon / Siemens SAB80515, SAB80535, SAB80515A
32 Version 1.0.1 (Nov 3, 2000)
33 SAB80515A definitions revised by Michael Schmitt / michael.schmitt@t-online.de
35 Version 1.0.2 (Nov 6, 2000)
36 T2CON bug corrected 8052 and SABX microcontrollers have different T2CONs
37 Support for the Atmel AT89C52, AT80LV52, AT89C55, AT80LV55
38 Support for the Dallas DS80C320 and DS80C323
39 B. Torok / bela.torok@kssg.ch
41 Version 1.0.3 (Nov 7, 2000)
42 SAB80517 definitions added by Michael Schmitt / michael.schmitt@t-online.de
43 Dallas AT89S53 definitions added by B. Torok / bela.torok@kssg.ch
44 Dallas DS87C520 and DS83C520 definitions added by B. Torok / bela.torok@kssg.ch
46 Version 1.0.4 (Nov 9, 2000)
47 To simplify the identication of registers, a large number of definitios
48 were renamed. Long register names now (hopefully) clearly define the
49 function of the registers.
50 Dallas DS89C420 definitions added by B. Torok / bela.torok@kssg.ch
52 Version 1.0.5 (Dec 15, 2000)
53 Definitions added: #ifdef MCS51REG_EXTERNAL_ROM
54 #ifdef MCS51REG_EXTERNAL_RAM
55 #ifndef MCS51REG_DISABLE_WARNINGS
58 Version 1.0.6 (March 10, 2001)
59 Support for the Dallas DS5000 & DS2250
60 Support for the Dallas DS5001 & DS2251
61 Support for the Dallas DS80C390
62 microcontrollers - B. Torok / bela.torok@kssg.ch
64 Version 1.0.7 (June 7, 2001)
65 #ifndef MCS51REG_DISABLE_WARNINGS removed
66 #ifdef MCS51REG_DISABLE_WARNINGS added - B. Torok / bela.torok@kssg.ch
67 Support for the Philips P80C552 added - Bernhard Held / Bernhard.Held@otelo-online.de
69 Version 1.0.8 (Feb 28, 2002)
70 Dallas DS89C420 definitions corrected by B. Torok / bela.torok@kssg.ch
71 Revised by lanius@ewetel.net
73 Version 1.0.9 (Sept 9, 2002)
74 Register declarations for the Atmel T89C51RD2 added by Johannes Hoelzl / johannes.hoelzl@gmx.de
76 Version 1.0.10 (Sept 19, 2002)
77 Register declarations for the Philips P89C668 added by Eric Limpens / Eric@limpens.net
79 Adding support for additional microcontrollers:
80 -----------------------------------------------
82 1. Don't modify this file!!!
84 2. Insert your code in a separate file e.g.: mcs51reg_update.h and include
85 this after the #define HEADER_MCS51REG statement in this file
87 3. The mcs51reg_update.h file should contain following definitions:
89 a. An entry with the inventory of the register set of the
90 microcontroller in the "Describe microcontrollers" section.
92 b. If necessary add entry(s) for registers not defined in this file
94 c. Define interrupt vectors
96 4. Compile a program for the microcontroller using the Preprocessor only, e.g.:,
97 sdcc -E test.c > t.txt
98 and check definitions for validity in the t.txt file.
100 5. If everithing seems to be OK send me the mcs51reg_update.h file. --> bela.torok@kssg.ch
101 I'm going to resolve conflicts & verify/merge new definitions to this file.
104 Microcontroller support:
106 Use one of the following options:
108 1. use #include <mcs51reg.h> in your program & define MICROCONTROLLER_XXXX in your makefile.
110 2. use following definitions prior the
111 #include <mcs51reg.h> line in your program:
113 #define MICROCONTROLLER_8052 -> 8052 type microcontroller
115 #define MICROCONTROLLER_AT89CX051 -> Atmel AT89C1051, AT89C2051 and AT89C4051 microcontrollers
118 Use only one of the following definitions!!!
120 Supported Microcontrollers:
123 MICROCONTROLLER_8051 8051
124 MICROCONTROLLER_8052 8052
125 MICROCONTROLLER_AT89CX051 Atmel AT89C1051, AT89C2051 and AT89C4051
126 MICROCONTROLLER_AT89S53 Atmel AT89S53 microcontroller
127 MICROCONTROLLER_AT89X52 Atmel AT89C52 and AT80LV52 microcontrollers
128 MICROCONTROLLER_AT89X55 Atmel AT89C55 and AT80LV55 microcontrollers
129 MICROCONTROLLER_DS5000 Dallas DS5000 & DS2250 microcontroller
130 MICROCONTROLLER_DS5001 Dallas DS5001 & DS2251 microcontroller
131 MICROCONTROLLER_DS80C32X Dallas DS80C320 and DS80C323 microcontrollers
132 MICROCONTROLLER_DS80C390 Dallas DS80C390 microcontroller
133 MICROCONTROLLER_DS89C420 Dallas DS89C420 microcontroller
134 MICROCONTROLLER_DS8XC520 Dallas DS87C520 and DS83C520 microcontrollers
135 MICROCONTROLLER_P80C552 Philips P80C552
136 MICROCONTROLLER_P89C668 Philips P89C668
137 MICROCONTROLLER_SAB80515 Infineon / Siemens SAB80515 & SAB80535
138 MICROCONTROLLER_SAB80515A Infineon / Siemens SAB80515A
139 MICROCONTROLLER_SAB80517 Infineon / Siemens SAB80517
140 MICROCONTROLLER_T89C51RD2 Atmel T89C51RD2
142 Additional definitions (use them prior the #include mcs51reg.h statement):
144 Ports P0 & P2 are not available if external ROM used.
145 Use statement "#define MCS51REG_EXTERNAL_ROM" to undefine P0 & P2.
147 Ports P0, P2, P3_6, WR, P3_7 & RD are not available if external RAM is used.
148 Use statement "#define MCS51REG_EXTERNAL_RAM" to undefine P0, P2,
151 #define MCS51REG_ENABLE_WARNINGS -> enable warnings
153 -----------------------------------------------------------------------*/
156 #ifndef HEADER_MCS51REG
157 #define HEADER_MCS51REG
159 ///////////////////////////////////////////////////////
160 /// Insert header here (for developers only) ///
161 /// remove "//" from the begining of the next line ///
162 //#include "mcs51reg_update.h" ///
163 ///////////////////////////////////////////////////////
165 //////////////////////////////////
166 /// Describe microcontrollers ///
167 /// (inventory of registers) ///
168 //////////////////////////////////
170 // definitions for the 8051
171 #ifdef MICROCONTROLLER_8051
172 #ifdef MICROCONTROLLER_DEFINED
173 #define MCS51REG_ERROR
175 #ifndef MICROCONTROLLER_DEFINED
176 #define MICROCONTROLLER_DEFINED
178 #ifdef MCS51REG_ENABLE_WARNINGS
179 #warning Selected HW: 8051
185 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
196 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
198 #define IP__x__x__x__PS__PT1__PX1__PT0__PX0
203 // end of definitions for the 8051
206 // definitions for the 8052 microcontroller
207 #ifdef MICROCONTROLLER_8052
208 #ifdef MICROCONTROLLER_DEFINED
209 #define MCS51REG_ERROR
211 #ifndef MICROCONTROLLER_DEFINED
212 #define MICROCONTROLLER_DEFINED
214 #ifdef MCS51REG_ENABLE_WARNINGS
215 #warning Selected HW: 8052
222 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
233 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
235 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
239 // 8052 specific registers
240 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
246 // end of definitions for the 8052 microcontroller
249 // definitionsons for the Atmel
250 // AT89C1051, AT89C2051 and AT89C4051 microcontrollers
251 #ifdef MICROCONTROLLER_AT89CX051
252 #ifdef MICROCONTROLLER_DEFINED
253 #define MCS51REG_ERROR
255 #ifndef MICROCONTROLLER_DEFINED
256 #define MICROCONTROLLER_DEFINED
258 #ifdef MCS51REG_ENABLE_WARNINGS
259 #warning Selected HW: Atmel AT89Cx051
261 // 8051 register set without P0 & P2
265 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
275 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
277 #define IP__x__x__x__PS__PT1__PX1__PT0__PX0
282 // end of definitionsons for the Atmel
283 // AT89C1051, AT89C2051 and AT89C4051 microcontrollers
286 // definitions for the Atmel AT89S53
287 #ifdef MICROCONTROLLER_AT89S53
288 #ifdef MICROCONTROLLER_DEFINED
289 #define MCS51REG_ERROR
291 #ifndef MICROCONTROLLER_DEFINED
292 #define MICROCONTROLLER_DEFINED
294 #ifdef MCS51REG_ENABLE_WARNINGS
295 #warning Selected HW: AT89S53
302 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
313 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
315 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
319 // 8052 specific registers
320 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
325 // AT89S53 specific register
326 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
327 #define P1_EXT__x__x__x__x__x__x__T2EX__T2
335 // end of definitions for the Atmel AT89S53 microcontroller
338 // definitions for the Atmel AT89C52 and AT89LV52 microcontrollers
339 #ifdef MICROCONTROLLER_AT89X52
340 #ifdef MICROCONTROLLER_DEFINED
341 #define MCS51REG_ERROR
343 #ifndef MICROCONTROLLER_DEFINED
344 #define MICROCONTROLLER_DEFINED
346 #ifdef MCS51REG_ENABLE_WARNINGS
347 #warning Selected HW: AT89C52 or AT89LV52
354 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
365 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
367 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
371 // 8052 specific registers
372 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
377 // AT89X55 specific register
378 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
379 #define P1_EXT__x__x__x__x__x__x__T2EX__T2
381 // end of definitions for the Atmel AT89C52 and AT89LV52 microcontrollers
384 // definitions for the Atmel AT89C55 and AT89LV55 microcontrollers
385 #ifdef MICROCONTROLLER_AT89X55
386 #ifdef MICROCONTROLLER_DEFINED
387 #define MCS51REG_ERROR
389 #ifndef MICROCONTROLLER_DEFINED
390 #define MICROCONTROLLER_DEFINED
392 #ifdef MCS51REG_ENABLE_WARNINGS
393 #warning Selected HW: AT89C55 or AT89LV55
400 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
411 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
413 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
417 // 8052 specific registers
418 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
423 // AT89X55 specific register
424 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
425 #define P1_EXT__x__x__x__x__x__x__T2EX__T2
427 // end of definitions for the Atmel AT89C55 and AT89LV55 microcontrollers
430 // definitions for the Dallas DS5000
431 #ifdef MICROCONTROLLER_DS5000
432 #ifdef MICROCONTROLLER_DEFINED
433 #define MCS51REG_ERROR
435 #ifndef MICROCONTROLLER_DEFINED
436 #define MICROCONTROLLER_DEFINED
438 #ifdef MCS51REG_ENABLE_WARNINGS
439 #warning Selected HW: DS5000
445 #define PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
456 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
458 #define IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
459 #define MCON__SL__PAA__ECE2__RA32_8__PA0__PA1__PA2__PA3
465 // end of definitions for the Dallas DS5000
468 // definitions for the Dallas DS5001
469 #ifdef MICROCONTROLLER_DS5001
470 #ifdef MICROCONTROLLER_DEFINED
471 #define MCS51REG_ERROR
473 #ifndef MICROCONTROLLER_DEFINED
474 #define MICROCONTROLLER_DEFINED
476 #ifdef MCS51REG_ENABLE_WARNINGS
477 #warning Selected HW: DS5001
483 #define PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
494 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
496 #define IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
500 #define MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL
505 #define STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF
509 // end of definitions for the Dallas DS5001
512 // definitions for the Dallas DS80C320 and DS80C323 microcontrollers
513 #ifdef MICROCONTROLLER_DS80C32X
514 #ifdef MICROCONTROLLER_DEFINED
515 #define MCS51REG_ERROR
517 #ifndef MICROCONTROLLER_DEFINED
518 #define MICROCONTROLLER_DEFINED
520 #ifdef MCS51REG_ENABLE_WARNINGS
521 #warning Selected HW: Dallas DS80C320 or DS80C323
528 #define PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
540 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
542 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
546 // 8052 specific registers
547 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
552 // DS80C320 specific register
555 #define DPS__x__x__x__x__x__x__x__SEL
556 #define CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
557 #define EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
564 #define STATUS__PIP__HIP__LIP__x__x__x__x__x
566 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
567 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
569 #define EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
570 #define EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2
572 // end of definitions for the Dallas DS80C320 and DS80C323 microcontrollers
575 // definitions for the Dallas DS80C390
576 #ifdef MICROCONTROLLER_DS80C390
577 #ifdef MICROCONTROLLER_DEFINED
578 #define MCS51REG_ERROR
580 #ifndef MICROCONTROLLER_DEFINED
581 #define MICROCONTROLLER_DEFINED
583 #ifdef MCS51REG_ENABLE_WARNINGS
584 #warning Selected HW: Dallas DS80C390
591 #define PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
603 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
605 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
609 // 8052 specific registers
610 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
615 // DS80C390 specific register
619 #define DPS__ID1__ID0__TSL__x__x__x__x__SEL
620 #define CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
621 #define EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
629 #define ACON__x__x__x__x__x__SA__AM1__AM0
660 #define PMR__CD1__CD0__SWB__CTM__4X_2X__ALEOFF__x__x
661 #define STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
662 #define MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0
664 #define T2MOD__x__x__x__D13T1__D13T2__x__T2OE__DCEN
681 #define EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2
692 #define EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
699 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
701 // end of definitions for the Dallas DS80C390
703 // definitions for the Dallas DS89C420 microcontroller
704 #ifdef MICROCONTROLLER_DS89C420
705 #ifdef MICROCONTROLLER_DEFINED
706 #define MCS51REG_ERROR
708 #ifndef MICROCONTROLLER_DEFINED
709 #define MICROCONTROLLER_DEFINED
711 #ifdef MCS51REG_ENABLE_WARNINGS
712 #warning Selected HW: Dallas DS89C420
719 #define PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
731 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
733 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
737 // 8052 specific registers
738 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
743 // DS8XC420 specific registers
744 #define ACON__PAGEE__PAGES1__PAGES0__x__x__x__x__x
747 #define DPS__ID1__ID0__TSL__AID__x__x__x__SEL
748 #define CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
750 #define IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
751 #define IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
752 #define EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
753 #define PMR__CD1__CD0__SWB__CTM__4X_2X__ALEON__DME1__DME0
760 #define STATUS__PIS2__PIS1__PIS0__x__SPTA1__SPRA1__SPTA0__SPRA0
762 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
763 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
764 #define ROMSIZE__x__x__x__x__PRAME__RMS2__RMS1__RMS0
766 #define EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
767 #define EIP0__x__x__x__LPWDI__LPX5__LPX4__LPX3__LPX2
768 #define EIP1__x__x__x__MPWDI__MPX5__MPX4__MPX3__MPX2
769 #define FCNTL__FBUSY__FERR__x__x__FC3__FC2__FC1__FC0
771 // end of definitions for the Dallas DS89C420 microcontroller
773 // definitions for the Dallas DS87C520 and DS83C520 microcontrollers
774 #ifdef MICROCONTROLLER_DS8XC520
775 #ifdef MICROCONTROLLER_DEFINED
776 #define MCS51REG_ERROR
778 #ifndef MICROCONTROLLER_DEFINED
779 #define MICROCONTROLLER_DEFINED
781 #ifdef MCS51REG_ENABLE_WARNINGS
782 #warning Selected HW: Dallas DS87C520 or DS85C520
789 #define PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
801 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
803 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
807 // 8052 specific registers
808 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
813 // DS8XC520 specific registers
816 #define DPS__x__x__x__x__x__x__x__SEL
817 #define CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
818 #define EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
819 #define PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1__DME0
826 #define STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
828 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
829 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
831 #define ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0
834 #define EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
835 #define EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2
837 // end of definitions for the Dallas DS87C520 and DS83C520 microcontrollers
840 // definitions for the Philips P80C552 microcontroller
841 #ifdef MICROCONTROLLER_P80C552
842 #ifdef MICROCONTROLLER_DEFINED
843 #define MCS51REG_ERROR
845 #ifndef MICROCONTROLLER_DEFINED
846 #define MICROCONTROLLER_DEFINED
848 #ifdef MCS51REG_ENABLE_WARNINGS
849 #warning Selected HW: Philips P80C552
856 #define PCON__SMOD__x__x__WLE__GF1__GF0__PD__IDL
867 #define IE__EA__EAD__ES1__ES0__ET1__EX1__ET0__EX0
869 #define IP__x__PAD__PS1__PS0__PT1__PX1__PT0__PX0
873 // P80C552 specific register-names
874 #define S0BUF // same as SBUF, set in mcs51reg.h
875 #define S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI
876 // P80C552 specific registers
878 #define ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0
879 #define CTCON__CTN3__CTP3__CTN2__CTP2__CTN1__CTP1__CTN0__CTP0
894 #define IEN1__ET2__ECM2__ECM1__ECM0__ECT3__ECT2__ECT1__ECT0
895 #define IP1__PT2__PCM2__PCM1__PCM0__PCT3__PCT2__PCT1__PCT0
899 #define P1_EXT__SDA__SCL__RT2__T2__CT3I__CT2I__CT1I__CT0I
900 #define P4_AT_0XC0__CMT0__CMT1__CMSR5__CMSR4__CMSR3__CMSR2__CMSR1__CMSR0
902 #define RTE__TP47__TP46__RP45__RP44__RP43__RP42__RP41__RP40
903 #define S1ADR__x__x__x__x__x__x__x__GC
904 #define S1DAT_AT_0XDA
905 #define S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x
906 #define S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0
907 #define STE__TG47__TG46__SP45__SP44__SP43__SP42__SP41__SP40
910 #define TM2CON__T2IS1__T2IS0__T2ER__T2B0__T2P1__T2P0__T2MS1__T2MS0
911 #define TM2IR__T20V__CMI2__CMI1__CMI0__CTI3__CTI2__CTI1__CTI0
914 // end of definitions for the Philips P80C552 microcontroller
917 // definitions for the Philips P89C668
918 #ifdef MICROCONTROLLER_P89C668
919 #ifdef MICROCONTROLLER_DEFINED
920 #define MCS51REG_ERROR
922 #ifndef MICROCONTROLLER_DEFINED
923 #define MICROCONTROLLER_DEFINED
925 #ifdef MCS51REG_ENABLE_WARNINGS
926 #warning Selected HW: P89C668
929 #define P0_EXT__AD7__AD6__AD5__AD4__AD3__AD2__AD1__AD0
931 #define P1_EXT__SDA__SCL__CEX2__CEX1__CEX0__ECI__T2EX__T2
933 #define P2_EXT__AD15__AD14__AD13__AD12__AD11__AD10__AD9__AD8
935 #define P3_EXT__x__x__CEX4__CEX3__x__x__x__x
941 #define PCON__SMOD1__SMOD0__x__POF__GF1__GF0__PD__IDL
947 #define S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI
948 #define S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0
955 #define SADEN_AT_0XB9
956 #define S1IST_AT_0XDC
957 #define S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x
958 #define S1DAT_AT_0XDA
959 #define S1ADR__x__x__x__x__x__x__x__GC
961 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
962 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
967 #define IEN0__EA__EC__ES1__ES0__ET1__EX1__ET0__EX0
968 #define IEN1__x__x__x__x__x__x__x__ET2
969 #define IP__PT2__PPC__PS1__PS0__PT1__PX1__PT0__PX0
970 #define IPH__PT2H__PPCH__PS1H__PS0H__PT1H__PX1H__PT0H__PX0H
971 #define CCON__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0
972 #define CMOD__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
973 #define AUXR__x__x__x__x__x__x__EXTRAM__A0
974 #define AUXR1__x__x__ENBOOT__x__GF2__0__x__DPS
975 #define WDTRST_AT_0XA6
976 #define CCAPM0_AT_0XC2
977 #define CCAPM1_AT_0XC3
978 #define CCAPM2_AT_0XC4
979 #define CCAPM3_AT_0XC5
980 #define CCAPM4_AT_0XC6
981 #define CCAP0L_AT_0XEA
982 #define CCAP1L_AT_0XEB
983 #define CCAP2L_AT_0XEC
984 #define CCAP3L_AT_0XED
985 #define CCAP4L_AT_0XEE
988 #define CCAP0H_AT_0XFA
989 #define CCAP1H_AT_0XFB
990 #define CCAP2H_AT_0XFC
991 #define CCAP3H_AT_0XFD
992 #define CCAP4H_AT_0XFE
994 // end of definitions for the Philips P89C668
997 // definitions for the Infineon / Siemens SAB80515 & SAB80535
998 #ifdef MICROCONTROLLER_SAB80515
999 #ifdef MICROCONTROLLER_DEFINED
1000 #define MCS51REG_ERROR
1002 #ifndef MICROCONTROLLER_DEFINED
1003 #define MICROCONTROLLER_DEFINED
1005 #ifdef MCS51REG_ENABLE_WARNINGS
1006 #warning Selected HW: Infineon / Siemens SAB80515 & SAB80535
1008 // 8051 register set without IP
1013 #define PCON__SMOD__x__x__x__x__x__x__x
1024 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
1029 // SAB80515 specific registers
1030 #define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
1031 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
1032 #define IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
1041 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
1048 #define DAPR__SAB80515
1053 // end of definitions for the Infineon / Siemens SAB80515
1056 // definitions for the Infineon / Siemens SAB80515A
1057 #ifdef MICROCONTROLLER_SAB80515A
1058 #ifdef MICROCONTROLLER_DEFINED
1059 #define MCS51REG_ERROR
1061 #ifndef MICROCONTROLLER_DEFINED
1062 #define MICROCONTROLLER_DEFINED
1064 #ifdef MCS51REG_ENABLE_WARNINGS
1065 #warning Selected HW: Infineon / Siemens SAB80515A
1067 // 8051 register set without IP
1072 #define PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
1083 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
1088 // SAB80515A specific registers
1089 #define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
1090 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
1091 #define IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
1092 #define IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
1101 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
1118 // end of definitions for the Infineon / Siemens SAB80515A
1121 // definitions for the Infineon / Siemens SAB80517
1122 #ifdef MICROCONTROLLER_SAB80517
1123 #ifdef MICROCONTROLLER_DEFINED
1124 #define MCS51REG_ERROR
1126 #ifndef MICROCONTROLLER_DEFINED
1127 #define MICROCONTROLLER_DEFINED
1129 #ifdef MCS51REG_ENABLE_WARNINGS
1130 #warning Selected HW: Infineon / Siemens SAB80517
1132 // 8051 register set without IP, SCON & SBUF
1137 #define PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
1148 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
1153 // SAB80517 specific registers
1154 #define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
1155 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
1156 #define IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
1157 #define IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
1158 #define IEN2__SAB80517
1188 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
1191 #define CTCOM_AT_0XE1
1199 #define DAPR__SAB80517
1214 #define S0CON__SM0__SM1__SM20__REN0__TB80__RB80__TI0__RI0
1218 #define S1CON_AT_0X9B
1225 // end of definitions for the Infineon / Siemens SAB80517
1228 // definitions for the Atmel T89C51RD2
1229 #ifdef MICROCONTROLLER_T89C51RD2
1230 #ifdef MICROCONTROLLER_DEFINED
1231 #define MCS51REG_ERROR
1233 #ifndef MICROCONTROLLER_DEFINED
1234 #define MICROCONTROLLER_DEFINED
1236 #ifdef MCS51REG_ENABLE_WARNINGS
1237 #warning Selected HW: T89C51RD2
1240 // 8051 register set
1245 #define PCON__SMOD1__SMOD0__x__POF__GF1__GF0__PD__IDL
1256 #define IE__EA__EC__ET2__ES__ET1__EX1__ET0__EX0
1259 #define IP__x__PPC__PT2__PS__PT1__PX1__PT0__PX0
1264 // 8052 register set
1265 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
1271 // T89C51RD2 register set
1272 #define P4_AT_0XC0__P4_7__P4_6__P4_5__P4_3__P4_2__P4_1__P4_0
1276 #define AUXR1__x__x__x__x__GF3__x__x__DPS
1277 #define WDTRST_AT_0XA6
1278 #define WDTPRG_AT_0XA7
1279 #define AUXR__x__x__M0__x__XRS1__XRS0__EXTRAM__A0
1280 #define IPH__x__PPCH__PT2H__PSH__PT1H__PX1H__PT0H__PX0H
1284 #define CKCON__X2__T0X2__T1X2__T2X2__SiX2__PcaX2__WdX2__x
1285 #define CCON__0xD8__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0
1286 #define CMOD__0xD9__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
1287 #define CCAPM0_AT_0XDA
1288 #define CCAPM1_AT_0XDB
1289 #define CCAPM2_AT_0XDC
1290 #define CCAPM3_AT_0XDD
1291 #define CCAPM4_AT_0XDE
1293 #define CCAP0L_AT_0XEA
1294 #define CCAP1L_AT_0XEB
1295 #define CCAP2L_AT_0XEC
1296 #define CCAP3L_AT_0XED
1297 #define CCAP4L_AT_0XEE
1299 #define CCAP0H_AT_0XFA
1300 #define CCAP1H_AT_0XFB
1301 #define CCAP2H_AT_0XFC
1302 #define CCAP3H_AT_0XFD
1303 #define CCAP4H_AT_0XFE
1304 #endif /* MICROCONTROLLER_T89C51RD2 */
1305 /* end of definition for the Atmel T89C51RD2 */
1308 /////////////////////////////////////////////////////////
1309 /// don't specify microcontrollers below this line! ///
1310 /////////////////////////////////////////////////////////
1313 // default microcontroller -> 8051
1314 // use default if no microcontroller specified
1315 #ifndef MICROCONTROLLER_DEFINED
1316 #define MICROCONTROLLER_DEFINED
1317 #ifdef MCS51REG_ENABLE_WARNINGS
1318 #warning No microcontroller defined!
1319 #warning Code generated for the 8051
1321 // 8051 register set
1326 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
1337 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
1339 #define IP__x__x__x__PS__PT1__PX1__PT0__PX0
1344 // end of definitions for the default microcontroller
1347 #ifdef MCS51REG_ERROR
1348 #error Two or more microcontrollers defined!
1351 #ifdef MCS51REG_EXTERNAL_ROM
1352 #ifndef MCS51REG_UNDEFINE_P0
1353 #define MCS51REG_UNDEFINE_P0
1355 #ifndef MCS51REG_UNDEFINE_P2
1356 #define MCS51REG_UNDEFINE_P2
1360 #ifdef MCS51REG_EXTERNAL_RAM
1361 #ifndef MCS51REG_UNDEFINE_P0
1362 #define MCS51REG_UNDEFINE_P0
1364 #ifndef MCS51REG_UNDEFINE_P2
1365 #define MCS51REG_UNDEFINE_P2
1369 #ifdef MCS51REG_UNDEFINE_P0
1373 #ifdef MCS51REG_UNDEFINE_P2
1377 ////////////////////////////////
1378 /// Register definitions ///
1379 /// (In alphabetical order) ///
1380 ////////////////////////////////
1387 #ifdef ACON__PAGEE__PAGES1__PAGES0__x__x__x__x__x
1388 #undef ACON__PAGEE__PAGES1__PAGES0__x__x__x__x__x
1389 sfr at 0x9D ACON ; // DS89C420 specific
1390 // Not directly accessible bits
1396 #ifdef ACON__x__x__x__x__x__SA__AM1__AM0
1397 #undef ACON__x__x__x__x__x__SA__AM1__AM0
1398 sfr at 0x9D ACON ; // DS89C390 specific
1399 // Not directly accessible bits
1407 sfr at 0xC6 ADCH ; // A/D converter high
1412 sfr at 0xD8 ADCON ; // A/D-converter control register SAB80515 specific
1423 // ADCON0 ... Infineon / Siemens also called this register ADCON in the User Manual
1426 sfr at 0xD8 ADCON0 ; // A/D-converter control register 0 SAB80515A &
1427 // Bit registers // SAB80517 specific
1436 // Not directly accessible ADCON0
1437 #define ADCON0_MX0 0x01
1438 #define ADCON0_MX1 0x02
1439 #define ADCON0_MX2 0x04
1440 #define ADCON0_ADM 0x08
1441 #define ADCON0_BSY 0x10
1442 #define ADCON0_ADEX 0x20
1443 #define ADCON0_CLK 0x40
1444 #define ADCON0_BD 0x80
1449 sfr at 0xDC ADCON1 ; // A/D-converter control register 1 SAB80515A & SAB80517 specific
1450 // Not directly accessible ADCON1
1451 #define ADCON1_MX0 0x01
1452 #define ADCON1_MX1 0x02
1453 #define ADCON1_MX2 0x04
1454 #define ADCON1_ADCL 0x80
1457 #ifdef ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0
1458 #undef ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0
1459 sfr at 0xC5 ADCON ; // A/D control, P80C552 specific
1460 // Not directly accessible Bits.
1467 #define ADC_0 0x40 // different name as ADC0 in P5
1468 #define ADC_1 0x80 // different name as ADC1 in P5
1473 sfr at 0xD9 ADDAT ; // A/D-converter data register SAB80515 specific
1478 sfr at 0xD9 ADDATH ; // A/D data high byte SAB80515A specific
1483 sfr at 0xDA ADDATL ; // A/D data low byte SAB80515A specific
1488 sfr at 0xEF ARCON ; // arithmetic control register SAB80517
1493 sfr at 0x9C AP ; // DS80C390
1496 #ifdef AUXR__x__x__x__x__x__x__EXTRAM__A0
1497 #undef AUXR__x__x__x__x__x__x__EXTRAM__A0
1498 // P89C668 specific, Auxilary
1500 // not bit addressable:
1505 #ifdef AUXR__x__x__M0__x__XRS1__XRS0__EXTRAM__A0
1506 #undef AUXR__x__x__M0__x__XRS1__XRS0__EXTRAM__A0
1518 sbit at 0xF0 BREG_F0 ;
1519 sbit at 0xF1 BREG_F1 ;
1520 sbit at 0xF2 BREG_F2 ;
1521 sbit at 0xF3 BREG_F3 ;
1522 sbit at 0xF4 BREG_F4 ;
1523 sbit at 0xF5 BREG_F5 ;
1524 sbit at 0xF6 BREG_F6 ;
1525 sbit at 0xF7 BREG_F7 ;
1528 #ifdef AUXR1__x__x__x__x__GF3__x__x__DPS
1529 #undef AUXR1__x__x__x__x__GF3__x__x__DPS
1535 #ifdef AUXR1__x__x__ENBOOT__x__GF2__0__x__DPS
1536 #undef AUXR1__x__x__ENBOOT__x__GF2__0__x__DPS
1537 // P89C668 specific, Auxilary 1
1541 #define ALWAYS_ZERO 0x04
1548 // Not directly accessible bits
1559 sfr at 0xA3 C0C ; // DS80C390 specific
1560 // Not directly accessible bits
1573 sfr at 0xA5 C0IR ; // DS80C390 specific
1574 // Not directly accessible bits
1587 sfr at 0xAB C0M1C ; // DS80C390 specific
1588 // Not directly accessible bits
1590 #define ROW_TIH 0x02
1601 sfr at 0xAC C0M2C ; // DS80C390 specific
1606 sfr at 0xAD C0M3C ; // DS80C390 specific
1611 sfr at 0xAE C0M4C ; // DS80C390 specific
1616 sfr at 0xAF C0M5C ; // DS80C390 specific
1621 sfr at 0xB3 C0M6C ; // DS80C390 specific
1626 sfr at 0xB4 C0M7C ; // DS80C390 specific
1631 sfr at 0xB5 C0M8C ; // DS80C390 specific
1636 sfr at 0xB6 C0M9C ; // DS80C390 specific
1641 sfr at 0xB7 C0M10C ; // DS80C390 specific
1646 sfr at 0xBB C0M11C ; // DS80C390 specific
1651 sfr at 0xBC C0M12C ; // DS80C390 specific
1656 sfr at 0xBD C0M13C ; // DS80C390 specific
1661 sfr at 0xBE C0M14C ; // DS80C390 specific
1666 sfr at 0xBF C0M15C ; // DS80C390 specific
1671 sfr at 0xA7 C0RE ; // DS80C390 specific
1676 sfr at 0x96 C0RMS0 ; // DS80C390 specific
1681 sfr at 0x97 C0RMS1 ; // DS80C390 specific
1686 sfr at 0xA4 C0S ; // DS80C390 specific
1687 // Not directly accessible bits
1694 #define EC96_128 0x40
1700 sfr at 0xA6 C0TE ; // DS80C390 specific
1705 sfr at 0x9E C0TMA0 ; // DS80C390 specific
1710 sfr at 0x9F C0TMA1 ; // DS80C390 specific
1715 sfr at 0xE3 C1C ; // DS80C390 specific
1716 // Not directly accessible bits
1729 sfr at 0xE5 C1IR ; // DS80C390 specific
1730 // Not directly accessible bits
1743 sfr at 0xE7 C1RE ; // DS80C390 specific
1748 sfr at 0xEB C1M1C ; // DS80C390 specific
1753 sfr at 0xEC C1M2C ; // DS80C390 specific
1758 sfr at 0xED C1M3C ; // DS80C390 specific
1763 sfr at 0xEE C1M4C ; // DS80C390 specific
1768 sfr at 0xEF C1M5C ; // DS80C390 specific
1773 sfr at 0xF3 C1M6C ; // DS80C390 specific
1778 sfr at 0xF4 C1M7C ; // DS80C390 specific
1783 sfr at 0xF5 C1M8C ; // DS80C390 specific
1788 sfr at 0xF6 C1M9C ; // DS80C390 specific
1793 sfr at 0xF7 C1M10C ; // DS80C390 specific
1798 sfr at 0xFB C1M11C ; // DS80C390 specific
1803 sfr at 0xFC C1M12C ; // DS80C390 specific
1808 sfr at 0xFD C1M13C ; // DS80C390 specific
1813 sfr at 0xFE C1M14C ; // DS80C390 specific
1818 sfr at 0xFF C1M15C ; // DS80C390 specific
1823 sfr at 0xE4 C1S ; // DS80C390 specific
1824 // Not directly accessible bits
1837 sfr at 0xE6 C1TE ; // DS80C390 specific
1842 sfr at 0xD6 C1RSM0 ; // DS80C390 specific
1847 sfr at 0xD7 C1RSM1 ; // DS80C390 specific
1852 sfr at 0xDE C1TMA0 ; // DS80C390 specific
1857 sfr at 0xDF C1TMA1 ; // DS80C390 specific
1862 sfr at 0xC9 CC4EN ; // compare/capture 4 enable register SAB80517 specific
1865 #ifdef CCAP0H_AT_0XFA
1866 #undef CCAP0H_AT_0XFA
1867 sfr at 0xFA CCAP0H ;
1870 #ifdef CCAP1H_AT_0XFB
1871 #undef CCAP1H_AT_0XFB
1872 sfr at 0xFB CCAP1H ;
1875 #ifdef CCAP2H_AT_0XFC
1876 #undef CCAP2H_AT_0XFC
1877 sfr at 0xFC CCAP2H ;
1880 #ifdef CCAP3H_AT_0XFD
1881 #undef CCAP3H_AT_0XFD
1882 sfr at 0xFD CCAP3H ;
1885 #ifdef CCAP4H_AT_0XFE
1886 #undef CCAP4H_AT_0XFE
1887 sfr at 0xFE CCAP4H ;
1890 #ifdef CCAP0L_AT_0XEA
1891 #undef CCAP0L_AT_0XEA
1892 sfr at 0xEA CCAP0L ;
1895 #ifdef CCAP1L_AT_0XEB
1896 #undef CCAP1L_AT_0XEB
1897 sfr at 0xEB CCAP1L ;
1900 #ifdef CCAP2L_AT_0XEC
1901 #undef CCAP2L_AT_0XEC
1902 sfr at 0xEC CCAP2L ;
1905 #ifdef CCAP3L_AT_0XED
1906 #undef CCAP3L_AT_0XED
1907 sfr at 0xED CCAP3L ;
1910 #ifdef CCAP4L_AT_0XEE
1911 #undef CCAP4L_AT_0XEE
1912 sfr at 0xEE CCAP4L ;
1915 #ifdef CCAPM0_AT_0XC2
1916 #undef CCAPM0_AT_0XC2
1917 // P89C668 specific, Capture module:
1918 sfr at 0xC2 CCAPM0 ;
1921 #ifdef CCAPM0_AT_0XDA
1922 #undef CCAPM0_AT_0XDA
1923 sfr at 0xDA CCAPM0 ;
1933 #ifdef CCAPM1_AT_0XC3
1934 #undef CCAPM1_AT_0XC3
1935 sfr at 0xC3 CCAPM1 ;
1938 #ifdef CCAPM1_AT_0XDB
1939 #undef CCAPM1_AT_0XDB
1940 sfr at 0xDB CCAPM1 ;
1943 #ifdef CCAPM2_AT_0XC4
1944 #undef CCAPM2_AT_0XC4
1945 sfr at 0xC4 CCAPM2 ;
1948 #ifdef CCAPM2_AT_0XDC
1949 #undef CCAPM2_AT_0XDC
1950 sfr at 0x0DC CCAPM2 ;
1953 #ifdef CCAPM3_AT_0XC5
1954 #undef CCAPM3_AT_0XC5
1955 sfr at 0xC5 CCAPM3 ;
1958 #ifdef CCAPM3_AT_0XDD
1959 #undef CCAPM3_AT_0XDD
1960 sfr at 0x0DD CCAPM3 ;
1963 #ifdef CCAPM4_AT_0XDE
1964 #undef CCAPM4_AT_0XDE
1965 sfr at 0x0DE CCAPM4 ;
1968 #ifdef CCAPM4_AT_0XC6
1969 #undef CCAPM4_AT_0XC6
1970 sfr at 0xC6 CCAPM4 ;
1975 sfr at 0xC1 CCEN ; // compare/capture enable register SAB80515 specific
1980 sfr at 0xC3 CCH1 ; // compare/capture register 1, high byte SAB80515 specific
1985 sfr at 0xC5 CCH2 ; // compare/capture register 2, high byte SAB80515 specific
1990 sfr at 0xC7 CCH3 ; // compare/capture register 3, high byte SAB80515 specific
1995 sfr at 0xCF CCH4 ; // compare/capture register 4, high byte SAB80515 specific
2000 sfr at 0xC2 CCL1 ; // compare/capture register 1, low byte SAB80515 specific
2005 sfr at 0xC4 CCL2 ; // compare/capture register 2, low byte SAB80515 specific
2010 sfr at 0xC6 CCL3 ; // compare/capture register 3, low byte SAB80515 specific
2015 sfr at 0xCE CCL4 ; // compare/capture register 4, low byte SAB80515 specific
2018 #ifdef CCON__0xD8__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0
2019 #undef CCON__0xD8__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0
2020 sfr at 0xD8 CCON ; // T89C51RD2 specific register
2031 #ifdef CCON__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0
2032 #undef CCON__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0
2033 // P89C668 specific, PCA Counter control:
2051 #ifdef CMOD__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
2052 #undef CMOD__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
2053 // P89C668 specific, PCA Counter mode:
2055 // not bit addressable:
2063 #ifdef CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
2064 #undef CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
2065 sfr at 0x8E CKCON ; // DS80C320 & DS80C390 specific
2066 // Not directly accessible Bits.
2077 #ifdef CKCON__X2__T0X2__T1X2__T2X2__SiX2__PcaX2__WdX2__x
2078 #undef CKCON__X2__T0X2__T1X2__T2X2__SiX2__PcaX2__WdX2__x
2091 sfr at 0x96 CKMOD ; // DS89C420 specific
2092 // Not directly accessible Bits.
2105 sfr at 0xF6 CMEN ; // compare enable register SAB80517 specific
2110 sfr at 0xD3 CMH0 ; // compare register 0 high byte SAB80517 specific
2115 sfr at 0xD5 CMH1 ; // compare register 1 high byte SAB80517 specific
2120 sfr at 0xD7 CMH2 ; // compare register 2 high byte SAB80517 specific
2125 sfr at 0xE3 CMH3 ; // compare register 3 high byte SAB80517 specific
2130 sfr at 0xE5 CMH4 ; // compare register 4 high byte SAB80517 specific
2135 sfr at 0xE7 CMH5 ; // compare register 5 high byte SAB80517 specific
2140 sfr at 0xF3 CMH6 ; // compare register 6 high byte SAB80517 specific
2145 sfr at 0xF5 CMH7 ; // compare register 7 high byte SAB80517 specific
2150 sfr at 0xC9 CMH0 ; // Compare high 0, P80C552 specific
2155 sfr at 0xCA CMH1 ; // Compare high 1, P80C552 specific
2160 sfr at 0xCB CMH2 ; // Compare high 2, P80C552 specific
2165 sfr at 0xD2 CML0 ; // compare register 0 low byte SAB80517 specific
2170 sfr at 0xD4 CML1 ; // compare register 1 low byte SAB80517 specific
2175 sfr at 0xD6 CML2 ; // compare register 2 low byte SAB80517 specific
2180 sfr at 0xE2 CML3 ; // compare register 3 low byte SAB80517 specific
2185 sfr at 0xE4 CML4 ; // compare register 4 low byte SAB80517 specific
2190 sfr at 0xE6 CML5 ; // compare register 5 low byte SAB80517 specific
2195 sfr at 0xF2 CML6 ; // compare register 6 low byte SAB80517 specific
2200 sfr at 0xF4 CML7 ; // compare register 7 low byte SAB80517 specific
2205 sfr at 0xA9 CML0 ; // Compare low 0, P80C552 specific
2210 sfr at 0xAA CML1 ; // Compare low 1, P80C552 specific
2215 sfr at 0xAB CML2 ; // Compare low 2, P80C552 specific
2218 #ifdef CMOD__0xD9__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
2219 #undef CMOD__0xD9__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
2230 sfr at 0xF7 CMSEL ; // compare input select SAB80517
2235 sfr at 0xCE COR ; // Dallas DS80C390 specific
2248 sfr at 0xC1 CRC ; // Dallas DS5001 specific
2259 sfr at 0xCB CRCH ; // compare/reload/capture register, high byte SAB80515 specific
2264 sfr at 0xC3 CRCHIGH ; // DS5001 specific
2269 sfr at 0xCA CRCL ; // compare/reload/capture register, low byte SAB80515 specific
2274 sfr at 0xC2 CRCLOW ; // DS5001 specific
2277 #ifdef CTCOM_AT_0XE1
2278 #undef CTCOM_AT_0XE1
2279 sfr at 0xE1 CTCON ; // com.timer control register SAB80517
2282 #ifdef CTCON__CTN3__CTP3__CTN2__CTP2__CTN1__CTP1__CTN0__CTP0
2283 #undef CTCON__CTN3__CTP3__CTN2__CTP2__CTN1__CTP1__CTN0__CTP0
2284 sfr at 0xEB CTCON ; // Capture control, P80C552 specific
2285 // Not directly accessible Bits.
2298 sfr at 0xCC CTH0 ; // Capture high 0, P80C552 specific
2303 sfr at 0xCD CTH1 ; // Capture high 1, P80C552 specific
2308 sfr at 0xCE CTH2 ; // Capture high 2, P80C552 specific
2313 sfr at 0xCF CTH3 ; // Capture high 3, P80C552 specific
2318 sfr at 0xAC CTL0 ; // Capture low 0, P80C552 specific
2323 sfr at 0xAD CTL1 ; // Capture low 1, P80C552 specific
2328 sfr at 0xAE CTL2 ; // Capture low 2, P80C552 specific
2333 sfr at 0xAF CTL3 ; // Capture low 3, P80C552 specific
2338 sfr at 0xDF CTRELH ; // com.timer rel register high byte SAB80517
2343 sfr at 0xDE CTRELL ; // com.timer rel register low byte SAB80517
2346 #ifdef DAPR__SAB80515
2347 #undef DAPR__SAB80515
2348 sfr at 0xD8 DAPR ; // D/A-converter program register SAB80515 specific
2351 #ifdef DAPR__SAB80517
2352 #undef DAPR__SAB80517
2353 sfr at 0xDA DAPR ; // D/A-converter program register SAB80517 specific
2359 sfr at 0x83 DP0H ; // Alternate name for AT89S53
2364 sfr at 0x85 DPH1 ; // DS80C320 specific
2365 sfr at 0x85 DP1H ; // Alternate name for AT89S53
2370 sfr at 0x82 DPL ; // Alternate name for AT89S53
2376 sfr at 0x84 DPL1 ; // DS80C320 specific
2377 sfr at 0x84 DP1L ; // Alternate name for AT89S53
2380 #ifdef DPS__x__x__x__x__x__x__x__SEL
2381 #undef DPS__x__x__x__x__x__x__x__SEL
2383 // Not directly accessible DPS Bit. DS80C320 & DPS8XC520 specific
2387 #ifdef DPS__ID1__ID0__TSL__x__x__x__x__SEL
2388 #undef DPS__ID1__ID0__TSL__x__x__x__x__SEL
2390 // Not directly accessible DPS Bit. DS89C390 specific
2397 #ifdef DPS__ID1__ID0__TSL__AID__x__x__x__SEL
2398 #undef DPS__ID1__ID0__TSL__AID__x__x__x__SEL
2400 // Not directly accessible DPS Bit. DS89C420 specific
2410 sfr at 0x92 DPSEL ; // data pointer select register SAB80517
2415 sfr at 0x93 DPX1 ; // DS80C390 specific
2420 sfr at 0x95 DPX1 ; // DS80C390 specific
2440 #ifdef EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
2441 #undef EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
2443 // Bit registers DS80C320 specific
2451 #ifdef EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2
2452 #undef EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2
2454 // Bit registers DS80C390 specific
2462 sbit at 0xEF CANBIE ;
2465 #ifdef EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2
2466 #undef EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2
2468 // Bit registers DS80C320 specific
2476 #ifdef EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
2477 #undef EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
2479 // Bit registers DS80C320 specific
2487 sbit at 0xFF CANBIP ;
2490 #ifdef EIP0__x__x__x__LPWDI__LPX5__LPX4__LPX3__LPX2
2491 #undef EIP0__x__x__x__LPWDI__LPX5__LPX4__LPX3__LPX2
2493 // Bit registers DS89C420 specific
2498 sbit at 0xFC LPWDI ;
2501 #ifdef EIP1__x__x__x__MPWDI__MPX5__MPX4__MPX3__MPX2
2502 #undef EIP1__x__x__x__MPWDI__MPX5__MPX4__MPX3__MPX2
2504 // Not directly accessible Bits DS89C420 specific
2515 // Not directly accessible Bits DS80C390 specific
2520 #ifdef EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
2521 #undef EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
2523 // Not directly accessible EXIF Bits DS80C320 specific
2533 #ifdef EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
2534 #undef EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
2536 // Not directly accessible EXIF Bits DS87C520 specific
2547 #ifdef EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
2548 #undef EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
2550 // Not directly accessible EXIF Bits DS80C390 & DS89C420 specific
2561 #ifdef FCNTL__FBUSY__FERR__x__x__FC3__FC2__FC1__FC0
2562 #undef FCNTL__FBUSY__FERR__x__x__FC3__FC2__FC1__FC0
2564 // Not directly accessible DS89C420 specific
2592 #ifdef IE__EA__x__x__ES__ET1__EX1__ET0__EX0
2593 #undef IE__EA__x__x__ES__ET1__EX1__ET0__EX0
2604 #ifdef IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
2605 #undef IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
2613 sbit at 0xAD ET2 ; // Enable timer2 interrupt
2617 #ifdef IE__EA__EAD__ES1__ES0__ET1__EX1__ET0__EX0
2618 #undef IE__EA__EAD__ES1__ES0__ET1__EX1__ET0__EX0
2619 sfr at 0xA8 IE ; // same as IEN0 - Interrupt enable 0, P80C552 specific
2620 sfr at 0xA8 IEN0 ; // alternate name
2632 #ifdef IE__EA__EC__ET2__ES__ET1__EX1__ET0__EX0
2633 #undef IE__EA__EC__ET2__ES__ET1__EX1__ET0__EX0
2645 #ifdef IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
2646 #undef IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
2654 sbit at 0xAC ES0 ; // Alternate name
2655 sbit at 0xAD ET2 ; // Enable timer2 interrupt
2660 #ifdef IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
2661 #undef IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
2663 sfr at 0xA8 IEN0 ; // Alternate name
2664 // Bit registers for the SAB80515 and compatible IE
2671 sbit at 0xAD ET2 ; // Enable timer 2 overflow SAB80515 specific
2672 sbit at 0xAE WDT ; // watchdog timer reset - SAB80515 specific
2674 sbit at 0xAF EAL ; // EA as called by Infineon / Siemens
2677 #ifdef IEN0__EA__EC__ES1__ES0__ET1__EX1__ET0__EX0
2678 #undef IEN0__EA__EC__ES1__ES0__ET1__EX1__ET0__EX0
2692 #ifdef IEN1__x__x__x__x__x__x__x__ET2
2693 #undef IEN1__x__x__x__x__x__x__x__ET2
2694 // P89C668 specific bit registers
2700 #ifdef IEN1__ET2__ECM2__ECM1__ECM0__ECT3__ECT2__ECT1__ECT0
2701 #undef IEN1__ET2__ECM2__ECM1__ECM0__ECT3__ECT2__ECT1__ECT0
2702 sfr at 0xE8 IEN1 ; // Interrupt enable 1, P80C552 specific
2714 #ifdef IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
2715 #undef IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
2716 sfr at 0xB8 IEN1 ; // interrupt enable register - SAB80515 specific
2718 sbit at 0xB8 EADC ; // A/D converter interrupt enable
2724 sbit at 0xBE SWDT ; // watchdog timer start/reset
2725 sbit at 0xBF EXEN2 ; // timer2 external reload interrupt enable
2728 #ifdef IEN2__SAB80517
2729 #undef IEN2__SAB80517
2730 sfr at 0x9A IEN2 ; // interrupt enable register 2 SAB80517
2733 #ifdef IP__x__x__x__PS__PT1__PX1__PT0__PX0
2734 #undef IP__x__x__x__PS__PT1__PX1__PT0__PX0
2744 #ifdef IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
2745 #undef IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
2753 sbit at 0xBC PS0 ; // alternate name
2757 #ifdef IP__x__PAD__PS1__PS0__PT1__PX1__PT0__PX0
2758 #undef IP__x__PAD__PS1__PS0__PT1__PX1__PT0__PX0
2759 sfr at 0xB8 IP ; // Interrupt priority 0, P80C552 specific
2760 sfr at 0xB8 IP0 ; // alternate name
2771 #ifdef IP__x__PPC__PT2__PS__PT1__PX1__PT0__PX0
2772 #undef IP__x__PPC__PT2__PS__PT1__PX1__PT0__PX0
2784 #ifdef IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
2785 #undef IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
2797 #ifdef IP__PT2__PPC__PS1__PS0__PT1__PX1__PT0__PX0
2798 #undef IP__PT2__PPC__PS1__PS0__PT1__PX1__PT0__PX0
2799 // P89C668 specific:
2812 #ifdef IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
2813 #undef IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
2824 #ifdef IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
2825 #undef IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
2826 sfr at 0xA9 IP0 ; // interrupt priority register SAB80515 specific
2827 // Not directly accessible IP0 bits
2837 #ifdef IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
2838 #undef IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
2839 sfr at 0xB8 IP0 ; // interrupt priority register DS89C420 specific
2840 // Not directly accessible IP0 bits
2850 #ifdef IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
2851 #undef IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
2852 sfr at 0xB9 IP1 ; // interrupt priority register SAB80515 specific
2853 // Not directly accessible IP1 bits
2862 #ifdef IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
2863 #undef IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
2864 sfr at 0xB1 IP1 ; // interrupt priority register DS89C420 specific
2865 // Not directly accessible IP0 bits
2875 #ifdef IP1__PT2__PCM2__PCM1__PCM0__PCT3__PCT2__PCT1__PCT0
2876 #undef IP1__PT2__PCM2__PCM1__PCM0__PCT3__PCT2__PCT1__PCT0
2877 sfr at 0xF8 IP1 ; // Interrupt priority 1, P80C552 specific
2889 #ifdef IPH__x__PPCH__PT2H__PSH__PT1H__PX1H__PT0H__PX0H
2890 #undef IPH__x__PPCH__PT2H__PSH__PT1H__PX1H__PT0H__PX0H
2901 #ifdef IPH__PT2H__PPCH__PS1H__PS0H__PT1H__PX1H__PT0H__PX0H
2902 #undef IPH__PT2H__PPCH__PS1H__PS0H__PT1H__PX1H__PT0H__PX0H
2903 // P89C668 specific:
2905 // not bit addressable:
2918 sfr at 0xC0 IRCON ; // interrupt control register - SAB80515 specific
2920 sbit at 0xC0 IADC ; // A/D converter irq flag
2921 sbit at 0xC1 IEX2 ; // external interrupt edge detect flag
2926 sbit at 0xC6 TF2 ; // timer 2 owerflow flag
2927 sbit at 0xC7 EXF2 ; // timer2 reload flag
2932 sfr at 0xC0 IRCON0 ; // interrupt control register - SAB80515 specific
2934 sbit at 0xC0 IADC ; // A/D converter irq flag
2935 sbit at 0xC1 IEX2 ; // external interrupt edge detect flag
2940 sbit at 0xC6 TF2 ; // timer 2 owerflow flag
2941 sbit at 0xC7 EXF2 ; // timer2 reload flag
2946 sfr at 0xD1 IRCON1 ; // interrupt control register - SAB80515 specific
2951 sfr at 0xD3 MA ; // DS80C390
2956 sfr at 0xD4 MB ; // DS80C390
2961 sfr at 0xD5 MC ; // DS80C390
2966 sfr at 0xD1 MCNT0 ; // DS80C390
2979 sfr at 0xD2 MCNT1 ; // DS80C390
2985 #ifdef MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0
2986 #undef MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0
2987 sfr at 0xC6 MCON ; // DS80C390
2997 #ifdef MCON__PA3__PA2__PA1__PA0__RA32_8__ECE2__PAA__SL
2998 #undef MCON__PA3__PA2__PA1__PA0__RA32_8__ECE2__PAA__SL
2999 sfr at 0xC6 MCON ; // DS5000
3010 #ifdef MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL
3011 #undef MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL
3012 sfr at 0xC6 MCON ; // DS5001
3025 sfr at 0xE9 MD0 ; // MUL / DIV register 0 SAB80517
3030 sfr at 0xEA MD1 ; // MUL / DIV register 1 SAB80517
3035 sfr at 0xEB MD2 ; // MUL / DIV register 2 SAB80517
3040 sfr at 0xEC MD3 ; // MUL / DIV register 3 SAB80517
3045 sfr at 0xED MD4 ; // MUL / DIV register 4 SAB80517
3050 sfr at 0xEE MD5 ; // MUL / DIV register 5 SAB80517
3055 sfr at 0xEA MXAX ; // Dallas DS80C390
3072 #ifdef P0_EXT__AD7__AD6__AD5__AD4__AD3__AD2__AD1__AD0
3073 #undef P0_EXT__AD7__AD6__AD5__AD4__AD3__AD2__AD1__AD0
3074 // P89C668 alternate names for bits in P0
3099 #ifdef P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
3100 #undef P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
3101 // P1 alternate functions
3112 #ifdef P1_EXT__SDA__SCL__CEX2__CEX1__CEX0__ECI__T2EX__T2
3113 #undef P1_EXT__SDA__SCL__CEX2__CEX1__CEX0__ECI__T2EX__T2
3114 // P89C669 alternate names for bits at P1
3115 // P1_EXT__SDA__SCL__CEX2__CEX1__CEX0__ECI__T2EX__T2
3126 #ifdef P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
3127 sbit at 0x90 INT3_CC0 ; // P1 alternate functions - SAB80515 specific
3128 sbit at 0x91 INT4_CC1 ;
3129 sbit at 0x92 INT5_CC2 ;
3130 sbit at 0x93 INT6_CC3 ;
3133 sbit at 0x96 CLKOUT ;
3137 #ifdef P1_EXT__CT0I__CT1I__CT2I__CT3I__T2__RT2__SCL__SDA
3138 #undef P1_EXT__CT0I__CT1I__CT2I__CT3I__T2__RT2__SCL__SDA
3140 sbit at 0x90 CT0I ; // Port 1 alternate functions, P80C552 specific
3150 #ifdef P1_EXT__x__x__x__x__x__x__T2EX__T2
3151 #undef P1_EXT__x__x__x__x__x__x__T2EX__T2
3152 // P1 alternate functions
3171 #ifdef P2_EXT__AD15__AD14__AD13__AD12__AD11__AD10__AD9__AD8
3172 #undef P2_EXT__AD15__AD14__AD13__AD12__AD11__AD10__AD9__AD8
3173 // P89C668 specific bit registers at P2:
3194 #ifndef MCS51REG_EXTERNAL_RAM
3207 #ifndef MCS51REG_EXTERNAL_RAM
3213 #ifdef P3_EXT__x__x__CEX4__CEX3__x__x__x__x
3214 #undef P3_EXT__x__x__CEX4__CEX3__x__x__x__x
3215 // P89C668 specific bit registers at P3 (alternate names)
3222 sfr at 0x80 P4 ; // Port 4 - DS80C390
3234 #ifdef P4_AT_0XC0__CMT0__CMT1__CMSR5__CMSR4__CMSR3__CMSR2__CMSR1__CMSR0
3235 #undef P4_AT_0XC0__CMT0__CMT1__CMSR5__CMSR4__CMSR3__CMSR2__CMSR1__CMSR0
3236 sfr at 0xC0 P4 ; // Port 4, P80C552 specific
3238 sbit at 0xC0 CMSR0 ;
3239 sbit at 0xC1 CMSR1 ;
3240 sbit at 0xC2 CMSR2 ;
3241 sbit at 0xC3 CMSR3 ;
3242 sbit at 0xC4 CMSR4 ;
3243 sbit at 0xC5 CMSR5 ;
3248 #ifdef P4_AT_0XC0__P4_7__P4_6__P4_5__P4_3__P4_2__P4_1__P4_0
3249 #undef P4_AT_0XC0__P4_7__P4_6__P4_5__P4_3__P4_2__P4_1__P4_0
3250 sfr at 0xC0 P4 ; // Port 4, T89C51 specific
3264 sfr at 0xE8 P4 ; // Port 4 - SAB80515 & compatible microcontrollers
3278 sfr at 0x92 P4CNT ; // DS80C390
3279 // Not directly accessible bits
3280 #define P4CNT_0 0x01
3281 #define P4CNT_1 0x02
3282 #define P4CNT_2 0x04
3283 #define P4CNT_3 0x08
3284 #define P4CNT_4 0x10
3285 #define P4CNT_5 0x20
3291 sfr at 0xA1 P5 ; // Port 5 - DS80C390
3296 sfr at 0xE8 P5 ; // Port 5 - T89C51RD2
3310 sfr at 0xA2 P5CNT ; // DS80C390
3311 // Not directly accessible bits
3312 #define P5CNT_0 0x01
3313 #define P5CNT_1 0x02
3314 #define P5CNT_2 0x04
3318 #define SBCAN0BA 0x40
3319 #define SBCAN1BA 0x80
3324 sfr at 0xC4 P5 ; // Port 5, P80C552 specific
3325 // Not directly accessible Bits.
3338 sfr at 0xF8 P5 ; // Port 5 - SAB80515 & compatible microcontrollers
3352 sfr at 0xDB P6 ; // Port 6 - SAB80515 & compatible microcontrollers
3357 sfr at 0xFA P6 ; // Port 6 - SAB80517 specific
3362 sfr at 0xDB P7 ; // Port 7 - SAB80517 specific
3367 sfr at 0xDD P8 ; // Port 6 - SAB80517 specific
3370 #ifdef PCON__SMOD__x__x__x__x__x__x__x
3371 #undef PCON__SMOD__x__x__x__x__x__x__x
3373 // Not directly accessible PCON bits
3377 #ifdef PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
3378 #undef PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
3380 // Not directly accessible PCON bits
3388 #ifdef PCON__SMOD__x__x__WLE__GF1__GF0__PD__IDL
3389 #undef PCON__SMOD__x__x__WLE__GF1__GF0__PD__IDL
3390 sfr at 0x87 PCON ; // PCON, P80C552 specific
3391 // Not directly accessible Bits.
3393 #define IDLE 0x01 /* same as IDL */
3401 #ifdef PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
3402 #undef PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
3404 // Not directly accessible PCON bits
3406 #define IDLE 0x01 /* same as IDL */
3408 #define PDE 0x02 /* same as PD */
3413 #define PCON_IDLE 0x01
3414 #define PCON_PDE 0x02
3415 #define PCON_GF0 0x04
3416 #define PCON_GF1 0x08
3417 #define PCON_IDLS 0x20
3418 #define PCON_PDS 0x40
3419 #define PCON_SMOD 0x80
3422 #ifdef PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
3423 #undef PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
3425 // Not directly accessible PCON bits
3427 #define IDLE 0x01 /* same as IDL */
3437 #ifdef PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
3438 #undef PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
3440 // Not directly accessible PCON bits
3442 #define IDLE 0x01 /* same as IDL */
3450 #ifdef PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
3451 #undef PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
3453 // Not directly accessible PCON bits
3455 #define IDLE 0x01 /* same as IDL */
3463 #define SMOD_0 0x80 /* same as SMOD */
3466 #ifdef PCON__SMOD1__SMOD0__x__POF__GF1__GF0__PD__IDL
3467 #undef PCON__SMOD1__SMOD0__x__POF__GF1__GF0__PD__IDL
3478 #ifdef PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1__DME0
3479 #undef PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1__DME0
3480 sfr at 0xC4 PMR ; // DS87C520, DS83C520
3481 // Not directly accessible bits
3491 #ifdef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEOFF__x__x
3492 #undef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEOFF__x__x
3493 sfr at 0xC4 PMR ; // DS80C390
3494 // Not directly accessible bits
3503 #ifdef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEON__DME1__DME0
3504 #undef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEON__DME1__DME0
3505 sfr at 0xC4 PMR ; // DS89C420
3506 // Not directly accessible bits
3533 sfr at 0xFC PWM0 ; // PWM register 0, P80C552 specific
3538 sfr at 0xFD PWM1 ; // PWM register 1, P80C552 specific
3543 sfr at 0xFE PWMP ; // PWM prescaler, P80C552 specific
3548 sfr at 0xCB RCAP2H ;
3553 sfr at 0xCA RCAP2L ;
3561 #ifdef ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0
3562 #undef ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0
3563 sfr at 0xC2 ROMSIZE ; // DS87C520, DS83C520
3564 // Not directly accessible bits
3570 #ifdef ROMSIZE__x__x__x__x__PRAME__RMS2__RMS1__RMS0
3571 #undef ROMSIZE__x__x__x__x__PRAME__RMS2__RMS1__RMS0
3572 sfr at 0xC2 ROMSIZE ; // DS89C420
3573 // Not directly accessible bits
3580 #ifdef ROMSIZE__HBPF__BPF__TE__MOVCX__PRAME__RMS2__RMS1__RMS0
3581 #undef ROMSIZE__HBPF__BPF__TE__MOVCX__PRAME__RMS2__RMS1__RMS0
3582 sfr at 0xC2 ROMSIZE ; // DS87C520, DS83C520
3583 // Not directly accessible bits
3596 sfr at 0xD8 RPCTL ; // Dallas DS5001 specific
3598 sbit at 0xD9 RPCON ;
3603 sbit at 0xDF RNR_FLAG ;
3606 #ifdef RTE__TP47__TP46__RP45__RP44__RP43__RP42__RP41__RP40
3607 #undef RTE__TP47__TP46__RP45__RP44__RP43__RP42__RP41__RP40
3608 sfr at 0xEF RTE ; // Reset/toggle enable, P80C552 specific
3609 // Not directly accessible Bits.
3622 sfr at 0x99 S0BUF ; // serial channel 0 buffer register SAB80517 specific
3625 #ifdef S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI
3626 #undef S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI
3627 sfr at 0x98 S0CON ; // serial channel 0 control register P80C552 specific
3629 // Already defined in SCON
3630 //sbit at 0x98 RI0 ;
3631 //sbit at 0x99 TI0 ;
3632 //sbit at 0x9A RB8 ;
3633 //sbit at 0x9B TB8 ;
3634 //sbit at 0x9C REN ;
3635 //sbit at 0x9D SM2 ;
3636 //sbit at 0x9E SM1 ;
3637 //sbit at 0x9F SM0 ;
3640 #ifdef S0CON__SM0__SM1__SM20__REN0__TB80__RB80__TI0__RI0
3641 #undef S0CON__SM0__SM1__SM20__REN0__TB80__RB80__TI0__RI0
3642 // serial channel 0 buffer register SAB80517 specific(same as stock SCON)
3656 sfr at 0xAA S0RELL ; // serial channel 0 reload register low byte SAB80517 specific
3661 sfr at 0xBA S0RELH ; // serial channel 0 reload register high byte SAB80517 specific
3664 #ifdef S1ADR__x__x__x__x__x__x__x__GC
3665 #undef S1ADR__x__x__x__x__x__x__x__GC
3666 sfr at 0xDB S1ADR ; // Serial 1 address, P80C552 specific
3667 // Not directly accessible Bits.
3673 sfr at 0x9C S1BUF ; // serial channel 1 buffer register SAB80517 specific
3676 #ifdef S1CON_AT_0X9B
3677 #undef S1CON_AT_0X9B
3678 sfr at 0x9B S1CON ; // serial channel 1 control register SAB80517 specific
3681 #ifdef S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0
3682 #undef S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0
3683 sfr at 0xD8 S1CON ; // Serial 1 control, P80C552 specific
3684 sfr at 0xD8 SICON ; // sometimes called SICON
3696 #ifdef S1DAT_AT_0XDA
3697 #undef S1DAT_AT_0XDA
3698 sfr at 0xDA S1DAT ; // Serial 1 data, P80C552 specific
3699 sfr at 0xDA SIDAT ; // sometimes called SIDAT
3702 #ifdef S1IST_AT_0XDC
3703 #undef S1IST_AT_0XDC
3710 sfr at 0x9D S1RELL ; // serial channel 1 reload register low byte SAB80517 specific
3715 sfr at 0xBB S1RELH ; // serial channel 1 reload register high byte SAB80517 specific
3718 #ifdef S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x
3719 #undef S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x
3720 sfr at 0xD9 S1STA ; // Serial 1 status, P80C552 specific
3721 // Not directly accessible Bits.
3736 // DS80C320 specific
3737 sfr at 0xA9 SADDR0 ;
3742 // DS80C320 specific
3743 sfr at 0xAA SADDR1 ;
3746 #ifdef SADEN_AT_0XB9
3747 #undef SADEN_AT_0XB9
3753 // DS80C320 & DS80C390 specific
3754 sfr at 0xB9 SADEN0 ;
3759 // DS80C320 & DS80C390 specific
3760 sfr at 0xBA SADEN1 ;
3771 // DS80C320 & DS80C390 specific
3795 sbit at 0x9A RB8_0 ;
3796 sbit at 0x9B TB8_0 ;
3797 sbit at 0x9C REN_0 ;
3798 sbit at 0x9D SM2_0 ;
3799 sbit at 0x9E SM1_0 ;
3800 sbit at 0x9F SM0_0 ;
3802 sbit at 0x9F SM0_FE_0 ;
3807 // DS80C320 - 80C390 specific
3812 sbit at 0xC2 RB8_1 ;
3813 sbit at 0xC3 TB8_1 ;
3814 sbit at 0xC4 REN_1 ;
3815 sbit at 0xC5 SM2_1 ;
3816 sbit at 0xC6 SM1_1 ;
3817 sbit at 0xC7 SM0_1 ;
3819 sbit at 0xC7 SM0_FE_1 ;
3829 sfr at 0xD5 SPCR ; // AT89S53 specific
3830 // Not directly accesible bits
3843 sfr at 0x86 SPDR ; // AT89S53 specific
3844 // Not directly accesible bits
3857 sfr at 0xAA SPSR ; // AT89S53 specific
3858 // Not directly accesible bits
3865 sfr at 0xBA SRELH ; // Baudrate generator reload high
3870 sfr at 0xAA SRELL ; // Baudrate generator reload low
3873 #ifdef STATUS__PIP__HIP__LIP__x__x__x__x__x
3874 #undef STATUS__PIP__HIP__LIP__x__x__x__x__x
3875 // DS80C320 specific
3876 sfr at 0xC5 STATUS ;
3877 // Not directly accessible Bits. DS80C320 specific
3883 #ifdef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
3884 #undef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
3885 sfr at 0xC5 STATUS ; // DS80C390 specific
3886 // Not directly accessible Bits.
3896 #ifdef STATUS__PIS2__PIS1__PIS0__x__SPTA1__SPRA1__SPTA0__SPRA0
3897 #undef STATUS__PIS2__PIS1__PIS0__x__SPTA1__SPRA1__SPTA0__SPRA0
3898 sfr at 0xC5 STATUS ; // DS89C420 specific
3899 // Not directly accessible Bits.
3909 #ifdef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
3910 #undef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
3911 sfr at 0xC5 STATUS ; // DS80C390 specific
3912 // Not directly accessible Bits.
3922 #ifdef STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
3923 #undef STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
3924 sfr at 0xC5 STATUS ; // DS87C520 & DS83520specific
3925 // Not directly accessible Bits.
3936 #ifdef STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF
3937 #undef STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF
3938 sfr at 0xDA STATUS ; // DS5001specific
3939 // Not directly accessible Bits.
3950 #ifdef STE__TG47__TG46__SP45__SP44__SP43__SP42__SP41__SP40
3951 #undef STE__TG47__TG46__SP45__SP44__SP43__SP42__SP41__SP40
3952 sfr at 0xEE STE ; // Set enable, P80C552 specific
3953 // Not directly accessible Bits.
3966 sfr at 0xB1 SYSCON ; // XRAM Controller Access Control
3968 #define SYSCON_XMAP0 0x01
3969 #define SYSCON_XMAP1 0x02
3970 #define SYSCON_RMAP 0x10
3971 #define SYSCON_EALE 0x20
3974 #ifdef T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
3975 #undef T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
3977 // Definitions for the 8052 compatible microcontrollers.
3979 sbit at 0xC8 CP_RL2 ;
3982 sbit at 0xCB EXEN2 ;
3988 sbit at 0xC8 T2CON_0 ;
3989 sbit at 0xC9 T2CON_1 ;
3990 sbit at 0xCA T2CON_2 ;
3991 sbit at 0xCB T2CON_3 ;
3992 sbit at 0xCC T2CON_4 ;
3993 sbit at 0xCD T2CON_5 ;
3994 sbit at 0xCE T2CON_6 ;
3995 sbit at 0xCF T2CON_7 ;
3998 #ifdef T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
3999 #undef T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
4001 // Definitions for the Infineon / Siemens SAB80515, SAB80515A, SAB80517
4012 sbit at 0xC8 T2CON_0 ;
4013 sbit at 0xC9 T2CON_1 ;
4014 sbit at 0xCA T2CON_2 ;
4015 sbit at 0xCB T2CON_3 ;
4016 sbit at 0xCC T2CON_4 ;
4017 sbit at 0xCD T2CON_5 ;
4018 sbit at 0xCE T2CON_6 ;
4019 sbit at 0xCF T2CON_7 ;
4022 #ifdef T2MOD__x__x__x__D13T1__D13T2__x__T2OE__DCEN
4023 #undef T2MOD__x__x__x__D13T1__D13T2__x__T2OE__DCEN
4024 // Definitions for the timer/counter 2 of the Atmel & Dallas microcontrollers
4026 // Not not directly accessible T2MOD bits
4033 #ifdef T2MOD__x__x__x__x__x__x__T2OE__DCEN
4034 #undef T2MOD__x__x__x__x__x__x__T2OE__DCEN
4035 // Definitions for the timer/counter 2 of the Atmel 89x52 microcontroller
4037 // Not not directly accessible T2MOD bits
4047 sfr at 0xFF T3 ; // Timer 3, P80C552 specific
4052 // DS500x, DS80C320 & DS80C390 specific
4103 // Not directly accessible TMOD bits
4107 #define T0_GATE 0x08
4111 #define T1_GATE 0x80
4113 #define T0_MASK 0x0F
4114 #define T1_MASK 0xF0
4117 #ifdef TM2CON__T2IS1__T2IS0__T2ER__T2B0__T2P1__T2P0__T2MS1__T2MS0
4118 #undef TM2CON__T2IS1__T2IS0__T2ER__T2B0__T2P1__T2P0__T2MS1__T2MS0
4119 sfr at 0xEA TM2CON ; // Timer 2 control, P80C552 specific
4120 // Not directly accessible Bits.
4131 #ifdef TM2IR__T20V__CMI2__CMI1__CMI0__CTI3__CTI2__CTI1__CTI0
4132 #undef TM2IR__T20V__CMI2__CMI1__CMI0__CTI3__CTI2__CTI1__CTI0
4133 sfr at 0xC8 TM2IR ; // Timer 2 int flag reg, P80C552 specific
4147 sfr at 0xED TMH2 ; // Timer high 2, P80C552 specific
4152 sfr at 0xEC TML2 ; // Timer low 2, P80C552 specific
4157 sfr at 0x96 WCON ; // AT89S53 specific
4158 // Not directly accesible bits
4169 // DS80C320 - 390, DS89C420, etc. specific
4179 sbit at 0xDF SMOD_1 ;
4182 #ifdef WDTPRG_AT_0XA7
4183 #undef WDTPRG_AT_0XA7
4184 sfr at 0xA7 WDTPRG ;
4185 #define WDTRPRG_S0 0x01
4186 #define WDTRPRG_S1 0x02
4187 #define WDTRPRG_S2 0x04
4192 sfr at 0x86 WDTREL ; // Watchdof Timer reload register
4195 #ifdef WDTRST_AT_0XA6
4196 #undef WDTRST_AT_0XA6
4197 sfr at 0xA6 WDTRST ;
4202 sfr at 0x91 XPAGE ; // Page Address Register for Extended On-Chip Ram - Infineon / Siemens SAB80515A specific
4205 /////////////////////////
4206 /// Interrupt vectors ///
4207 /////////////////////////
4209 // Interrupt numbers: address = (number * 8) + 3
4210 #define IE0_VECTOR 0 // 0x03 external interrupt 0
4211 #define TF0_VECTOR 1 // 0x0b timer 0
4212 #define IE1_VECTOR 2 // 0x13 external interrupt 1
4213 #define TF1_VECTOR 3 // 0x1b timer 1
4214 #define SI0_VECTOR 4 // 0x23 serial port 0
4216 #ifdef MICROCONTROLLER_AT89S53
4217 #define TF2_VECTOR 5 /* 0x2B timer 2 */
4218 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
4221 #ifdef MICROCONTROLLER_AT89X52
4222 #define TF2_VECTOR 5 /* 0x2B timer 2 */
4223 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
4226 #ifdef MICROCONTROLLER_AT89X55
4227 #define TF2_VECTOR 5 /* 0x2B timer 2 */
4228 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
4231 #ifdef MICROCONTROLLER_DS5000
4232 #define PFW_VECTOR 5 /* 0x2B */
4235 #ifdef MICROCONTROLLER_DS5001
4236 #define PFW_VECTOR 5 /* 0x2B */
4239 #ifdef MICROCONTROLLER_DS80C32X
4240 #define TF2_VECTOR 5 /* 0x2B */
4241 #define PFI_VECTOR 6 /* 0x33 */
4242 #define SIO1_VECTOR 7 /* 0x3B */
4243 #define IE2_VECTOR 8 /* 0x43 */
4244 #define IE3_VECTOR 9 /* 0x4B */
4245 #define IE4_VECTOR 10 /* 0x53 */
4246 #define IE5_VECTOR 11 /* 0x5B */
4247 #define WDI_VECTOR 12 /* 0x63 */
4250 #ifdef MICROCONTROLLER_DS8XC520
4251 #define TF2_VECTOR 5 /* 0x2B */
4252 #define PFI_VECTOR 6 /* 0x33 */
4253 #define SIO1_VECTOR 7 /* 0x3B */
4254 #define IE2_VECTOR 8 /* 0x43 */
4255 #define IE3_VECTOR 9 /* 0x4B */
4256 #define IE4_VECTOR 10 /* 0x53 */
4257 #define IE5_VECTOR 11 /* 0x5B */
4258 #define WDI_VECTOR 12 /* 0x63 */
4261 #ifdef MICROCONTROLLER_P80C552
4262 #define SIO1_VECTOR 5 // 0x2B SIO1 (I2C)
4263 #define CT0_VECTOR 6 // 0x33 T2 capture 0
4264 #define CT1_VECTOR 7 // 0x3B T2 capture 1
4265 #define CT2_VECTOR 8 // 0x43 T2 capture 2
4266 #define CT3_VECTOR 9 // 0x4B T2 capture 3
4267 #define ADC_VECTOR 10 // 0x53 ADC completion
4268 #define CM0_VECTOR 11 // 0x5B T2 compare 0
4269 #define CM1_VECTOR 12 // 0x63 T2 compare 1
4270 #define CM2_VECTOR 13 // 0x6B T2 compare 2
4271 #define TF2_VECTOR 14 // 0x73 T2 overflow
4274 #ifdef MICROCONTROLLER_P89C668
4275 #define SIO1_VECTOR 5 // 0x2b SIO1 (i2c)
4276 #define PCA_VECTOR 6 // 0x33 (Programmable Counter Array)
4277 #define TF2_VECTOR 7 // 0x3B (Timer 2)
4280 #ifdef MICROCONTROLLER_SAB80515
4281 #define TF2_VECTOR 5 // 0x2B timer 2
4282 #define EX2_VECTOR 5 // 0x2B external interrupt 2
4283 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt
4284 #define IEX2_VECTOR 9 // 0x4B external interrupt 2
4285 #define IEX3_VECTOR 10 // 0x53 external interrupt 3
4286 #define IEX4_VECTOR 11 // 0x5B external interrupt 4
4287 #define IEX5_VECTOR 12 // 0x63 external interrupt 5
4288 #define IEX6_VECTOR 13 // 0x6B external interrupt 6
4291 #ifdef MICROCONTROLLER_SAB80515A
4292 #define TF2_VECTOR 5 // 0x2B timer 2
4293 #define EX2_VECTOR 5 // 0x2B external interrupt 2
4294 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt
4295 #define IEX2_VECTOR 9 // 0x4B external interrupt 2
4296 #define IEX3_VECTOR 10 // 0x53 external interrupt 3
4297 #define IEX4_VECTOR 11 // 0x5B external interrupt 4
4298 #define IEX5_VECTOR 12 // 0x63 external interrupt 5
4299 #define IEX6_VECTOR 13 // 0x6B external interrupt 6
4302 #ifdef MICROCONTROLLER_SAB80517
4303 #define TF2_VECTOR 5 // 0x2B timer 2
4304 #define EX2_VECTOR 5 // 0x2B external interrupt 2
4305 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt
4306 #define IEX2_VECTOR 9 // 0x4B external interrupt 2
4307 #define IEX3_VECTOR 10 // 0x53 external interrupt 3
4308 #define IEX4_VECTOR 11 // 0x5B external interrupt 4
4309 #define IEX5_VECTOR 12 // 0x63 external interrupt 5
4310 #define IEX6_VECTOR 13 // 0x6B external interrupt 6
4313 #define SI1_VECTOR 16 // 0x83 serial port 1
4316 #define COMPARE_VECTOR 19 // 0x9B compare
4319 #ifdef MICROCONTORLLER_T89C51RD2
4320 #define TF2_VECTOR 5 /* 0x2B timer 2 */
4321 #define PCA_VECTOR 6 /* 0x33 Programmable Counter Array interrupt */
4322 #endif /* MICROCONTORLLER_T89C51RD2 */
4324 #endif // End of the header -> #ifndef MCS51REG_H