1 /*-------------------------------------------------------------------------
2 Register Declarations for the mcs51 compatible microcontrollers
4 Written By - Bela Torok / bela.torok@kssg.ch (November 2000)
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the
8 Free Software Foundation; either version 2, or (at your option) any
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 In other words, you are welcome to use, share and improve this program.
21 You are forbidden to forbid anyone else to use, share and improve
22 what you give them. Help stamp out software-hoarding!
27 Version 1.0 Nov 2, 2000 - B. Torok / bela.torok@kssg.ch
28 Initial release, supported microcontrollers:
29 8051, 8052, Atmel AT89C1051, AT89C2051, AT89C4051,
30 Infineon / Siemens SAB80515, SAB80535, SAB80515A
32 Version 1.0.1 (Nov 3, 2000)
33 SAB80515A definitions revised by Michael Schmitt / michael.schmitt@t-online.de
35 Version 1.0.2 (Nov 6, 2000)
36 T2CON bug corrected 8052 and SABX microcontrollers have different T2CONs
37 Support for the Atmel AT89C52, AT80LV52, AT89C55, AT80LV55
38 Support for the Dallas DS80C320 and DS80C323
39 B. Torok / bela.torok@kssg.ch
41 Version 1.0.3 (Nov 7, 2000)
42 SAB80517 definitions added by Michael Schmitt / michael.schmitt@t-online.de
43 Dallas AT89S53 definitions added by B. Torok / bela.torok@kssg.ch
44 Dallas DS87C520 and DS83C520 definitions added by B. Torok / bela.torok@kssg.ch
46 Version 1.0.4 (Nov 9, 2000)
47 To simplify the identication of registers, a large number of definitios
48 were renamed. Long register names now (hopefully) clearly define the
49 function of the registers.
50 Dallas DS89C420 definitions added by B. Torok / bela.torok@kssg.ch
52 Version 1.0.5 (Dec 15, 2000)
53 Definitions added: #ifdef MCS51REG_EXTERNAL_ROM
54 #ifdef MCS51REG_EXTERNAL_RAM
55 #ifdef MCS51REG_DISABLE_WARNINGS
58 Version 1.0.6 (March 10, 2001)
59 Support for the Dallas DS5000 & DS2250
60 Support for the Dallas DS5001 & DS2251
61 microcontrollers - B. Torok / bela.torok@kssg.ch
63 Adding support for additional microcontrollers:
64 -----------------------------------------------
66 1. Don't modify this file!!!
68 2. Insert your code in a separate file e.g.: mcs51reg_update.h and include
69 this after the #define HEADER_MCS51REG statement in this file
71 3. The mcs51reg_update.h file should contain following definitions:
73 a. An entry with the inventory of the register set of the
74 microcontroller in the "Describe microcontrollers" section.
76 b. If necessary add entry(s) in for registers not defined in this file
78 c. Define interrupt vectors
80 4. Send me the file mcs51reg_update.h ( bela.torok@kssg.ch ).
81 I'm going to verify/merge new definitions to this file.
84 Microcontroller support:
86 Use one of the following options:
88 1. use #include <mcs51reg.h> in your program & define MICROCONTROLLER_XXXX in your makefile.
90 2. use following definitions prior the
91 #include <mcs51reg.h> line in your program:
93 #define MICROCONTROLLER_8052 -> 8052 type microcontroller
95 #define MICROCONTROLLER_AT89CX051 -> Atmel AT89C1051, AT89C2051 and AT89C4051 microcontrollers
98 Use only one of the following definitions!!!
100 Supported Microcontrollers:
103 MICROCONTROLLER_8051 8051
104 MICROCONTROLLER_8052 8052
105 MICROCONTROLLER_AT89CX051 Atmel AT89C1051, AT89C2051 and AT89C4051
106 MICROCONTROLLER_AT89S53 Atmel AT89S53 microcontroller
107 MICROCONTROLLER_AT89X52 Atmel AT89C52 and AT80LV52 microcontrollers
108 MICROCONTROLLER_AT89X55 Atmel AT89C55 and AT80LV55 microcontrollers
109 MICROCONTROLLER_DS5000 Dallas DS5000 & DS2250 microcontroller
110 MICROCONTROLLER_DS5001 Dallas DS5001 & DS2251 microcontroller
111 MICROCONTROLLER_DS80C32X Dallas DS80C320 and DS80C323 microcontrollers
112 MICROCONTROLLER_DS89C420 Dallas DS89C420 microcontroller
113 MICROCONTROLLER_DS8XC520 Dallas DS87C520 and DS83C520 microcontrollers
114 MICROCONTROLLER_SAB80515 Infineon / Siemens SAB80515 & SAB80535
115 MICROCONTROLLER_SAB80515A Infineon / Siemens SAB80515A
116 MICROCONTROLLER_SAB80517 Infineon / Siemens SAB80517
118 Additional definitions (use them prior the #include mcs51reg.h statement):
120 Ports P0 & P2 are not available for the programmer if external ROM used.
121 Use statement "#define MCS51REG_EXTERNAL_RAM" to undefine P0 & P2.
123 Ports P0, P2, P3_6, WR, P3_7 & RD are not available for the programmer if
124 external RAM is used.
125 Use statement "#define MCS51REG_EXTERNAL_RAM" to undefine P0, P2,
128 #define MCS51REG_DISABLE_WARNINGS -> disables warnings
130 -----------------------------------------------------------------------*/
133 #ifndef HEADER_MCS51REG
134 #define HEADER_MCS51REG
136 ///////////////////////////////////////////////////////
137 /// Insert header here (for developers only) ///
138 /// remove "//" from the begining of the next line ///
139 //#include "mcs51reg_update.h" ///
140 ///////////////////////////////////////////////////////
142 //////////////////////////////////
143 /// Describe microcontrollers ///
144 /// (inventory of registers) ///
145 //////////////////////////////////
147 // definitions for the 8051
148 #ifdef MICROCONTROLLER_8051
149 #ifdef MICROCONTROLLER_DEFINED
150 #define MCS51REG_ERROR
152 #ifndef MICROCONTROLLER_DEFINED
153 #define MICROCONTROLLER_DEFINED
155 #ifndef MCS51REG_DISABLE_WARNINGS
156 #warning Selected HW: 8051
162 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
173 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
175 #define IP__x__x__x__PS__PT1__PX1__PT0__PX0
180 // end of definitions for the 8051
183 // definitions for the 8052 microcontroller
184 #ifdef MICROCONTROLLER_8052
185 #ifdef MICROCONTROLLER_DEFINED
186 #define MCS51REG_ERROR
188 #ifndef MICROCONTROLLER_DEFINED
189 #define MICROCONTROLLER_DEFINED
191 #ifndef MCS51REG_DISABLE_WARNINGS
192 #warning Selected HW: 8052
199 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
210 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
212 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
216 // 8052 specific registers
217 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
223 // end of definitions for the 8052 microcontroller
226 // definitionsons for the Atmel
227 // AT89C1051, AT89C2051 and AT89C4051 microcontrollers
228 #ifdef MICROCONTROLLER_AT89CX051
229 #ifdef MICROCONTROLLER_DEFINED
230 #define MCS51REG_ERROR
232 #ifndef MICROCONTROLLER_DEFINED
233 #define MICROCONTROLLER_DEFINED
235 #ifndef MCS51REG_DISABLE_WARNINGS
236 #warning Selected HW: Atmel AT89Cx051
238 // 8051 register set without P0 & P2
242 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
252 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
254 #define IP__x__x__x__PS__PT1__PX1__PT0__PX0
259 // end of definitionsons for the Atmel
260 // AT89C1051, AT89C2051 and AT89C4051 microcontrollers
263 // definitions for the Atmel AT89S53
264 #ifdef MICROCONTROLLER_AT89S53
265 #ifdef MICROCONTROLLER_DEFINED
266 #define MCS51REG_ERROR
268 #ifndef MICROCONTROLLER_DEFINED
269 #define MICROCONTROLLER_DEFINED
271 #ifndef MCS51REG_DISABLE_WARNINGS
272 #warning Selected HW: AT89S53
279 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
290 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
292 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
296 // 8052 specific registers
297 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
302 // AT89S53 specific register
304 #define P1_EXT__x__x__x__x__x__x__T2EX__T2
312 // end of definitions for the Atmel AT89S53 microcontroller
315 // definitions for the Atmel AT89C52 and AT89LV52 microcontrollers
316 #ifdef MICROCONTROLLER_AT89X52
317 #ifdef MICROCONTROLLER_DEFINED
318 #define MCS51REG_ERROR
320 #ifndef MICROCONTROLLER_DEFINED
321 #define MICROCONTROLLER_DEFINED
323 #ifndef MCS51REG_DISABLE_WARNINGS
324 #warning Selected HW: AT89C52 or AT89LV52
331 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
342 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
344 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
348 // 8052 specific registers
349 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
354 // AT89X55 specific register
356 #define P1_EXT__x__x__x__x__x__x__T2EX__T2
358 // end of definitions for the Atmel AT89C52 and AT89LV52 microcontrollers
361 // definitions for the Atmel AT89C55 and AT89LV55 microcontrollers
362 #ifdef MICROCONTROLLER_AT89X55
363 #ifdef MICROCONTROLLER_DEFINED
364 #define MCS51REG_ERROR
366 #ifndef MICROCONTROLLER_DEFINED
367 #define MICROCONTROLLER_DEFINED
369 #ifndef MCS51REG_DISABLE_WARNINGS
370 #warning Selected HW: AT89C55 or AT89LV55
377 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
388 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
390 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
394 // 8052 specific registers
395 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
400 // AT89X55 specific register
402 #define P1_EXT__x__x__x__x__x__x__T2EX__T2
404 // end of definitions for the Atmel AT89C55 and AT89LV55 microcontrollers
407 // definitions for the Dallas DS5000
408 #ifdef MICROCONTROLLER_DS5000
409 #ifdef MICROCONTROLLER_DEFINED
410 #define MCS51REG_ERROR
412 #ifndef MICROCONTROLLER_DEFINED
413 #define MICROCONTROLLER_DEFINED
415 #ifndef MCS51REG_DISABLE_WARNINGS
416 #warning Selected HW: 8051
422 #define PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
433 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
435 #define IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
436 #define MCON__SL__PAA__ECE2__RA32_8__PA0__PA1__PA2__PA3
442 // end of definitions for the Dallas DS5000
445 // definitions for the Dallas DS5001
446 #ifdef MICROCONTROLLER_DS5001
447 #ifdef MICROCONTROLLER_DEFINED
448 #define MCS51REG_ERROR
450 #ifndef MICROCONTROLLER_DEFINED
451 #define MICROCONTROLLER_DEFINED
453 #ifndef MCS51REG_DISABLE_WARNINGS
454 #warning Selected HW: 8051
460 #define PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
471 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
473 #define IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
477 #define MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL
482 #define STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF
486 // end of definitions for the Dallas DS5001
489 // definitions for the Dallas DS80C320 and DS80C323 microcontrollers
490 #ifdef MICROCONTROLLER_DS80C32X
491 #ifdef MICROCONTROLLER_DEFINED
492 #define MCS51REG_ERROR
494 #ifndef MICROCONTROLLER_DEFINED
495 #define MICROCONTROLLER_DEFINED
497 #ifndef MCS51REG_DISABLE_WARNINGS
498 #warning Selected HW: Dallas DS80C320 or DS80C323
505 #define PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
516 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
518 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
522 // 8052 specific registers
523 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
528 // DS80C320 specific register
531 #define DPS__x__x__x__x__x__x__x__SEL
533 #define EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
540 #define STATUS__PIP__HIP__LIP__x__x__x__x__x
543 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
548 // end of definitions for the Dallas DS80C320 and DS80C323 microcontrollers
551 // definitions for the Dallas DS89C420 microcontroller
552 #ifdef MICROCONTROLLER_DS89C420
553 #ifdef MICROCONTROLLER_DEFINED
554 #define MCS51REG_ERROR
556 #ifndef MICROCONTROLLER_DEFINED
557 #define MICROCONTROLLER_DEFINED
559 #ifndef MCS51REG_DISABLE_WARNINGS
560 #warning Selected HW: Dallas DS89C420
567 #define PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
578 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
580 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
584 // 8052 specific registers
585 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
590 // DS8XC520 specific registers
594 #define DPS__ID1__ID0__TSL__AID__x__x__x__SEL
597 #define IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
598 #define IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
599 #define EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
607 #define STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
610 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
612 #define ROMSIZE__HBPF__BPF__TE__MOVCX__PRAME__RMS2__RMS1__RMS0
617 // end of definitions for the Dallas DS89C420 microcontroller
620 // definitions for the Dallas DS87C520 and DS83C520 microcontrollers
621 #ifdef MICROCONTROLLER_DS8XC520
622 #ifdef MICROCONTROLLER_DEFINED
623 #define MCS51REG_ERROR
625 #ifndef MICROCONTROLLER_DEFINED
626 #define MICROCONTROLLER_DEFINED
628 #ifndef MCS51REG_DISABLE_WARNINGS
629 #warning Selected HW: Dallas DS87C520 or DS85C520
636 #define PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
647 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
649 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
653 // 8052 specific registers
654 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
659 // DS8XC520 specific registers
662 #define DPS__x__x__x__x__x__x__x__SEL
664 #define EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
672 #define STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
675 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
677 #define ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0
683 // end of definitions for the Dallas DS87C520 and DS83C520 microcontrollers
686 // definitions for the Infineon / Siemens SAB80515 & SAB80535
687 #ifdef MICROCONTROLLER_SAB80515
688 #ifdef MICROCONTROLLER_DEFINED
689 #define MCS51REG_ERROR
691 #ifndef MICROCONTROLLER_DEFINED
692 #define MICROCONTROLLER_DEFINED
694 #ifndef MCS51REG_DISABLE_WARNINGS
695 #warning Selected HW: Infineon / Siemens SAB80515 & SAB80535
697 // 8051 register set without IP
702 #define PCON__SMOD__x__x__x__x__x__x__x
713 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
718 // SAB80515 specific registers
719 #define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
720 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
730 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
737 #define DAPR__SAB80515
741 // end of definitions for the Infineon / Siemens SAB80515
744 // definitions for the Infineon / Siemens SAB80515A
745 #ifdef MICROCONTROLLER_SAB80515A
746 #ifdef MICROCONTROLLER_DEFINED
747 #define MCS51REG_ERROR
749 #ifndef MICROCONTROLLER_DEFINED
750 #define MICROCONTROLLER_DEFINED
752 #ifndef MCS51REG_DISABLE_WARNINGS
753 #warning Selected HW: Infineon / Siemens SAB80515A
755 // 8051 register set without IP
760 #define PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
771 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
776 // SAB80515A specific registers
777 #define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
778 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
779 #define IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
789 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
806 // end of definitions for the Infineon / Siemens SAB80515A
809 // definitions for the Infineon / Siemens SAB80517
810 #ifdef MICROCONTROLLER_SAB80517
811 #ifdef MICROCONTROLLER_DEFINED
812 #define MCS51REG_ERROR
814 #ifndef MICROCONTROLLER_DEFINED
815 #define MICROCONTROLLER_DEFINED
817 #ifndef MCS51REG_DISABLE_WARNINGS
818 #warning Selected HW: Infineon / Siemens SAB80517
820 // 8051 register set without IP, SCON & SBUF
825 #define PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
836 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
841 // SAB80517 specific registers
842 #define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
843 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
844 #define IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
846 #define IEN2__SAB80517
876 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
887 #define DAPR__SAB80517
913 // end of definitions for the Infineon / Siemens SAB80517
916 /////////////////////////////////////////////////////////
917 /// don't specify microcontrollers below this line! ///
918 /////////////////////////////////////////////////////////
921 // default microcontroller -> 8051
922 // use default if no microcontroller specified
923 #ifndef MICROCONTROLLER_DEFINED
924 #define MICROCONTROLLER_DEFINED
925 #ifndef MCS51REG_DISABLE_WARNINGS
926 #warning //////////////////////////////////
927 #warning // No microcontroller defined! //
928 #warning //////////////////////////////////
929 #warning Code will be generated for the
930 #warning 8051 (default) microcontroller.
931 #warning If you have another microcontroller
932 #warning define it in the makefile, or in the
933 #warning "C" source prior
934 #warning the #include <mcs51reg.h> statement.
935 #warning If you use a non supported
936 #warning microcontroller, mcs51reg.h can be
937 #warning easily extended to support your HW.
944 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
955 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
957 #define IP__x__x__x__PS__PT1__PX1__PT0__PX0
962 // end of definitions for the default microcontroller
965 #ifdef MCS51REG_ERROR
966 #error Two or more microcontrollers defined!
969 #ifdef MCS51REG_EXTERNAL_ROM
970 #ifndef MCS51REG_UNDEFINE_P0
971 #define MCS51REG_UNDEFINE_P0
973 #ifndef MCS51REG_UNDEFINE_P2
974 #define MCS51REG_UNDEFINE_P2
978 #ifdef MCS51REG_EXTERNAL_RAM
979 #ifndef MCS51REG_UNDEFINE_P0
980 #define MCS51REG_UNDEFINE_P0
982 #ifndef MCS51REG_UNDEFINE_P2
983 #define MCS51REG_UNDEFINE_P2
987 #ifdef MCS51REG_UNDEFINE_P0
991 #ifdef MCS51REG_UNDEFINE_P2
995 ////////////////////////////////
996 /// Register definitions ///
997 /// (In alphabetical order) ///
998 ////////////////////////////////
1007 sfr at 0x9D ACON ; // DS89C420 specific
1016 sfr at 0xD8 ADCON ; // A/D-converter control register SAB80515 specific
1027 // ADCON0 ... Infineon / Siemens also called this register ADCON in the User Manual
1030 sfr at 0xD8 ADCON0 ; // A/D-converter control register 0 SAB80515A &
1031 // Bit registers // SAB80517 specific
1040 // Not directly accessible ADCON0
1041 #define ADCON0_MX0 0x01
1042 #define ADCON0_MX1 0x02
1043 #define ADCON0_MX2 0x04
1044 #define ADCON0_ADM 0x08
1045 #define ADCON0_BSY 0x10
1046 #define ADCON0_ADEX 0x20
1047 #define ADCON0_CLK 0x40
1048 #define ADCON0_BD 0x80
1053 sfr at 0xDC ADCON1 ; // A/D-converter control register 1 SAB80515A & SAB80517 specific
1054 // Not directly accessible ADCON1
1055 #define ADCON1_MX0 0x01
1056 #define ADCON1_MX1 0x02
1057 #define ADCON1_MX2 0x04
1058 #define ADCON1_ADCL 0x80
1063 sfr at 0xD9 ADDAT ; // A/D-converter data register SAB80515 specific
1068 sfr at 0xD9 ADDATH ; // A/D data high byte SAB80515A specific
1073 sfr at 0xDA ADDATL ; // A/D data low byte SAB80515A specific
1078 sfr at 0xEF ARCON ; // arithmetic control register SAB80517
1085 sbit at 0xF0 BREG_F0 ;
1086 sbit at 0xF1 BREG_F1 ;
1087 sbit at 0xF2 BREG_F2 ;
1088 sbit at 0xF3 BREG_F3 ;
1089 sbit at 0xF4 BREG_F4 ;
1090 sbit at 0xF5 BREG_F5 ;
1091 sbit at 0xF6 BREG_F6 ;
1092 sbit at 0xF7 BREG_F7 ;
1098 // Not directly accessible bits
1109 sfr at 0xC9 CC4EN ; // compare/capture 4 enable register SAB80517 specific
1114 sfr at 0xC1 CCEN ; // compare/capture enable register SAB80515 specific
1119 sfr at 0xC3 CCH1 ; // compare/capture register 1, high byte SAB80515 specific
1124 sfr at 0xC5 CCH2 ; // compare/capture register 2, high byte SAB80515 specific
1129 sfr at 0xC7 CCH3 ; // compare/capture register 3, high byte SAB80515 specific
1134 sfr at 0xCF CCH4 ; // compare/capture register 4, high byte SAB80515 specific
1139 sfr at 0xC2 CCL1 ; // compare/capture register 1, low byte SAB80515 specific
1144 sfr at 0xC4 CCL2 ; // compare/capture register 2, low byte SAB80515 specific
1149 sfr at 0xC6 CCL3 ; // compare/capture register 3, low byte SAB80515 specific
1154 sfr at 0xCE CCL4 ; // compare/capture register 4, low byte SAB80515 specific
1159 sfr at 0x8E CKCON ; // DS80C320 specific
1160 // Not directly accessible Bits. DS80C320 specific
1173 sfr at 0x96 CKMOD ; // DS89C420 specific
1174 // Not directly accessible Bits.
1182 sfr at 0xF6 CMEN ; // compare enable register SAB80517 specific
1187 sfr at 0xD3 CMH0 ; // compare register 0 high byte SAB80517 specific
1192 sfr at 0xD5 CMH1 ; // compare register 1 high byte SAB80517 specific
1197 sfr at 0xD7 CMH2 ; // compare register 2 high byte SAB80517 specific
1202 sfr at 0xE3 CMH3 ; // compare register 3 high byte SAB80517 specific
1207 sfr at 0xE5 CMH4 ; // compare register 4 high byte SAB80517 specific
1212 sfr at 0xE7 CMH5 ; // compare register 5 high byte SAB80517 specific
1217 sfr at 0xF3 CMH6 ; // compare register 6 high byte SAB80517 specific
1222 sfr at 0xF5 CMH7 ; // compare register 7 high byte SAB80517 specific
1227 sfr at 0xD2 CML0 ; // compare register 0 low byte SAB80517 specific
1232 sfr at 0xD4 CML1 ; // compare register 1 low byte SAB80517 specific
1237 sfr at 0xD6 CML2 ; // compare register 2 low byte SAB80517 specific
1242 sfr at 0xE2 CML3 ; // compare register 3 low byte SAB80517 specific
1247 sfr at 0xE4 CML4 ; // compare register 4 low byte SAB80517 specific
1252 sfr at 0xE6 CML5 ; // compare register 5 low byte SAB80517 specific
1257 sfr at 0xF2 CML6 ; // compare register 6 low byte SAB80517 specific
1262 sfr at 0xF4 CML7 ; // compare register 7 low byte SAB80517 specific
1267 sfr at 0xF7 CMSEL ; // compare input select SAB80517
1272 sfr at 0xC1 CRC ; // Dallas DS5001 specific
1283 sfr at 0xCB CRCH ; // compare/reload/capture register, high byte SAB80515 specific
1288 sfr at 0xC3 CRCHIGH ; // DS5001 specific
1293 sfr at 0xCA CRCL ; // compare/reload/capture register, low byte SAB80515 specific
1298 sfr at 0xC2 CRCLOW ; // DS5001 specific
1303 sfr at 0xE1 CTCON ; // com.timer control register SAB80517
1308 sfr at 0xDF CTRELH ; // com.timer rel register high byte SAB80517
1313 sfr at 0xDE CTRELL ; // com.timer rel register low byte SAB80517
1316 #ifdef DAPR__SAB80515
1317 #undef DAPR__SAB80515
1318 sfr at 0xD8 DAPR ; // D/A-converter program register SAB80515 specific
1321 #ifdef DAPR__SAB80517
1322 #undef DAPR__SAB80517
1323 sfr at 0xDA DAPR ; // D/A-converter program register SAB80517 specific
1329 sfr at 0x83 DP0H ; // Alternate name for AT89S53
1334 sfr at 0x85 DPH1 ; // DS80C320 specific
1335 sfr at 0x85 DP1H ; // Alternate name for AT89S53
1340 sfr at 0x82 DPL ; // Alternate name for AT89S53
1346 sfr at 0x84 DPL1 ; // DS80C320 specific
1347 sfr at 0x84 DP1L ; // Alternate name for AT89S53
1350 #ifdef DPS__x__x__x__x__x__x__x__SEL
1351 #undef DPS__x__x__x__x__x__x__x__SEL
1353 // Not directly accessible DPS Bit. DS80C320 & DPS8XC520 specific
1357 #ifdef DPS__ID1__ID0__TSL__AID__x__x__x__SEL
1358 #undef DPS__ID1__ID0__TSL__AID__x__x__x__SEL
1360 // Not directly accessible DPS Bit. DS89C420 specific
1370 sfr at 0x92 DPSEL ; // data pointer select register SAB80517
1376 // Bit registers DS80C320 specific
1387 // Bit registers DS80C320 specific
1395 #ifdef EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
1396 #undef EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
1398 // Not directly accessible EXIF Bits DS80C320 specific
1408 #ifdef EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
1409 #undef EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
1411 // Not directly accessible EXIF Bits DS87C520 specific
1422 #ifdef EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
1423 #undef EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
1425 // Not directly accessible EXIF Bits DS89C420 specific
1436 #ifdef IE__EA__x__x__ES__ET1__EX1__ET0__EX0
1437 #undef IE__EA__x__x__ES__ET1__EX1__ET0__EX0
1448 #ifdef IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
1449 #undef IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
1457 sbit at 0xAD ET2 ; // Enable timer2 interrupt
1461 #ifdef IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
1462 #undef IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
1470 sbit at 0xAC ES0 ; // Alternate name
1471 sbit at 0xAD ET2 ; // Enable timer2 interrupt
1476 #ifdef IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
1477 #undef IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
1479 sfr at 0xA8 IEN0 ; // Alternate name
1480 // Bit registers for the SAB80515 and compatible IE
1487 sbit at 0xAD ET2 ; // Enable timer 2 overflow SAB80515 specific
1488 sbit at 0xAE WDT ; // watchdog timer reset - SAB80515 specific
1490 sbit at 0xAF EAL ; // EA as called by Infineon / Siemens
1495 sfr at 0xB8 IEN1 ; // interrupt enable register - SAB80515 specific
1497 sbit at 0xB8 EADC ; // A/D converter interrupt enable
1503 sbit at 0xBE SWDT ; // watchdog timer start/reset
1504 sbit at 0xBF EXEN2 ; // timer2 external reload interrupt enable
1507 #ifdef IEN2__SAB80517
1508 #undef IEN2__SAB80517
1509 sfr at 0x9A IEN2 ; // interrupt enable register 2 SAB80517
1512 #ifdef IP__x__x__x__PS__PT1__PX1__PT0__PX0
1513 #undef IP__x__x__x__PS__PT1__PX1__PT0__PX0
1523 #ifdef IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
1524 #undef IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
1535 #ifdef IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
1536 #undef IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
1548 #ifdef IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
1549 #undef IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
1560 #ifdef IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
1561 #undef IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
1562 sfr at 0xA9 IP0 ; // interrupt priority register SAB80515 specific
1563 // Not directly accessible IP0 bits
1573 #ifdef IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
1574 #undef IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
1575 sfr at 0xB8 IP0 ; // interrupt priority register DS89C420 specific
1576 // Not directly accessible IP0 bits
1586 #ifdef IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
1587 #undef IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
1588 sfr at 0xB9 IP1 ; // interrupt priority register SAB80515 specific
1589 // Not directly accessible IP1 bits
1598 #ifdef IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
1599 #undef IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
1600 sfr at 0xB1 IP1 ; // interrupt priority register DS89C420 specific
1601 // Not directly accessible IP0 bits
1613 sfr at 0xC0 IRCON ; // interrupt control register - SAB80515 specific
1615 sbit at 0xC0 IADC ; // A/D converter irq flag
1616 sbit at 0xC1 IEX2 ; // external interrupt edge detect flag
1621 sbit at 0xC6 TF2 ; // timer 2 owerflow flag
1622 sbit at 0xC7 EXF2 ; // timer2 reload flag
1627 sfr at 0xC0 IRCON0 ; // interrupt control register - SAB80515 specific
1629 sbit at 0xC0 IADC ; // A/D converter irq flag
1630 sbit at 0xC1 IEX2 ; // external interrupt edge detect flag
1635 sbit at 0xC6 TF2 ; // timer 2 owerflow flag
1636 sbit at 0xC7 EXF2 ; // timer2 reload flag
1641 sfr at 0xD1 IRCON1 ; // interrupt control register - SAB80515 specific
1644 #ifdef MCON__PA3__PA2__PA1__PA0__RA32_8__ECE2__PAA__SL
1645 #undef MCON__PA3__PA2__PA1__PA0__RA32_8__ECE2__PAA__SL
1646 sfr at 0xC6 MCON ; // DS5000
1657 #ifdef MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL
1658 #undef MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL
1659 sfr at 0xC6 MCON ; // DS5001
1672 sfr at 0xE9 MD0 ; // MUL / DIV register 0 SAB80517
1677 sfr at 0xEA MD1 ; // MUL / DIV register 1 SAB80517
1682 sfr at 0xEB MD2 ; // MUL / DIV register 2 SAB80517
1687 sfr at 0xEC MD3 ; // MUL / DIV register 3 SAB80517
1692 sfr at 0xED MD4 ; // MUL / DIV register 4 SAB80517
1697 sfr at 0xEE MD5 ; // MUL / DIV register 5 SAB80517
1728 #ifdef P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
1729 #undef P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
1730 // P1 alternate functions
1741 #ifdef P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
1742 sbit at 0x90 INT3_CC0 ; // P1 alternate functions - SAB80515 specific
1743 sbit at 0x91 INT4_CC1 ;
1744 sbit at 0x92 INT5_CC2 ;
1745 sbit at 0x93 INT6_CC3 ;
1748 sbit at 0x96 CLKOUT ;
1752 #ifdef P1_EXT__x__x__x__x__x__x__T2EX__T2
1753 #undef P1_EXT__x__x__x__x__x__x__T2EX__T2
1754 // P1 alternate functions
1783 #ifndef MCS51REG_EXTERNAL_RAM
1794 #ifndef MCS51REG_EXTERNAL_RAM
1802 sfr at 0xE8 P4 ; // Port 4 - SAB80515 & compatible microcontrollers
1816 sfr at 0xF8 P5 ; // Port 5 - SAB80515 & compatible microcontrollers
1830 sfr at 0xDB P6 ; // Port 6 - SAB80515 & compatible microcontrollers
1835 sfr at 0xFA P6 ; // Port 6 - SAB80517 specific
1840 sfr at 0xDB P7 ; // Port 7 - SAB80517 specific
1845 sfr at 0xDD P8 ; // Port 6 - SAB80517 specific
1848 #ifdef PCON__SMOD__x__x__x__x__x__x__x
1849 #undef PCON__SMOD__x__x__x__x__x__x__x
1851 // Not directly accessible PCON bits
1855 #ifdef PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
1856 #undef PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
1858 // Not directly accessible PCON bits
1866 #ifdef PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
1867 #undef PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
1869 // Not directly accessible PCON bits
1871 #define IDLE 0x01 ; same as IDL
1873 #define PDE 0x02 ; same as PD
1878 #define PCON_IDLE 0x01
1879 #define PCON_PDE 0x02
1880 #define PCON_GF0 0x04
1881 #define PCON_GF1 0x08
1882 #define PCON_IDLS 0x20
1883 #define PCON_PDS 0x40
1884 #define PCON_SMOD 0x80
1887 #ifdef PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
1888 #undef PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
1890 // Not directly accessible PCON bits
1892 #define IDLE 0x01 ; same as IDL
1902 #ifdef PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
1903 #undef PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
1905 // Not directly accessible PCON bits
1907 #define IDLE 0x01 ; same as IDL
1915 #ifdef PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
1916 #undef PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
1918 // Not directly accessible PCON bits
1920 #define IDLE 0x01 ; same as IDL
1932 sfr at 0xC4 PMR ; // DS87C520, DS83C520
1933 // Not directly accessible bits
1959 sfr at 0xCB RCAP2H ;
1964 sfr at 0xCA RCAP2L ;
1972 #ifdef ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0
1973 #undef ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0
1974 sfr at 0xC2 ROMSIZE ; // DS87C520, DS83C520
1975 // Not directly accessible bits
1981 #ifdef ROMSIZE__HBPF__BPF__TE__MOVCX__PRAME__RMS2__RMS1__RMS0
1982 #undef ROMSIZE__HBPF__BPF__TE__MOVCX__PRAME__RMS2__RMS1__RMS0
1983 sfr at 0xC2 ROMSIZE ; // DS87C520, DS83C520
1984 // Not directly accessible bits
1997 sfr at 0xD8 RPCTL ; // Dallas DS5001 specific
1999 sbit at 0xD9 RPCON ;
2004 sbit at 0xDF RNR_FLAG ;
2009 sfr at 0x99 S0BUF ; // serial channel 0 buffer register SAB80517 specific
2014 sfr at 0x98 S0CON ; // serial channel 0 control register SAB80517 specific
2016 sbit at 0x98 RI0 ; // S0CON.0: receiver0 interrupt flag
2017 sbit at 0x99 TI0 ; // S0CON.1: transmitter0 interrupt flag
2018 sbit at 0x9A RB80 ; // S0CON.2: receiver0 bit8
2019 sbit at 0x9B TB80 ; // S0CON.3: transmitter0 bit 8
2020 sbit at 0x9C REN0 ; // S0CON.4: receiver0 enable
2021 sbit at 0x9D SM20 ; // S0CON.5: multiprocessor feature
2022 sbit at 0x9E SM1 ; // S0CON.6: | select serial mode
2023 sbit at 0x9F SM0 ; // S0CON.7: |
2028 sfr at 0xAA S0RELL ; // serial channel 0 reload register low byte SAB80517 specific
2033 sfr at 0xBA S0RELH ; // serial channel 0 reload register high byte SAB80517 specific
2038 sfr at 0x9C S1BUF ; // serial channel 1 buffer register SAB80517 specific
2043 sfr at 0x9B S1CON ; // serial channel 1 control register SAB80517 specific
2048 sfr at 0x9D S1RELL ; // serial channel 1 reload register low byte SAB80517 specific
2053 sfr at 0xBB S1RELH ; // serial channel 1 reload register high byte SAB80517 specific
2058 // DS80C320 specific
2059 sfr at 0xA9 SADDR0 ;
2064 // DS80C320 specific
2065 sfr at 0xAA SADDR1 ;
2070 // DS80C320 specific
2071 sfr at 0xB9 SADEN0 ;
2076 // DS80C320 specific
2077 sfr at 0xBA SADEN1 ;
2087 // DS80C320 specific
2107 // DS80C320 specific
2112 sbit at 0xCA RB8_1 ;
2113 sbit at 0xCB TB8_1 ;
2114 sbit at 0xCC REN_1 ;
2115 sbit at 0xCD SM2_1 ;
2116 sbit at 0xCE SM1_1 ;
2117 sbit at 0xCF SM0_1 ;
2119 sbit at 0xCF SM0_FE_1 ;
2129 sfr at 0xD5 SPCR ; // AT89S53 specific
2130 // Not directly accesible bits
2143 sfr at 0x86 SPDR ; // AT89S53 specific
2144 // Not directly accesible bits
2157 sfr at 0xAA SPSR ; // AT89S53 specific
2158 // Not directly accesible bits
2165 sfr at 0xBA SRELH ; // Baudrate generator reload high
2170 sfr at 0xAA SRELL ; // Baudrate generator reload low
2173 #ifdef STATUS__PIP__HIP__LIP__x__x__x__x__x
2174 #undef STATUS__PIP__HIP__LIP__x__x__x__x__x
2175 // DS80C320 specific
2176 sfr at 0xC5 STATUS ;
2177 // Not directly accessible Bits. DS80C320 specific
2183 #ifdef STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
2184 #undef STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
2185 sfr at 0xC5 STATUS ; // DS87C520 & DS83520specific
2186 // Not directly accessible Bits.
2197 #ifdef STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF
2198 #undef STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF
2199 sfr at 0xDA STATUS ; // DS5001specific
2200 // Not directly accessible Bits.
2213 sfr at 0xB1 SYSCON ; // XRAM Controller Access Control
2215 #define SYSCON_XMAP0 0x01
2216 #define SYSCON_XMAP1 0x02
2217 #define SYSCON_RMAP 0x10
2218 #define SYSCON_EALE 0x20
2221 #ifdef T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
2222 #undef T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
2224 // Definitions for the 8052 compatible microcontrollers.
2226 sbit at 0xC8 CP_RL2 ;
2229 sbit at 0xCB EXEN2 ;
2235 sbit at 0xC8 T2CON_0 ;
2236 sbit at 0xC9 T2CON_1 ;
2237 sbit at 0xCA T2CON_2 ;
2238 sbit at 0xCB T2CON_3 ;
2239 sbit at 0xCC T2CON_4 ;
2240 sbit at 0xCD T2CON_5 ;
2241 sbit at 0xCE T2CON_6 ;
2242 sbit at 0xCF T2CON_7 ;
2245 #ifdef T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
2246 #undef T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
2248 // Definitions for the Infineon / Siemens SAB80515, SAB80515A, SAB80517
2259 sbit at 0xC8 T2CON_0 ;
2260 sbit at 0xC9 T2CON_1 ;
2261 sbit at 0xCA T2CON_2 ;
2262 sbit at 0xCB T2CON_3 ;
2263 sbit at 0xCC T2CON_4 ;
2264 sbit at 0xCD T2CON_5 ;
2265 sbit at 0xCE T2CON_6 ;
2266 sbit at 0xCF T2CON_7 ;
2271 // Definitions for the timer/counter 2 of the Atmel 89x52 microcontroller
2273 // Not not directly accessible T2MOD bits
2283 // DS500 & DS80C320 specific
2334 // Not directly accessible TMOD bits
2338 #define T0_GATE 0x08
2342 #define T1_GATE 0x80
2344 #define T0_MASK 0x0F
2345 #define T1_MASK 0xF0
2350 sfr at 0x96 WCON ; // AT89S53 specific
2351 // Not directly accesible bits
2362 // DS80C320 specific
2364 // Not directly accessible bits
2365 #define RWT 0x01 /* Timed-Access protected */
2366 #define EWT 0x02 /* Timed-Access protected */
2368 #define WDIF 0x08 /* Timed-Access protected */
2371 #define POR 0x40 /* Timed-Access protected */
2377 sfr at 0x86 WDTREL ; // Watchdof Timer reload register
2382 sfr at 0x91 XPAGE ; // Page Address Register for Extended On-Chip Ram - Infineon / Siemens SAB80515A specific
2386 /////////////////////////
2387 /// Interrupt vectors ///
2388 /////////////////////////
2390 // Interrupt numbers: address = (number * 8) + 3
2391 #define IE0_VECTOR 0 // 0x03 external interrupt 0
2392 #define TF0_VECTOR 1 // 0x0b timer 0
2393 #define IE1_VECTOR 2 // 0x13 external interrupt 1
2394 #define TF1_VECTOR 3 // 0x1b timer 1
2395 #define SI0_VECTOR 4 // 0x23 serial port 0
2397 #ifdef MICROCONTROLLER_AT89S53
2398 #define TF2_VECTOR 5 /* 0x2B timer 2 */
2399 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
2402 #ifdef MICROCONTROLLER_AT89X52
2403 #define TF2_VECTOR 5 /* 0x2B timer 2 */
2404 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
2407 #ifdef MICROCONTROLLER_AT89X55
2408 #define TF2_VECTOR 5 /* 0x2B timer 2 */
2409 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
2412 #ifdef MICROCONTROLLER_DS5000
2413 #define PFW_VECTOR 5 /* 0x2B */
2416 #ifdef MICROCONTROLLER_DS5001
2417 #define PFW_VECTOR 5 /* 0x2B */
2420 #ifdef MICROCONTROLLER_DS80C32X
2421 #define TF2_VECTOR 5 /* 0x2B */
2422 #define PFI_VECTOR 6 /* 0x33 */
2423 #define SIO1_VECTOR 7 /* 0x3B */
2424 #define IE2_VECTOR 8 /* 0x43 */
2425 #define IE3_VECTOR 9 /* 0x4B */
2426 #define IE4_VECTOR 10 /* 0x53 */
2427 #define IE5_VECTOR 11 /* 0x5B */
2428 #define WDI_VECTOR 12 /* 0x63 */
2431 #ifdef MICROCONTROLLER_DS8XC520
2432 #define TF2_VECTOR 5 /* 0x2B */
2433 #define PFI_VECTOR 6 /* 0x33 */
2434 #define SIO1_VECTOR 7 /* 0x3B */
2435 #define IE2_VECTOR 8 /* 0x43 */
2436 #define IE3_VECTOR 9 /* 0x4B */
2437 #define IE4_VECTOR 10 /* 0x53 */
2438 #define IE5_VECTOR 11 /* 0x5B */
2439 #define WDI_VECTOR 12 /* 0x63 */
2442 #ifdef MICROCONTROLLER_SAB80515
2443 #define TF2_VECTOR 5 // 0x2B timer 2
2444 #define EX2_VECTOR 5 // 0x2B external interrupt 2
2445 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt
2446 #define IEX2_VECTOR 9 // 0x4B external interrupt 2
2447 #define IEX3_VECTOR 10 // 0x53 external interrupt 3
2448 #define IEX4_VECTOR 11 // 0x5B external interrupt 4
2449 #define IEX5_VECTOR 12 // 0x63 external interrupt 5
2450 #define IEX6_VECTOR 13 // 0x6B external interrupt 6
2453 #ifdef MICROCONTROLLER_SAB80515A
2454 #define TF2_VECTOR 5 // 0x2B timer 2
2455 #define EX2_VECTOR 5 // 0x2B external interrupt 2
2456 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt
2457 #define IEX2_VECTOR 9 // 0x4B external interrupt 2
2458 #define IEX3_VECTOR 10 // 0x53 external interrupt 3
2459 #define IEX4_VECTOR 11 // 0x5B external interrupt 4
2460 #define IEX5_VECTOR 12 // 0x63 external interrupt 5
2461 #define IEX6_VECTOR 13 // 0x6B external interrupt 6
2464 #ifdef MICROCONTROLLER_SAB80517
2465 #define TF2_VECTOR 5 // 0x2B timer 2
2466 #define EX2_VECTOR 5 // 0x2B external interrupt 2
2467 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt
2468 #define IEX2_VECTOR 9 // 0x4B external interrupt 2
2469 #define IEX3_VECTOR 10 // 0x53 external interrupt 3
2470 #define IEX4_VECTOR 11 // 0x5B external interrupt 4
2471 #define IEX5_VECTOR 12 // 0x63 external interrupt 5
2472 #define IEX6_VECTOR 13 // 0x6B external interrupt 6
2475 #define SI1_VECTOR 16 // 0x83 serial port 1
2478 #define COMPARE_VECTOR 19 // 0x9B compare
2481 #endif // End of the header -> #ifndef MCS51REG_H