1 /*-------------------------------------------------------------------------
2 Register Declarations for the mcs51 compatible microcontrollers
4 Written By - Bela Torok / bela.torok@kssg.ch (November 2000)
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the
8 Free Software Foundation; either version 2, or (at your option) any
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 In other words, you are welcome to use, share and improve this program.
21 You are forbidden to forbid anyone else to use, share and improve
22 what you give them. Help stamp out software-hoarding!
27 Version 1.0 Nov 2, 2000 - B. Torok / bela.torok@kssg.ch
28 Initial release, supported microcontrollers:
29 8051, 8052, Atmel AT89C1051, AT89C2051, AT89C4051,
30 Infineon / Siemens SAB80515, SAB80535, SAB80515A
32 Version 1.0.1 (Nov 3, 2000)
33 SAB80515A definitions revised by Michael Schmitt / michael.schmitt@t-online.de
35 Version 1.0.2 (Nov 6, 2000)
36 T2CON bug corrected 8052 and SABX microcontrollers have different T2CONs
37 Support for the Atmel AT89C52, AT80LV52, AT89C55, AT80LV55
38 Support for the Dallas DS80C320 and DS80C323
39 B. Torok / bela.torok@kssg.ch
41 Version 1.0.3 (Nov 7, 2000)
42 SAB80517 definitions added by Michael Schmitt / michael.schmitt@t-online.de
43 Dallas AT89S53 definitions added by B. Torok / bela.torok@kssg.ch
44 Dallas DS87C520 and DS83C520 definitions added by B. Torok / bela.torok@kssg.ch
46 Version 1.0.4 (Nov 9, 2000)
47 To simplify the identication of registers, a large number of definitios
48 were renamed. Long register names now (hopefully) clearly define the
49 function of the registers.
50 Dallas DS89C420 definitions added by B. Torok / bela.torok@kssg.ch
52 Version 1.0.5 (Dec 15, 2000)
53 Definitions added: #ifdef MCS51REG_EXTERNAL_ROM
54 #ifdef MCS51REG_EXTERNAL_RAM
55 #ifndef MCS51REG_DISABLE_WARNINGS
58 Version 1.0.6 (March 10, 2001)
59 Support for the Dallas DS5000 & DS2250
60 Support for the Dallas DS5001 & DS2251
61 Support for the Dallas DS80C390
62 microcontrollers - B. Torok / bela.torok@kssg.ch
64 Version 1.0.7 (June 7, 2001)
65 #ifndef MCS51REG_DISABLE_WARNINGS removed
66 #ifdef MCS51REG_DISABLE_WARNINGS added - B. Torok / bela.torok@kssg.ch
67 Support for the Philips P80C552 added - Bernhard Held / Bernhard.Held@otelo-online.de
69 Version 1.0.8 (Feb 28, 2002)
70 Dallas DS89C420 definitions corrected by B. Torok / bela.torok@kssg.ch
71 Revised by lanius@ewetel.net
73 Version 1.0.9 (Sept 9, 2002)
74 Register declarations for the Atmel T89C51RD2 added by Johannes Hoelzl / johannes.hoelzl@gmx.de
76 Adding support for additional microcontrollers:
77 -----------------------------------------------
79 1. Don't modify this file!!!
81 2. Insert your code in a separate file e.g.: mcs51reg_update.h and include
82 this after the #define HEADER_MCS51REG statement in this file
84 3. The mcs51reg_update.h file should contain following definitions:
86 a. An entry with the inventory of the register set of the
87 microcontroller in the "Describe microcontrollers" section.
89 b. If necessary add entry(s) for registers not defined in this file
91 c. Define interrupt vectors
93 4. Send me the file mcs51reg_update.h ( bela.torok@kssg.ch ).
94 I'm going to verify/merge new definitions to this file.
97 Microcontroller support:
99 Use one of the following options:
101 1. use #include <mcs51reg.h> in your program & define MICROCONTROLLER_XXXX in your makefile.
103 2. use following definitions prior the
104 #include <mcs51reg.h> line in your program:
106 #define MICROCONTROLLER_8052 -> 8052 type microcontroller
108 #define MICROCONTROLLER_AT89CX051 -> Atmel AT89C1051, AT89C2051 and AT89C4051 microcontrollers
111 Use only one of the following definitions!!!
113 Supported Microcontrollers:
116 MICROCONTROLLER_8051 8051
117 MICROCONTROLLER_8052 8052
118 MICROCONTROLLER_AT89CX051 Atmel AT89C1051, AT89C2051 and AT89C4051
119 MICROCONTROLLER_AT89S53 Atmel AT89S53 microcontroller
120 MICROCONTROLLER_AT89X52 Atmel AT89C52 and AT80LV52 microcontrollers
121 MICROCONTROLLER_AT89X55 Atmel AT89C55 and AT80LV55 microcontrollers
122 MICROCONTROLLER_DS5000 Dallas DS5000 & DS2250 microcontroller
123 MICROCONTROLLER_DS5001 Dallas DS5001 & DS2251 microcontroller
124 MICROCONTROLLER_DS80C32X Dallas DS80C320 and DS80C323 microcontrollers
125 MICROCONTROLLER_DS80C390 Dallas DS80C390 microcontroller
126 MICROCONTROLLER_DS89C420 Dallas DS89C420 microcontroller
127 MICROCONTROLLER_DS8XC520 Dallas DS87C520 and DS83C520 microcontrollers
128 MICROCONTROLLER_P80C552 Philips P80C552
129 MICROCONTROLLER_SAB80515 Infineon / Siemens SAB80515 & SAB80535
130 MICROCONTROLLER_SAB80515A Infineon / Siemens SAB80515A
131 MICROCONTROLLER_SAB80517 Infineon / Siemens SAB80517
132 MICROCONTROLLER_T89C51RD2 Atmel T89C51RD2
134 Additional definitions (use them prior the #include mcs51reg.h statement):
136 Ports P0 & P2 are not available for the programmer if external ROM used.
137 Use statement "#define MCS51REG_EXTERNAL_RAM" to undefine P0 & P2.
139 Ports P0, P2, P3_6, WR, P3_7 & RD are not available for the programmer if
140 external RAM is used.
141 Use statement "#define MCS51REG_EXTERNAL_RAM" to undefine P0, P2,
144 #define MCS51REG_ENABLE_WARNINGS -> enable warnings
146 -----------------------------------------------------------------------*/
149 #ifndef HEADER_MCS51REG
150 #define HEADER_MCS51REG
152 ///////////////////////////////////////////////////////
153 /// Insert header here (for developers only) ///
154 /// remove "//" from the begining of the next line ///
155 /// #include "mcs51reg_update.h" ///
156 ///////////////////////////////////////////////////////
158 //////////////////////////////////
159 /// Describe microcontrollers ///
160 /// (inventory of registers) ///
161 //////////////////////////////////
163 // definitions for the 8051
164 #ifdef MICROCONTROLLER_8051
165 #ifdef MICROCONTROLLER_DEFINED
166 #define MCS51REG_ERROR
168 #ifndef MICROCONTROLLER_DEFINED
169 #define MICROCONTROLLER_DEFINED
171 #ifdef MCS51REG_ENABLE_WARNINGS
172 #warning Selected HW: 8051
178 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
189 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
191 #define IP__x__x__x__PS__PT1__PX1__PT0__PX0
196 // end of definitions for the 8051
199 // definitions for the 8052 microcontroller
200 #ifdef MICROCONTROLLER_8052
201 #ifdef MICROCONTROLLER_DEFINED
202 #define MCS51REG_ERROR
204 #ifndef MICROCONTROLLER_DEFINED
205 #define MICROCONTROLLER_DEFINED
207 #ifdef MCS51REG_ENABLE_WARNINGS
208 #warning Selected HW: 8052
215 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
226 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
228 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
232 // 8052 specific registers
233 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
239 // end of definitions for the 8052 microcontroller
242 // definitionsons for the Atmel
243 // AT89C1051, AT89C2051 and AT89C4051 microcontrollers
244 #ifdef MICROCONTROLLER_AT89CX051
245 #ifdef MICROCONTROLLER_DEFINED
246 #define MCS51REG_ERROR
248 #ifndef MICROCONTROLLER_DEFINED
249 #define MICROCONTROLLER_DEFINED
251 #ifdef MCS51REG_ENABLE_WARNINGS
252 #warning Selected HW: Atmel AT89Cx051
254 // 8051 register set without P0 & P2
258 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
268 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
270 #define IP__x__x__x__PS__PT1__PX1__PT0__PX0
275 // end of definitionsons for the Atmel
276 // AT89C1051, AT89C2051 and AT89C4051 microcontrollers
279 // definitions for the Atmel AT89S53
280 #ifdef MICROCONTROLLER_AT89S53
281 #ifdef MICROCONTROLLER_DEFINED
282 #define MCS51REG_ERROR
284 #ifndef MICROCONTROLLER_DEFINED
285 #define MICROCONTROLLER_DEFINED
287 #ifdef MCS51REG_ENABLE_WARNINGS
288 #warning Selected HW: AT89S53
295 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
306 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
308 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
312 // 8052 specific registers
313 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
318 // AT89S53 specific register
319 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
320 #define P1_EXT__x__x__x__x__x__x__T2EX__T2
328 // end of definitions for the Atmel AT89S53 microcontroller
331 // definitions for the Atmel AT89C52 and AT89LV52 microcontrollers
332 #ifdef MICROCONTROLLER_AT89X52
333 #ifdef MICROCONTROLLER_DEFINED
334 #define MCS51REG_ERROR
336 #ifndef MICROCONTROLLER_DEFINED
337 #define MICROCONTROLLER_DEFINED
339 #ifdef MCS51REG_ENABLE_WARNINGS
340 #warning Selected HW: AT89C52 or AT89LV52
347 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
358 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
360 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
364 // 8052 specific registers
365 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
370 // AT89X55 specific register
371 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
372 #define P1_EXT__x__x__x__x__x__x__T2EX__T2
374 // end of definitions for the Atmel AT89C52 and AT89LV52 microcontrollers
377 // definitions for the Atmel AT89C55 and AT89LV55 microcontrollers
378 #ifdef MICROCONTROLLER_AT89X55
379 #ifdef MICROCONTROLLER_DEFINED
380 #define MCS51REG_ERROR
382 #ifndef MICROCONTROLLER_DEFINED
383 #define MICROCONTROLLER_DEFINED
385 #ifdef MCS51REG_ENABLE_WARNINGS
386 #warning Selected HW: AT89C55 or AT89LV55
393 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
404 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
406 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
410 // 8052 specific registers
411 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
416 // AT89X55 specific register
417 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
418 #define P1_EXT__x__x__x__x__x__x__T2EX__T2
420 // end of definitions for the Atmel AT89C55 and AT89LV55 microcontrollers
423 // definitions for the Dallas DS5000
424 #ifdef MICROCONTROLLER_DS5000
425 #ifdef MICROCONTROLLER_DEFINED
426 #define MCS51REG_ERROR
428 #ifndef MICROCONTROLLER_DEFINED
429 #define MICROCONTROLLER_DEFINED
431 #ifdef MCS51REG_ENABLE_WARNINGS
432 #warning Selected HW: DS5000
438 #define PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
449 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
451 #define IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
452 #define MCON__SL__PAA__ECE2__RA32_8__PA0__PA1__PA2__PA3
458 // end of definitions for the Dallas DS5000
461 // definitions for the Dallas DS5001
462 #ifdef MICROCONTROLLER_DS5001
463 #ifdef MICROCONTROLLER_DEFINED
464 #define MCS51REG_ERROR
466 #ifndef MICROCONTROLLER_DEFINED
467 #define MICROCONTROLLER_DEFINED
469 #ifdef MCS51REG_ENABLE_WARNINGS
470 #warning Selected HW: DS5001
476 #define PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
487 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
489 #define IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
493 #define MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL
498 #define STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF
502 // end of definitions for the Dallas DS5001
505 // definitions for the Dallas DS80C320 and DS80C323 microcontrollers
506 #ifdef MICROCONTROLLER_DS80C32X
507 #ifdef MICROCONTROLLER_DEFINED
508 #define MCS51REG_ERROR
510 #ifndef MICROCONTROLLER_DEFINED
511 #define MICROCONTROLLER_DEFINED
513 #ifdef MCS51REG_ENABLE_WARNINGS
514 #warning Selected HW: Dallas DS80C320 or DS80C323
521 #define PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
533 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
535 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
539 // 8052 specific registers
540 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
545 // DS80C320 specific register
548 #define DPS__x__x__x__x__x__x__x__SEL
549 #define CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
550 #define EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
557 #define STATUS__PIP__HIP__LIP__x__x__x__x__x
559 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
560 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
562 #define EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
563 #define EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2
565 // end of definitions for the Dallas DS80C320 and DS80C323 microcontrollers
568 // definitions for the Dallas DS80C390
569 #ifdef MICROCONTROLLER_DS80C390
570 #ifdef MICROCONTROLLER_DEFINED
571 #define MCS51REG_ERROR
573 #ifndef MICROCONTROLLER_DEFINED
574 #define MICROCONTROLLER_DEFINED
576 #ifdef MCS51REG_ENABLE_WARNINGS
577 #warning Selected HW: Dallas DS80C390
584 #define PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
596 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
598 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
602 // 8052 specific registers
603 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
608 // DS80C390 specific register
612 #define DPS__ID1__ID0__TSL__x__x__x__x__SEL
613 #define CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
614 #define EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
622 #define ACON__x__x__x__x__x__SA__AM1__AM0
653 #define PMR__CD1__CD0__SWB__CTM__4X_2X__ALEOFF__x__x
654 #define STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
655 #define MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0
657 #define T2MOD__x__x__x__D13T1__D13T2__x__T2OE__DCEN
674 #define EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2
685 #define EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
692 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
694 // end of definitions for the Dallas DS80C390
696 // definitions for the Dallas DS89C420 microcontroller
697 #ifdef MICROCONTROLLER_DS89C420
698 #ifdef MICROCONTROLLER_DEFINED
699 #define MCS51REG_ERROR
701 #ifndef MICROCONTROLLER_DEFINED
702 #define MICROCONTROLLER_DEFINED
704 #ifdef MCS51REG_ENABLE_WARNINGS
705 #warning Selected HW: Dallas DS89C420
712 #define PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
724 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
726 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
730 // 8052 specific registers
731 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
736 // DS8XC420 specific registers
737 #define ACON__PAGEE__PAGES1__PAGES0__x__x__x__x__x
740 #define DPS__ID1__ID0__TSL__AID__x__x__x__SEL
741 #define CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
743 #define IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
744 #define IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
745 #define EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
746 #define PMR__CD1__CD0__SWB__CTM__4X_2X__ALEON__DME1__DME0
753 #define STATUS__PIS2__PIS1__PIS0__x__SPTA1__SPRA1__SPTA0__SPRA0
755 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
756 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
757 #define ROMSIZE__x__x__x__x__PRAME__RMS2__RMS1__RMS0
759 #define EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
760 #define EIP0__x__x__x__LPWDI__LPX5__LPX4__LPX3__LPX2
761 #define EIP1__x__x__x__MPWDI__MPX5__MPX4__MPX3__MPX2
762 #define FCNTL__FBUSY__FERR__x__x__FC3__FC2__FC1__FC0
764 // end of definitions for the Dallas DS89C420 microcontroller
766 // definitions for the Dallas DS87C520 and DS83C520 microcontrollers
767 #ifdef MICROCONTROLLER_DS8XC520
768 #ifdef MICROCONTROLLER_DEFINED
769 #define MCS51REG_ERROR
771 #ifndef MICROCONTROLLER_DEFINED
772 #define MICROCONTROLLER_DEFINED
774 #ifdef MCS51REG_ENABLE_WARNINGS
775 #warning Selected HW: Dallas DS87C520 or DS85C520
782 #define PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
794 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
796 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
800 // 8052 specific registers
801 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
806 // DS8XC520 specific registers
809 #define DPS__x__x__x__x__x__x__x__SEL
810 #define CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
811 #define EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
812 #define PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1__DME0
819 #define STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
821 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
822 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
824 #define ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0
827 #define EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
828 #define EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2
830 // end of definitions for the Dallas DS87C520 and DS83C520 microcontrollers
833 // definitions for the Philips P80C552 microcontroller
834 #ifdef MICROCONTROLLER_P80C552
835 #ifdef MICROCONTROLLER_DEFINED
836 #define MCS51REG_ERROR
838 #ifndef MICROCONTROLLER_DEFINED
839 #define MICROCONTROLLER_DEFINED
841 #ifdef MCS51REG_ENABLE_WARNINGS
842 #warning Selected HW: Philips P80C552
849 #define PCON__SMOD__x__x__WLE__GF1__GF0__PD__IDL
860 #define IE__EA__EAD__ES1__ES0__ET1__EX1__ET0__EX0
862 #define IP__x__PAD__PS1__PS0__PT1__PX1__PT0__PX0
866 // P80C552 specific register-names
867 #define S0BUF // same as SBUF, set in mcs51reg.h
868 #define S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI
869 // P80C552 specific registers
871 #define ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0
872 #define CTCON__CTN3__CTP3__CTN2__CTP2__CTN1__CTP1__CTN0__CTP0
887 #define IEN1__ET2__ECM2__ECM1__ECM0__ECT3__ECT2__ECT1__ECT0
888 #define IP1__PT2__PCM2__PCM1__PCM0__PCT3__PCT2__PCT1__PCT0
892 #define P1_EXT__SDA__SCL__RT2__T2__CT3I__CT2I__CT1I__CT0I
893 #define P4_AT_0XC0__CMT0__CMT1__CMSR5__CMSR4__CMSR3__CMSR2__CMSR1__CMSR0
895 #define RTE__TP47__TP46__RP45__RP44__RP43__RP42__RP41__RP40
896 #define S1ADR__x__x__x__x__x__x__x__GC
897 #define S1DAT_AT_0XDA
898 #define S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x
899 #define S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0
900 #define STE__TG47__TG46__SP45__SP44__SP43__SP42__SP41__SP40
903 #define TM2CON__T2IS1__T2IS0__T2ER__T2B0__T2P1__T2P0__T2MS1__T2MS0
904 #define TM2IR__T20V__CMI2__CMI1__CMI0__CTI3__CTI2__CTI1__CTI0
907 // end of definitions for the Philips P80C552 microcontroller
910 // definitions for the Infineon / Siemens SAB80515 & SAB80535
911 #ifdef MICROCONTROLLER_SAB80515
912 #ifdef MICROCONTROLLER_DEFINED
913 #define MCS51REG_ERROR
915 #ifndef MICROCONTROLLER_DEFINED
916 #define MICROCONTROLLER_DEFINED
918 #ifdef MCS51REG_ENABLE_WARNINGS
919 #warning Selected HW: Infineon / Siemens SAB80515 & SAB80535
921 // 8051 register set without IP
926 #define PCON__SMOD__x__x__x__x__x__x__x
937 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
942 // SAB80515 specific registers
943 #define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
944 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
945 #define IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
954 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
961 #define DAPR__SAB80515
965 // end of definitions for the Infineon / Siemens SAB80515
968 // definitions for the Infineon / Siemens SAB80515A
969 #ifdef MICROCONTROLLER_SAB80515A
970 #ifdef MICROCONTROLLER_DEFINED
971 #define MCS51REG_ERROR
973 #ifndef MICROCONTROLLER_DEFINED
974 #define MICROCONTROLLER_DEFINED
976 #ifdef MCS51REG_ENABLE_WARNINGS
977 #warning Selected HW: Infineon / Siemens SAB80515A
979 // 8051 register set without IP
984 #define PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
995 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
1000 // SAB80515A specific registers
1001 #define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
1002 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
1003 #define IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
1004 #define IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
1013 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
1030 // end of definitions for the Infineon / Siemens SAB80515A
1033 // definitions for the Infineon / Siemens SAB80517
1034 #ifdef MICROCONTROLLER_SAB80517
1035 #ifdef MICROCONTROLLER_DEFINED
1036 #define MCS51REG_ERROR
1038 #ifndef MICROCONTROLLER_DEFINED
1039 #define MICROCONTROLLER_DEFINED
1041 #ifdef MCS51REG_ENABLE_WARNINGS
1042 #warning Selected HW: Infineon / Siemens SAB80517
1044 // 8051 register set without IP, SCON & SBUF
1049 #define PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
1060 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
1065 // SAB80517 specific registers
1066 #define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
1067 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
1068 #define IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
1069 #define IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
1070 #define IEN2__SAB80517
1100 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
1103 #define CTCOM_AT_0XE1
1111 #define DAPR__SAB80517
1126 #define S0CON__SM0__SM1__SM20__REN0__TB80__RB80__TI0__RI0
1130 #define S1CON_AT_0X9B
1137 // end of definitions for the Infineon / Siemens SAB80517
1140 // definitions for the Atmel T89C51RD2
1141 #ifdef MICROCONTROLLER_T89C51RD2
1142 #ifdef MICROCONTROLLER_DEFINED
1143 #define MCS51REG_ERROR
1145 #ifndef MICROCONTROLLER_DEFINED
1146 #define MICROCONTROLLER_DEFINED
1148 #ifdef MCS51REG_ENABLE_WARNINGS
1149 #warning Selected HW: T89C51RD2
1152 // 8051 register set
1157 #define PCON__SMOD1__SMOD0__x__POF__GF1__GF0__PD__IDL
1168 #define IE__EA__EC__ET2__ES__ET1__EX1__ET0__EX0
1171 #define IP__x__PPC__PT2__PS__PT1__PX1__PT0__PX0
1176 // 8052 register set
1177 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
1183 // T89C51RD2 register set
1184 #define P4_AT_0XC0__P4_7__P4_6__P4_5__P4_3__P4_2__P4_1__P4_0
1196 #define CKCON__X2__T0X2__T1X2__T2X2__SiX2__PcaX2__WdX2__x
1216 #endif /* MICROCONTROLLER_T89C51RD2 */
1217 /* end of definition for the Atmel T89C51RD2 */
1220 /////////////////////////////////////////////////////////
1221 /// don't specify microcontrollers below this line! ///
1222 /////////////////////////////////////////////////////////
1225 // default microcontroller -> 8051
1226 // use default if no microcontroller specified
1227 #ifndef MICROCONTROLLER_DEFINED
1228 #define MICROCONTROLLER_DEFINED
1229 #ifdef MCS51REG_ENABLE_WARNINGS
1230 #warning No microcontroller defined!
1231 #warning Code generated for the 8051
1233 // 8051 register set
1238 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
1249 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
1251 #define IP__x__x__x__PS__PT1__PX1__PT0__PX0
1256 // end of definitions for the default microcontroller
1259 #ifdef MCS51REG_ERROR
1260 #error Two or more microcontrollers defined!
1263 #ifdef MCS51REG_EXTERNAL_ROM
1264 #ifndef MCS51REG_UNDEFINE_P0
1265 #define MCS51REG_UNDEFINE_P0
1267 #ifndef MCS51REG_UNDEFINE_P2
1268 #define MCS51REG_UNDEFINE_P2
1272 #ifdef MCS51REG_EXTERNAL_RAM
1273 #ifndef MCS51REG_UNDEFINE_P0
1274 #define MCS51REG_UNDEFINE_P0
1276 #ifndef MCS51REG_UNDEFINE_P2
1277 #define MCS51REG_UNDEFINE_P2
1281 #ifdef MCS51REG_UNDEFINE_P0
1285 #ifdef MCS51REG_UNDEFINE_P2
1289 ////////////////////////////////
1290 /// Register definitions ///
1291 /// (In alphabetical order) ///
1292 ////////////////////////////////
1299 #ifdef ACON__PAGEE__PAGES1__PAGES0__x__x__x__x__x
1300 #undef ACON__PAGEE__PAGES1__PAGES0__x__x__x__x__x
1301 sfr at 0x9D ACON ; // DS89C420 specific
1302 // Not directly accessible bits
1308 #ifdef ACON__x__x__x__x__x__SA__AM1__AM0
1309 #undef ACON__x__x__x__x__x__SA__AM1__AM0
1310 sfr at 0x9D ACON ; // DS89C390 specific
1311 // Not directly accessible bits
1319 sfr at 0xC6 ADCH ; // A/D converter high
1324 sfr at 0xD8 ADCON ; // A/D-converter control register SAB80515 specific
1335 // ADCON0 ... Infineon / Siemens also called this register ADCON in the User Manual
1338 sfr at 0xD8 ADCON0 ; // A/D-converter control register 0 SAB80515A &
1339 // Bit registers // SAB80517 specific
1348 // Not directly accessible ADCON0
1349 #define ADCON0_MX0 0x01
1350 #define ADCON0_MX1 0x02
1351 #define ADCON0_MX2 0x04
1352 #define ADCON0_ADM 0x08
1353 #define ADCON0_BSY 0x10
1354 #define ADCON0_ADEX 0x20
1355 #define ADCON0_CLK 0x40
1356 #define ADCON0_BD 0x80
1361 sfr at 0xDC ADCON1 ; // A/D-converter control register 1 SAB80515A & SAB80517 specific
1362 // Not directly accessible ADCON1
1363 #define ADCON1_MX0 0x01
1364 #define ADCON1_MX1 0x02
1365 #define ADCON1_MX2 0x04
1366 #define ADCON1_ADCL 0x80
1369 #ifdef ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0
1370 #undef ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0
1371 sfr at 0xC5 ADCON ; // A/D control, P80C552 specific
1372 // Not directly accessible Bits.
1379 #define ADC_0 0x40 // different name as ADC0 in P5
1380 #define ADC_1 0x80 // different name as ADC1 in P5
1385 sfr at 0xD9 ADDAT ; // A/D-converter data register SAB80515 specific
1390 sfr at 0xD9 ADDATH ; // A/D data high byte SAB80515A specific
1395 sfr at 0xDA ADDATL ; // A/D data low byte SAB80515A specific
1400 sfr at 0xEF ARCON ; // arithmetic control register SAB80517
1405 sfr at 0x9C AP ; // DS80C390
1421 sbit at 0xF0 BREG_F0 ;
1422 sbit at 0xF1 BREG_F1 ;
1423 sbit at 0xF2 BREG_F2 ;
1424 sbit at 0xF3 BREG_F3 ;
1425 sbit at 0xF4 BREG_F4 ;
1426 sbit at 0xF5 BREG_F5 ;
1427 sbit at 0xF6 BREG_F6 ;
1428 sbit at 0xF7 BREG_F7 ;
1441 // Not directly accessible bits
1452 sfr at 0xA3 C0C ; // DS80C390 specific
1453 // Not directly accessible bits
1466 sfr at 0xA5 C0IR ; // DS80C390 specific
1467 // Not directly accessible bits
1480 sfr at 0xAB C0M1C ; // DS80C390 specific
1481 // Not directly accessible bits
1483 #define ROW_TIH 0x02
1494 sfr at 0xAC C0M2C ; // DS80C390 specific
1499 sfr at 0xAD C0M3C ; // DS80C390 specific
1504 sfr at 0xAE C0M4C ; // DS80C390 specific
1509 sfr at 0xAF C0M5C ; // DS80C390 specific
1514 sfr at 0xB3 C0M6C ; // DS80C390 specific
1519 sfr at 0xB4 C0M7C ; // DS80C390 specific
1524 sfr at 0xB5 C0M8C ; // DS80C390 specific
1529 sfr at 0xB6 C0M9C ; // DS80C390 specific
1534 sfr at 0xB7 C0M10C ; // DS80C390 specific
1539 sfr at 0xBB C0M11C ; // DS80C390 specific
1544 sfr at 0xBC C0M12C ; // DS80C390 specific
1549 sfr at 0xBD C0M13C ; // DS80C390 specific
1554 sfr at 0xBE C0M14C ; // DS80C390 specific
1559 sfr at 0xBF C0M15C ; // DS80C390 specific
1564 sfr at 0xA7 C0RE ; // DS80C390 specific
1569 sfr at 0x96 C0RMS0 ; // DS80C390 specific
1574 sfr at 0x97 C0RMS1 ; // DS80C390 specific
1579 sfr at 0xA4 C0S ; // DS80C390 specific
1580 // Not directly accessible bits
1587 #define EC96_128 0x40
1593 sfr at 0xA6 C0TE ; // DS80C390 specific
1598 sfr at 0x9E C0TMA0 ; // DS80C390 specific
1603 sfr at 0x9F C0TMA1 ; // DS80C390 specific
1608 sfr at 0xE3 C1C ; // DS80C390 specific
1609 // Not directly accessible bits
1622 sfr at 0xE5 C1IR ; // DS80C390 specific
1623 // Not directly accessible bits
1636 sfr at 0xE7 C1RE ; // DS80C390 specific
1641 sfr at 0xEB C1M1C ; // DS80C390 specific
1646 sfr at 0xEC C1M2C ; // DS80C390 specific
1651 sfr at 0xED C1M3C ; // DS80C390 specific
1656 sfr at 0xEE C1M4C ; // DS80C390 specific
1661 sfr at 0xEF C1M5C ; // DS80C390 specific
1666 sfr at 0xF3 C1M6C ; // DS80C390 specific
1671 sfr at 0xF4 C1M7C ; // DS80C390 specific
1676 sfr at 0xF5 C1M8C ; // DS80C390 specific
1681 sfr at 0xF6 C1M9C ; // DS80C390 specific
1686 sfr at 0xF7 C1M10C ; // DS80C390 specific
1691 sfr at 0xFB C1M11C ; // DS80C390 specific
1696 sfr at 0xFC C1M12C ; // DS80C390 specific
1701 sfr at 0xFD C1M13C ; // DS80C390 specific
1706 sfr at 0xFE C1M14C ; // DS80C390 specific
1711 sfr at 0xFF C1M15C ; // DS80C390 specific
1716 sfr at 0xE4 C1S ; // DS80C390 specific
1717 // Not directly accessible bits
1730 sfr at 0xE6 C1TE ; // DS80C390 specific
1735 sfr at 0xD6 C1RSM0 ; // DS80C390 specific
1740 sfr at 0xD7 C1RSM1 ; // DS80C390 specific
1745 sfr at 0xDE C1TMA0 ; // DS80C390 specific
1750 sfr at 0xDF C1TMA1 ; // DS80C390 specific
1755 sfr at 0xC9 CC4EN ; // compare/capture 4 enable register SAB80517 specific
1810 sfr at 0x0DA CCAPM0;
1822 sfr at 0x0DB CCAPM1;
1827 sfr at 0x0DC CCAPM2;
1832 sfr at 0x0DD CCAPM3;
1837 sfr at 0x0DE CCAPM4;
1842 sfr at 0xC1 CCEN ; // compare/capture enable register SAB80515 specific
1847 sfr at 0xC3 CCH1 ; // compare/capture register 1, high byte SAB80515 specific
1852 sfr at 0xC5 CCH2 ; // compare/capture register 2, high byte SAB80515 specific
1857 sfr at 0xC7 CCH3 ; // compare/capture register 3, high byte SAB80515 specific
1862 sfr at 0xCF CCH4 ; // compare/capture register 4, high byte SAB80515 specific
1867 sfr at 0xC2 CCL1 ; // compare/capture register 1, low byte SAB80515 specific
1872 sfr at 0xC4 CCL2 ; // compare/capture register 2, low byte SAB80515 specific
1877 sfr at 0xC6 CCL3 ; // compare/capture register 3, low byte SAB80515 specific
1882 sfr at 0xCE CCL4 ; // compare/capture register 4, low byte SAB80515 specific
1887 sfr at 0xD8 CCON; // T89C51RD2 specific register
1903 #ifdef CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
1904 #undef CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
1905 sfr at 0x8E CKCON ; // DS80C320 & DS80C390 specific
1906 // Not directly accessible Bits.
1917 #ifdef CKCON__X2__T0X2__T1X2__T2X2__SiX2__PcaX2__WdX2__x
1918 #undef CKCON__X2__T0X2__T1X2__T2X2__SiX2__PcaX2__WdX2__x
1931 sfr at 0x96 CKMOD ; // DS89C420 specific
1932 // Not directly accessible Bits.
1945 sfr at 0xF6 CMEN ; // compare enable register SAB80517 specific
1950 sfr at 0xD3 CMH0 ; // compare register 0 high byte SAB80517 specific
1955 sfr at 0xD5 CMH1 ; // compare register 1 high byte SAB80517 specific
1960 sfr at 0xD7 CMH2 ; // compare register 2 high byte SAB80517 specific
1965 sfr at 0xE3 CMH3 ; // compare register 3 high byte SAB80517 specific
1970 sfr at 0xE5 CMH4 ; // compare register 4 high byte SAB80517 specific
1975 sfr at 0xE7 CMH5 ; // compare register 5 high byte SAB80517 specific
1980 sfr at 0xF3 CMH6 ; // compare register 6 high byte SAB80517 specific
1985 sfr at 0xF5 CMH7 ; // compare register 7 high byte SAB80517 specific
1990 sfr at 0xC9 CMH0 ; // Compare high 0, P80C552 specific
1995 sfr at 0xCA CMH1 ; // Compare high 1, P80C552 specific
2000 sfr at 0xCB CMH2 ; // Compare high 2, P80C552 specific
2005 sfr at 0xD2 CML0 ; // compare register 0 low byte SAB80517 specific
2010 sfr at 0xD4 CML1 ; // compare register 1 low byte SAB80517 specific
2015 sfr at 0xD6 CML2 ; // compare register 2 low byte SAB80517 specific
2020 sfr at 0xE2 CML3 ; // compare register 3 low byte SAB80517 specific
2025 sfr at 0xE4 CML4 ; // compare register 4 low byte SAB80517 specific
2030 sfr at 0xE6 CML5 ; // compare register 5 low byte SAB80517 specific
2035 sfr at 0xF2 CML6 ; // compare register 6 low byte SAB80517 specific
2040 sfr at 0xF4 CML7 ; // compare register 7 low byte SAB80517 specific
2045 sfr at 0xA9 CML0 ; // Compare low 0, P80C552 specific
2050 sfr at 0xAA CML1 ; // Compare low 1, P80C552 specific
2055 sfr at 0xAB CML2 ; // Compare low 2, P80C552 specific
2070 sfr at 0xF7 CMSEL ; // compare input select SAB80517
2075 sfr at 0xCE COR ; // Dallas DS80C390 specific
2088 sfr at 0xC1 CRC ; // Dallas DS5001 specific
2099 sfr at 0xCB CRCH ; // compare/reload/capture register, high byte SAB80515 specific
2104 sfr at 0xC3 CRCHIGH ; // DS5001 specific
2109 sfr at 0xCA CRCL ; // compare/reload/capture register, low byte SAB80515 specific
2114 sfr at 0xC2 CRCLOW ; // DS5001 specific
2117 #ifdef CTCOM_AT_0XE1
2118 #undef CTCOM_AT_0XE1
2119 sfr at 0xE1 CTCON ; // com.timer control register SAB80517
2122 #ifdef CTCON__CTN3__CTP3__CTN2__CTP2__CTN1__CTP1__CTN0__CTP0
2123 #undef CTCON__CTN3__CTP3__CTN2__CTP2__CTN1__CTP1__CTN0__CTP0
2124 sfr at 0xEB CTCON ; // Capture control, P80C552 specific
2125 // Not directly accessible Bits.
2138 sfr at 0xCC CTH0 ; // Capture high 0, P80C552 specific
2143 sfr at 0xCD CTH1 ; // Capture high 1, P80C552 specific
2148 sfr at 0xCE CTH2 ; // Capture high 2, P80C552 specific
2153 sfr at 0xCF CTH3 ; // Capture high 3, P80C552 specific
2158 sfr at 0xAC CTL0 ; // Capture low 0, P80C552 specific
2163 sfr at 0xAD CTL1 ; // Capture low 1, P80C552 specific
2168 sfr at 0xAE CTL2 ; // Capture low 2, P80C552 specific
2173 sfr at 0xAF CTL3 ; // Capture low 3, P80C552 specific
2178 sfr at 0xDF CTRELH ; // com.timer rel register high byte SAB80517
2183 sfr at 0xDE CTRELL ; // com.timer rel register low byte SAB80517
2186 #ifdef DAPR__SAB80515
2187 #undef DAPR__SAB80515
2188 sfr at 0xD8 DAPR ; // D/A-converter program register SAB80515 specific
2191 #ifdef DAPR__SAB80517
2192 #undef DAPR__SAB80517
2193 sfr at 0xDA DAPR ; // D/A-converter program register SAB80517 specific
2199 sfr at 0x83 DP0H ; // Alternate name for AT89S53
2204 sfr at 0x85 DPH1 ; // DS80C320 specific
2205 sfr at 0x85 DP1H ; // Alternate name for AT89S53
2210 sfr at 0x82 DPL ; // Alternate name for AT89S53
2216 sfr at 0x84 DPL1 ; // DS80C320 specific
2217 sfr at 0x84 DP1L ; // Alternate name for AT89S53
2220 #ifdef DPS__x__x__x__x__x__x__x__SEL
2221 #undef DPS__x__x__x__x__x__x__x__SEL
2223 // Not directly accessible DPS Bit. DS80C320 & DPS8XC520 specific
2227 #ifdef DPS__ID1__ID0__TSL__x__x__x__x__SEL
2228 #undef DPS__ID1__ID0__TSL__x__x__x__x__SEL
2230 // Not directly accessible DPS Bit. DS89C390 specific
2237 #ifdef DPS__ID1__ID0__TSL__AID__x__x__x__SEL
2238 #undef DPS__ID1__ID0__TSL__AID__x__x__x__SEL
2240 // Not directly accessible DPS Bit. DS89C420 specific
2250 sfr at 0x92 DPSEL ; // data pointer select register SAB80517
2255 sfr at 0x93 DPX1 ; // DS80C390 specific
2260 sfr at 0x95 DPX1 ; // DS80C390 specific
2280 #ifdef EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
2281 #undef EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
2283 // Bit registers DS80C320 specific
2291 #ifdef EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2
2292 #undef EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2
2294 // Bit registers DS80C390 specific
2302 sbit at 0xEF CANBIE ;
2305 #ifdef EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2
2306 #undef EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2
2308 // Bit registers DS80C320 specific
2316 #ifdef EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
2317 #undef EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
2319 // Bit registers DS80C320 specific
2327 sbit at 0xFF CANBIP ;
2330 #ifdef EIP0__x__x__x__LPWDI__LPX5__LPX4__LPX3__LPX2
2331 #undef EIP0__x__x__x__LPWDI__LPX5__LPX4__LPX3__LPX2
2333 // Bit registers DS89C420 specific
2338 sbit at 0xFC LPWDI ;
2341 #ifdef EIP1__x__x__x__MPWDI__MPX5__MPX4__MPX3__MPX2
2342 #undef EIP1__x__x__x__MPWDI__MPX5__MPX4__MPX3__MPX2
2344 // Not directly accessible Bits DS89C420 specific
2355 // Not directly accessible Bits DS80C390 specific
2360 #ifdef EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
2361 #undef EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
2363 // Not directly accessible EXIF Bits DS80C320 specific
2373 #ifdef EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
2374 #undef EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
2376 // Not directly accessible EXIF Bits DS87C520 specific
2387 #ifdef EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
2388 #undef EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
2390 // Not directly accessible EXIF Bits DS80C390 & DS89C420 specific
2401 #ifdef FCNTL__FBUSY__FERR__x__x__FC3__FC2__FC1__FC0
2402 #undef FCNTL__FBUSY__FERR__x__x__FC3__FC2__FC1__FC0
2404 // Not directly accessible DS89C420 specific
2432 #ifdef IE__EA__x__x__ES__ET1__EX1__ET0__EX0
2433 #undef IE__EA__x__x__ES__ET1__EX1__ET0__EX0
2444 #ifdef IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
2445 #undef IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
2453 sbit at 0xAD ET2 ; // Enable timer2 interrupt
2457 #ifdef IE__EA__EAD__ES1__ES0__ET1__EX1__ET0__EX0
2458 #undef IE__EA__EAD__ES1__ES0__ET1__EX1__ET0__EX0
2459 sfr at 0xA8 IE ; // same as IEN0 - Interrupt enable 0, P80C552 specific
2460 sfr at 0xA8 IEN0 ; // alternate name
2472 #ifdef IE__EA__EC__ET2__ES__ET1__EX1__ET0__EX0
2473 #undef IE__EA__EC__ET2__ES__ET1__EX1__ET0__EX0
2484 #ifdef IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
2485 #undef IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
2493 sbit at 0xAC ES0 ; // Alternate name
2494 sbit at 0xAD ET2 ; // Enable timer2 interrupt
2499 #ifdef IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
2500 #undef IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
2502 sfr at 0xA8 IEN0 ; // Alternate name
2503 // Bit registers for the SAB80515 and compatible IE
2510 sbit at 0xAD ET2 ; // Enable timer 2 overflow SAB80515 specific
2511 sbit at 0xAE WDT ; // watchdog timer reset - SAB80515 specific
2513 sbit at 0xAF EAL ; // EA as called by Infineon / Siemens
2516 #ifdef IEN1__ET2__ECM2__ECM1__ECM0__ECT3__ECT2__ECT1__ECT0
2517 #undef IEN1__ET2__ECM2__ECM1__ECM0__ECT3__ECT2__ECT1__ECT0
2518 sfr at 0xE8 IEN1 ; // Interrupt enable 1, P80C552 specific
2530 #ifdef IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
2531 #undef IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
2532 sfr at 0xB8 IEN1 ; // interrupt enable register - SAB80515 specific
2534 sbit at 0xB8 EADC ; // A/D converter interrupt enable
2540 sbit at 0xBE SWDT ; // watchdog timer start/reset
2541 sbit at 0xBF EXEN2 ; // timer2 external reload interrupt enable
2544 #ifdef IEN2__SAB80517
2545 #undef IEN2__SAB80517
2546 sfr at 0x9A IEN2 ; // interrupt enable register 2 SAB80517
2549 #ifdef IP__x__x__x__PS__PT1__PX1__PT0__PX0
2550 #undef IP__x__x__x__PS__PT1__PX1__PT0__PX0
2560 #ifdef IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
2561 #undef IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
2569 sbit at 0xBC PS0 ; // alternate name
2573 #ifdef IP__x__PAD__PS1__PS0__PT1__PX1__PT0__PX0
2574 #undef IP__x__PAD__PS1__PS0__PT1__PX1__PT0__PX0
2575 sfr at 0xB8 IP ; // Interrupt priority 0, P80C552 specific
2576 sfr at 0xB8 IP0 ; // alternate name
2587 #ifdef IP__x__PPC__PT2__PS__PT1__PX1__PT0__PX0
2588 #undef IP__x__PPC__PT2__PS__PT1__PX1__PT0__PX0
2600 #ifdef IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
2601 #undef IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
2613 #ifdef IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
2614 #undef IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
2625 #ifdef IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
2626 #undef IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
2627 sfr at 0xA9 IP0 ; // interrupt priority register SAB80515 specific
2628 // Not directly accessible IP0 bits
2638 #ifdef IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
2639 #undef IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
2640 sfr at 0xB8 IP0 ; // interrupt priority register DS89C420 specific
2641 // Not directly accessible IP0 bits
2651 #ifdef IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
2652 #undef IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
2653 sfr at 0xB9 IP1 ; // interrupt priority register SAB80515 specific
2654 // Not directly accessible IP1 bits
2663 #ifdef IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
2664 #undef IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
2665 sfr at 0xB1 IP1 ; // interrupt priority register DS89C420 specific
2666 // Not directly accessible IP0 bits
2676 #ifdef IP1__PT2__PCM2__PCM1__PCM0__PCT3__PCT2__PCT1__PCT0
2677 #undef IP1__PT2__PCM2__PCM1__PCM0__PCT3__PCT2__PCT1__PCT0
2678 sfr at 0xF8 IP1 ; // Interrupt priority 1, P80C552 specific
2704 sfr at 0xC0 IRCON ; // interrupt control register - SAB80515 specific
2706 sbit at 0xC0 IADC ; // A/D converter irq flag
2707 sbit at 0xC1 IEX2 ; // external interrupt edge detect flag
2712 sbit at 0xC6 TF2 ; // timer 2 owerflow flag
2713 sbit at 0xC7 EXF2 ; // timer2 reload flag
2718 sfr at 0xC0 IRCON0 ; // interrupt control register - SAB80515 specific
2720 sbit at 0xC0 IADC ; // A/D converter irq flag
2721 sbit at 0xC1 IEX2 ; // external interrupt edge detect flag
2726 sbit at 0xC6 TF2 ; // timer 2 owerflow flag
2727 sbit at 0xC7 EXF2 ; // timer2 reload flag
2732 sfr at 0xD1 IRCON1 ; // interrupt control register - SAB80515 specific
2737 sfr at 0xD3 MA ; // DS80C390
2742 sfr at 0xD4 MB ; // DS80C390
2747 sfr at 0xD5 MC ; // DS80C390
2752 sfr at 0xD1 MCNT0 ; // DS80C390
2765 sfr at 0xD2 MCNT1 ; // DS80C390
2771 #ifdef MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0
2772 #undef MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0
2773 sfr at 0xC6 MCON ; // DS80C390
2783 #ifdef MCON__PA3__PA2__PA1__PA0__RA32_8__ECE2__PAA__SL
2784 #undef MCON__PA3__PA2__PA1__PA0__RA32_8__ECE2__PAA__SL
2785 sfr at 0xC6 MCON ; // DS5000
2796 #ifdef MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL
2797 #undef MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL
2798 sfr at 0xC6 MCON ; // DS5001
2811 sfr at 0xE9 MD0 ; // MUL / DIV register 0 SAB80517
2816 sfr at 0xEA MD1 ; // MUL / DIV register 1 SAB80517
2821 sfr at 0xEB MD2 ; // MUL / DIV register 2 SAB80517
2826 sfr at 0xEC MD3 ; // MUL / DIV register 3 SAB80517
2831 sfr at 0xED MD4 ; // MUL / DIV register 4 SAB80517
2836 sfr at 0xEE MD5 ; // MUL / DIV register 5 SAB80517
2841 sfr at 0xEA MXAX ; // Dallas DS80C390
2872 #ifdef P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
2873 #undef P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
2874 // P1 alternate functions
2885 #ifdef P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
2886 sbit at 0x90 INT3_CC0 ; // P1 alternate functions - SAB80515 specific
2887 sbit at 0x91 INT4_CC1 ;
2888 sbit at 0x92 INT5_CC2 ;
2889 sbit at 0x93 INT6_CC3 ;
2892 sbit at 0x96 CLKOUT ;
2896 #ifdef P1_EXT__CT0I__CT1I__CT2I__CT3I__T2__RT2__SCL__SDA
2897 #undef P1_EXT__CT0I__CT1I__CT2I__CT3I__T2__RT2__SCL__SDA
2899 sbit at 0x90 CT0I ; // Port 1 alternate functions, P80C552 specific
2909 #ifdef P1_EXT__x__x__x__x__x__x__T2EX__T2
2910 #undef P1_EXT__x__x__x__x__x__x__T2EX__T2
2911 // P1 alternate functions
2940 #ifndef MCS51REG_EXTERNAL_RAM
2953 #ifndef MCS51REG_EXTERNAL_RAM
2961 sfr at 0x80 P4 ; // Port 4 - DS80C390
2973 #ifdef P4_AT_0XC0__CMT0__CMT1__CMSR5__CMSR4__CMSR3__CMSR2__CMSR1__CMSR0
2974 #undef P4_AT_0XC0__CMT0__CMT1__CMSR5__CMSR4__CMSR3__CMSR2__CMSR1__CMSR0
2975 sfr at 0xC0 P4 ; // Port 4, P80C552 specific
2977 sbit at 0xC0 CMSR0 ;
2978 sbit at 0xC1 CMSR1 ;
2979 sbit at 0xC2 CMSR2 ;
2980 sbit at 0xC3 CMSR3 ;
2981 sbit at 0xC4 CMSR4 ;
2982 sbit at 0xC5 CMSR5 ;
2987 #ifdef P4_AT_0XC0__P4_7__P4_6__P4_5__P4_3__P4_2__P4_1__P4_0
2988 #undef P4_AT_0XC0__P4_7__P4_6__P4_5__P4_3__P4_2__P4_1__P4_0
2989 sfr at 0xC0 P4 ; // Port 4, T89C51 specific
3003 sfr at 0xE8 P4 ; // Port 4 - SAB80515 & compatible microcontrollers
3017 sfr at 0x92 P4CNT ; // DS80C390
3018 // Not directly accessible bits
3019 #define P4CNT_0 0x01
3020 #define P4CNT_1 0x02
3021 #define P4CNT_2 0x04
3022 #define P4CNT_3 0x08
3023 #define P4CNT_4 0x10
3024 #define P4CNT_5 0x20
3030 sfr at 0xA1 P5 ; // Port 5 - DS80C390
3035 sfr at 0xE8 P5; // Port 5 - T89C51RD2
3049 sfr at 0xA2 P5CNT ; // DS80C390
3050 // Not directly accessible bits
3051 #define P5CNT_0 0x01
3052 #define P5CNT_1 0x02
3053 #define P5CNT_2 0x04
3057 #define SBCAN0BA 0x40
3058 #define SBCAN1BA 0x80
3063 sfr at 0xC4 P5 ; // Port 5, P80C552 specific
3064 // Not directly accessible Bits.
3077 sfr at 0xF8 P5 ; // Port 5 - SAB80515 & compatible microcontrollers
3091 sfr at 0xDB P6 ; // Port 6 - SAB80515 & compatible microcontrollers
3096 sfr at 0xFA P6 ; // Port 6 - SAB80517 specific
3101 sfr at 0xDB P7 ; // Port 7 - SAB80517 specific
3106 sfr at 0xDD P8 ; // Port 6 - SAB80517 specific
3109 #ifdef PCON__SMOD__x__x__x__x__x__x__x
3110 #undef PCON__SMOD__x__x__x__x__x__x__x
3112 // Not directly accessible PCON bits
3116 #ifdef PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
3117 #undef PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
3119 // Not directly accessible PCON bits
3127 #ifdef PCON__SMOD__x__x__WLE__GF1__GF0__PD__IDL
3128 #undef PCON__SMOD__x__x__WLE__GF1__GF0__PD__IDL
3129 sfr at 0x87 PCON ; // PCON, P80C552 specific
3130 // Not directly accessible Bits.
3132 #define IDLE 0x01 ; same as IDL
3140 #ifdef PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
3141 #undef PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
3143 // Not directly accessible PCON bits
3145 #define IDLE 0x01 ; same as IDL
3147 #define PDE 0x02 ; same as PD
3152 #define PCON_IDLE 0x01
3153 #define PCON_PDE 0x02
3154 #define PCON_GF0 0x04
3155 #define PCON_GF1 0x08
3156 #define PCON_IDLS 0x20
3157 #define PCON_PDS 0x40
3158 #define PCON_SMOD 0x80
3161 #ifdef PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
3162 #undef PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
3164 // Not directly accessible PCON bits
3166 #define IDLE 0x01 ; same as IDL
3176 #ifdef PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
3177 #undef PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
3179 // Not directly accessible PCON bits
3181 #define IDLE 0x01 ; same as IDL
3189 #ifdef PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
3190 #undef PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
3192 // Not directly accessible PCON bits
3194 #define IDLE 0x01 ; same as IDL
3202 #define SMOD_0 0x80 ; same as SMOD
3205 #ifdef PCON__SMOD1__SMOD0__x__POF__GF1__GF0__PD__IDL
3206 #undef PCON__SMOD1__SMOD0__x__POF__GF1__GF0__PD__IDL
3217 #ifdef PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1__DME0
3218 #undef PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1__DME0
3219 sfr at 0xC4 PMR ; // DS87C520, DS83C520
3220 // Not directly accessible bits
3230 #ifdef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEOFF__x__x
3231 #undef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEOFF__x__x
3232 sfr at 0xC4 PMR ; // DS80C390
3233 // Not directly accessible bits
3242 #ifdef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEON__DME1__DME0
3243 #undef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEON__DME1__DME0
3244 sfr at 0xC4 PMR ; // DS89C420
3245 // Not directly accessible bits
3272 sfr at 0xFC PWM0 ; // PWM register 0, P80C552 specific
3277 sfr at 0xFD PWM1 ; // PWM register 1, P80C552 specific
3282 sfr at 0xFE PWMP ; // PWM prescaler, P80C552 specific
3287 sfr at 0xCB RCAP2H ;
3292 sfr at 0xCA RCAP2L ;
3300 #ifdef ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0
3301 #undef ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0
3302 sfr at 0xC2 ROMSIZE ; // DS87C520, DS83C520
3303 // Not directly accessible bits
3309 #ifdef ROMSIZE__x__x__x__x__PRAME__RMS2__RMS1__RMS0
3310 #undef ROMSIZE__x__x__x__x__PRAME__RMS2__RMS1__RMS0
3311 sfr at 0xC2 ROMSIZE ; // DS89C420
3312 // Not directly accessible bits
3319 #ifdef ROMSIZE__HBPF__BPF__TE__MOVCX__PRAME__RMS2__RMS1__RMS0
3320 #undef ROMSIZE__HBPF__BPF__TE__MOVCX__PRAME__RMS2__RMS1__RMS0
3321 sfr at 0xC2 ROMSIZE ; // DS87C520, DS83C520
3322 // Not directly accessible bits
3335 sfr at 0xD8 RPCTL ; // Dallas DS5001 specific
3337 sbit at 0xD9 RPCON ;
3342 sbit at 0xDF RNR_FLAG ;
3345 #ifdef RTE__TP47__TP46__RP45__RP44__RP43__RP42__RP41__RP40
3346 #undef RTE__TP47__TP46__RP45__RP44__RP43__RP42__RP41__RP40
3347 sfr at 0xEF RTE ; // Reset/toggle enable, P80C552 specific
3348 // Not directly accessible Bits.
3361 sfr at 0x99 S0BUF ; // serial channel 0 buffer register SAB80517 specific
3364 #ifdef S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI
3365 #undef S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI
3366 sfr at 0x98 S0CON ; // serial channel 0 control register P80C552 specific
3368 // Already defined in SCON
3369 //sbit at 0x98 RI0 ;
3370 //sbit at 0x99 TI0 ;
3371 //sbit at 0x9A RB8 ;
3372 //sbit at 0x9B TB8 ;
3373 //sbit at 0x9C REN ;
3374 //sbit at 0x9D SM2 ;
3375 //sbit at 0x9E SM1 ;
3376 //sbit at 0x9F SM0 ;
3379 #ifdef S0CON__SM0__SM1__SM20__REN0__TB80__RB80__TI0__RI0
3380 #undef S0CON__SM0__SM1__SM20__REN0__TB80__RB80__TI0__RI0
3381 // serial channel 0 buffer register SAB80517 specific(same as stock SCON)
3395 sfr at 0xAA S0RELL ; // serial channel 0 reload register low byte SAB80517 specific
3400 sfr at 0xBA S0RELH ; // serial channel 0 reload register high byte SAB80517 specific
3403 #ifdef S1ADR__x__x__x__x__x__x__x__GC
3404 #undef S1ADR__x__x__x__x__x__x__x__GC
3405 sfr at 0xDB S1ADR ; // Serial 1 address, P80C552 specific
3406 // Not directly accessible Bits.
3412 sfr at 0x9C S1BUF ; // serial channel 1 buffer register SAB80517 specific
3415 #ifdef S1CON_AT_0X9B
3416 #undef S1CON_AT_0X9B
3417 sfr at 0x9B S1CON ; // serial channel 1 control register SAB80517 specific
3420 #ifdef S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0
3421 #undef S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0
3422 sfr at 0xD8 S1CON ; // Serial 1 control, P80C552 specific
3423 sfr at 0xD8 SICON ; // sometimes called SICON
3435 #ifdef S1DAT_AT_0XDA
3436 #undef S1DAT_AT_0XDA
3437 sfr at 0xDA S1DAT ; // Serial 1 data, P80C552 specific
3438 sfr at 0xDA SIDAT ; // sometimes called SIDAT
3443 sfr at 0x9D S1RELL ; // serial channel 1 reload register low byte SAB80517 specific
3448 sfr at 0xBB S1RELH ; // serial channel 1 reload register high byte SAB80517 specific
3451 #ifdef S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x
3452 #undef S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x
3453 sfr at 0xD9 S1STA ; // Serial 1 status, P80C552 specific
3454 // Not directly accessible Bits.
3464 // DS80C320 specific
3465 sfr at 0xA9 SADDR0 ;
3470 // DS80C320 specific
3471 sfr at 0xAA SADDR1 ;
3476 // DS80C320 & DS80C390 specific
3477 sfr at 0xB9 SADEN0 ;
3482 // DS80C320 & DS80C390 specific
3483 sfr at 0xBA SADEN1 ;
3494 // DS80C320 & DS80C390 specific
3518 sbit at 0x9A RB8_0 ;
3519 sbit at 0x9B TB8_0 ;
3520 sbit at 0x9C REN_0 ;
3521 sbit at 0x9D SM2_0 ;
3522 sbit at 0x9E SM1_0 ;
3523 sbit at 0x9F SM0_0 ;
3525 sbit at 0x9F SM0_FE_0 ;
3530 // DS80C320 - 80C390 specific
3535 sbit at 0xC2 RB8_1 ;
3536 sbit at 0xC3 TB8_1 ;
3537 sbit at 0xC4 REN_1 ;
3538 sbit at 0xC5 SM2_1 ;
3539 sbit at 0xC6 SM1_1 ;
3540 sbit at 0xC7 SM0_1 ;
3542 sbit at 0xC7 SM0_FE_1 ;
3552 sfr at 0xD5 SPCR ; // AT89S53 specific
3553 // Not directly accesible bits
3566 sfr at 0x86 SPDR ; // AT89S53 specific
3567 // Not directly accesible bits
3580 sfr at 0xAA SPSR ; // AT89S53 specific
3581 // Not directly accesible bits
3588 sfr at 0xBA SRELH ; // Baudrate generator reload high
3593 sfr at 0xAA SRELL ; // Baudrate generator reload low
3596 #ifdef STATUS__PIP__HIP__LIP__x__x__x__x__x
3597 #undef STATUS__PIP__HIP__LIP__x__x__x__x__x
3598 // DS80C320 specific
3599 sfr at 0xC5 STATUS ;
3600 // Not directly accessible Bits. DS80C320 specific
3606 #ifdef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
3607 #undef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
3608 sfr at 0xC5 STATUS ; // DS80C390 specific
3609 // Not directly accessible Bits.
3619 #ifdef STATUS__PIS2__PIS1__PIS0__x__SPTA1__SPRA1__SPTA0__SPRA0
3620 #undef STATUS__PIS2__PIS1__PIS0__x__SPTA1__SPRA1__SPTA0__SPRA0
3621 sfr at 0xC5 STATUS ; // DS89C420 specific
3622 // Not directly accessible Bits.
3632 #ifdef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
3633 #undef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
3634 sfr at 0xC5 STATUS ; // DS80C390 specific
3635 // Not directly accessible Bits.
3645 #ifdef STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
3646 #undef STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
3647 sfr at 0xC5 STATUS ; // DS87C520 & DS83520specific
3648 // Not directly accessible Bits.
3659 #ifdef STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF
3660 #undef STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF
3661 sfr at 0xDA STATUS ; // DS5001specific
3662 // Not directly accessible Bits.
3673 #ifdef STE__TG47__TG46__SP45__SP44__SP43__SP42__SP41__SP40
3674 #undef STE__TG47__TG46__SP45__SP44__SP43__SP42__SP41__SP40
3675 sfr at 0xEE STE ; // Set enable, P80C552 specific
3676 // Not directly accessible Bits.
3689 sfr at 0xB1 SYSCON ; // XRAM Controller Access Control
3691 #define SYSCON_XMAP0 0x01
3692 #define SYSCON_XMAP1 0x02
3693 #define SYSCON_RMAP 0x10
3694 #define SYSCON_EALE 0x20
3697 #ifdef T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
3698 #undef T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
3700 // Definitions for the 8052 compatible microcontrollers.
3702 sbit at 0xC8 CP_RL2 ;
3705 sbit at 0xCB EXEN2 ;
3711 sbit at 0xC8 T2CON_0 ;
3712 sbit at 0xC9 T2CON_1 ;
3713 sbit at 0xCA T2CON_2 ;
3714 sbit at 0xCB T2CON_3 ;
3715 sbit at 0xCC T2CON_4 ;
3716 sbit at 0xCD T2CON_5 ;
3717 sbit at 0xCE T2CON_6 ;
3718 sbit at 0xCF T2CON_7 ;
3721 #ifdef T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
3722 #undef T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
3724 // Definitions for the Infineon / Siemens SAB80515, SAB80515A, SAB80517
3735 sbit at 0xC8 T2CON_0 ;
3736 sbit at 0xC9 T2CON_1 ;
3737 sbit at 0xCA T2CON_2 ;
3738 sbit at 0xCB T2CON_3 ;
3739 sbit at 0xCC T2CON_4 ;
3740 sbit at 0xCD T2CON_5 ;
3741 sbit at 0xCE T2CON_6 ;
3742 sbit at 0xCF T2CON_7 ;
3745 #ifdef T2MOD__x__x__x__D13T1__D13T2__x__T2OE__DCEN
3746 #undef T2MOD__x__x__x__D13T1__D13T2__x__T2OE__DCEN
3747 // Definitions for the timer/counter 2 of the Atmel & Dallas microcontrollers
3749 // Not not directly accessible T2MOD bits
3756 #ifdef T2MOD__x__x__x__x__x__x__T2OE__DCEN
3757 #undef T2MOD__x__x__x__x__x__x__T2OE__DCEN
3758 // Definitions for the timer/counter 2 of the Atmel 89x52 microcontroller
3760 // Not not directly accessible T2MOD bits
3770 sfr at 0xFF T3 ; // Timer 3, P80C552 specific
3775 // DS500x, DS80C320 & DS80C390 specific
3826 // Not directly accessible TMOD bits
3830 #define T0_GATE 0x08
3834 #define T1_GATE 0x80
3836 #define T0_MASK 0x0F
3837 #define T1_MASK 0xF0
3840 #ifdef TM2CON__T2IS1__T2IS0__T2ER__T2B0__T2P1__T2P0__T2MS1__T2MS0
3841 #undef TM2CON__T2IS1__T2IS0__T2ER__T2B0__T2P1__T2P0__T2MS1__T2MS0
3842 sfr at 0xEA TM2CON ; // Timer 2 control, P80C552 specific
3843 // Not directly accessible Bits.
3854 #ifdef TM2IR__T20V__CMI2__CMI1__CMI0__CTI3__CTI2__CTI1__CTI0
3855 #undef TM2IR__T20V__CMI2__CMI1__CMI0__CTI3__CTI2__CTI1__CTI0
3856 sfr at 0xC8 TM2IR ; // Timer 2 int flag reg, P80C552 specific
3870 sfr at 0xED TMH2 ; // Timer high 2, P80C552 specific
3875 sfr at 0xEC TML2 ; // Timer low 2, P80C552 specific
3880 sfr at 0x96 WCON ; // AT89S53 specific
3881 // Not directly accesible bits
3892 // DS80C320 - 390, DS89C420, etc. specific
3902 sbit at 0xDF SMOD_1 ;
3908 #define WDRPRG_S0 0x01
3909 #define WDRPRG_S1 0x02
3910 #define WDRPRG_S2 0x04
3915 sfr at 0x86 WDTREL ; // Watchdof Timer reload register
3925 sfr at 0x91 XPAGE ; // Page Address Register for Extended On-Chip Ram - Infineon / Siemens SAB80515A specific
3928 /////////////////////////
3929 /// Interrupt vectors ///
3930 /////////////////////////
3932 // Interrupt numbers: address = (number * 8) + 3
3933 #define IE0_VECTOR 0 // 0x03 external interrupt 0
3934 #define TF0_VECTOR 1 // 0x0b timer 0
3935 #define IE1_VECTOR 2 // 0x13 external interrupt 1
3936 #define TF1_VECTOR 3 // 0x1b timer 1
3937 #define SI0_VECTOR 4 // 0x23 serial port 0
3939 #ifdef MICROCONTROLLER_AT89S53
3940 #define TF2_VECTOR 5 /* 0x2B timer 2 */
3941 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
3944 #ifdef MICROCONTROLLER_AT89X52
3945 #define TF2_VECTOR 5 /* 0x2B timer 2 */
3946 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
3949 #ifdef MICROCONTROLLER_AT89X55
3950 #define TF2_VECTOR 5 /* 0x2B timer 2 */
3951 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
3954 #ifdef MICROCONTROLLER_DS5000
3955 #define PFW_VECTOR 5 /* 0x2B */
3958 #ifdef MICROCONTROLLER_DS5001
3959 #define PFW_VECTOR 5 /* 0x2B */
3962 #ifdef MICROCONTROLLER_DS80C32X
3963 #define TF2_VECTOR 5 /* 0x2B */
3964 #define PFI_VECTOR 6 /* 0x33 */
3965 #define SIO1_VECTOR 7 /* 0x3B */
3966 #define IE2_VECTOR 8 /* 0x43 */
3967 #define IE3_VECTOR 9 /* 0x4B */
3968 #define IE4_VECTOR 10 /* 0x53 */
3969 #define IE5_VECTOR 11 /* 0x5B */
3970 #define WDI_VECTOR 12 /* 0x63 */
3973 #ifdef MICROCONTROLLER_DS8XC520
3974 #define TF2_VECTOR 5 /* 0x2B */
3975 #define PFI_VECTOR 6 /* 0x33 */
3976 #define SIO1_VECTOR 7 /* 0x3B */
3977 #define IE2_VECTOR 8 /* 0x43 */
3978 #define IE3_VECTOR 9 /* 0x4B */
3979 #define IE4_VECTOR 10 /* 0x53 */
3980 #define IE5_VECTOR 11 /* 0x5B */
3981 #define WDI_VECTOR 12 /* 0x63 */
3984 #ifdef MICROCONTROLLER_P80C552
3985 #define SIO1_VECTOR 5 // 0x2B SIO1 (I2C)
3986 #define CT0_VECTOR 6 // 0x33 T2 capture 0
3987 #define CT1_VECTOR 7 // 0x3B T2 capture 1
3988 #define CT2_VECTOR 8 // 0x43 T2 capture 2
3989 #define CT3_VECTOR 9 // 0x4B T2 capture 3
3990 #define ADC_VECTOR 10 // 0x53 ADC completion
3991 #define CM0_VECTOR 11 // 0x5B T2 compare 0
3992 #define CM1_VECTOR 12 // 0x63 T2 compare 1
3993 #define CM2_VECTOR 13 // 0x6B T2 compare 2
3994 #define TF2_VECTOR 14 // 0x73 T2 overflow
3997 #ifdef MICROCONTROLLER_SAB80515
3998 #define TF2_VECTOR 5 // 0x2B timer 2
3999 #define EX2_VECTOR 5 // 0x2B external interrupt 2
4000 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt
4001 #define IEX2_VECTOR 9 // 0x4B external interrupt 2
4002 #define IEX3_VECTOR 10 // 0x53 external interrupt 3
4003 #define IEX4_VECTOR 11 // 0x5B external interrupt 4
4004 #define IEX5_VECTOR 12 // 0x63 external interrupt 5
4005 #define IEX6_VECTOR 13 // 0x6B external interrupt 6
4008 #ifdef MICROCONTROLLER_SAB80515A
4009 #define TF2_VECTOR 5 // 0x2B timer 2
4010 #define EX2_VECTOR 5 // 0x2B external interrupt 2
4011 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt
4012 #define IEX2_VECTOR 9 // 0x4B external interrupt 2
4013 #define IEX3_VECTOR 10 // 0x53 external interrupt 3
4014 #define IEX4_VECTOR 11 // 0x5B external interrupt 4
4015 #define IEX5_VECTOR 12 // 0x63 external interrupt 5
4016 #define IEX6_VECTOR 13 // 0x6B external interrupt 6
4019 #ifdef MICROCONTROLLER_SAB80517
4020 #define TF2_VECTOR 5 // 0x2B timer 2
4021 #define EX2_VECTOR 5 // 0x2B external interrupt 2
4022 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt
4023 #define IEX2_VECTOR 9 // 0x4B external interrupt 2
4024 #define IEX3_VECTOR 10 // 0x53 external interrupt 3
4025 #define IEX4_VECTOR 11 // 0x5B external interrupt 4
4026 #define IEX5_VECTOR 12 // 0x63 external interrupt 5
4027 #define IEX6_VECTOR 13 // 0x6B external interrupt 6
4030 #define SI1_VECTOR 16 // 0x83 serial port 1
4033 #define COMPARE_VECTOR 19 // 0x9B compare
4036 #ifdef MICROCONTORLLER_T89C51RD2
4037 #define TF2_VECTOR 5 /* 0x2B timer 2 */
4038 #define PCA_VECTOR 6 /* 0x33 Programmable Counetr Array interrupt */
4039 #endif /* MICROCONTORLLER_T89C51RD2 */
4041 #endif // End of the header -> #ifndef MCS51REG_H