1 /*-------------------------------------------------------------------------
2 Register Declarations for the mcs51 compatible microcontrollers
4 Written By - Bela Torok / bela.torok@kssg.ch (November 2000)
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the
8 Free Software Foundation; either version 2, or (at your option) any
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 In other words, you are welcome to use, share and improve this program.
21 You are forbidden to forbid anyone else to use, share and improve
22 what you give them. Help stamp out software-hoarding!
27 Version 1.0 Nov 2, 2000 - B. Torok / bela.torok@kssg.ch
28 Initial release, supported microcontrollers:
29 8051, 8052, Atmel AT89C1051, AT89C2051, AT89C4051,
30 Infineon / Siemens SAB80515, SAB80535, SAB80515A
32 Version 1.0.1 (Nov 3, 2000)
33 SAB80515A definitions revised by Michael Schmitt / michael.schmitt@t-online.de
35 Version 1.0.2 (Nov 6, 2000)
36 T2CON bug corrected 8052 and SABX microcontrollers have different T2CONs
37 Support for the Atmel AT89C52, AT80LV52, AT89C55, AT80LV55
38 Support for the Dallas DS80C320 and DS80C323
39 B. Torok / bela.torok@kssg.ch
41 Version 1.0.3 (Nov 7, 2000)
42 SAB80517 definitions added by Michael Schmitt / michael.schmitt@t-online.de
43 Dallas AT89S53 definitions added by B. Torok / bela.torok@kssg.ch
44 Dallas DS87C520 and DS83C520 definitions added by B. Torok / bela.torok@kssg.ch
46 Version 1.0.4 (Nov 9, 2000)
47 To simplify the identication of registers, a large number of definitios
48 were renamed. Long register names now (hopefully) clearly define the
49 function of the registers.
50 Dallas DS89C420 definitions added by B. Torok / bela.torok@kssg.ch
52 Version 1.0.5 (Dec 15, 2000)
53 Definitions added: #ifdef MCS51REG_EXTERNAL_ROM
54 #ifdef MCS51REG_EXTERNAL_RAM
55 #ifndef MCS51REG_DISABLE_WARNINGS
58 Version 1.0.6 (March 10, 2001)
59 Support for the Dallas DS5000 & DS2250
60 Support for the Dallas DS5001 & DS2251
61 Support for the Dallas DS80C390
62 microcontrollers - B. Torok / bela.torok@kssg.ch
64 Version 1.0.7 (June 7, 2001)
65 #ifndef MCS51REG_DISABLE_WARNINGS removed
66 #ifdef MCS51REG_DISABLE_WARNINGS added - B. Torok / bela.torok@kssg.ch
67 Support for the Philips P80C552 added - Bernhard Held / Bernhard.Held@otelo-online.de
69 Version 1.0.8 (Feb 28, 2002)
70 Dallas DS89C420 definitions corrected by B. Torok / bela.torok@kssg.ch
71 Revised by lanius@ewetel.net
74 Adding support for additional microcontrollers:
75 -----------------------------------------------
77 1. Don't modify this file!!!
79 2. Insert your code in a separate file e.g.: mcs51reg_update.h and include
80 this after the #define HEADER_MCS51REG statement in this file
82 3. The mcs51reg_update.h file should contain following definitions:
84 a. An entry with the inventory of the register set of the
85 microcontroller in the "Describe microcontrollers" section.
87 b. If necessary add entry(s) in for registers not defined in this file
89 c. Define interrupt vectors
91 4. Send me the file mcs51reg_update.h ( bela.torok@kssg.ch ).
92 I'm going to verify/merge new definitions to this file.
95 Microcontroller support:
97 Use one of the following options:
99 1. use #include <mcs51reg.h> in your program & define MICROCONTROLLER_XXXX in your makefile.
101 2. use following definitions prior the
102 #include <mcs51reg.h> line in your program:
104 #define MICROCONTROLLER_8052 -> 8052 type microcontroller
106 #define MICROCONTROLLER_AT89CX051 -> Atmel AT89C1051, AT89C2051 and AT89C4051 microcontrollers
109 Use only one of the following definitions!!!
111 Supported Microcontrollers:
114 MICROCONTROLLER_8051 8051
115 MICROCONTROLLER_8052 8052
116 MICROCONTROLLER_AT89CX051 Atmel AT89C1051, AT89C2051 and AT89C4051
117 MICROCONTROLLER_AT89S53 Atmel AT89S53 microcontroller
118 MICROCONTROLLER_AT89X52 Atmel AT89C52 and AT80LV52 microcontrollers
119 MICROCONTROLLER_AT89X55 Atmel AT89C55 and AT80LV55 microcontrollers
120 MICROCONTROLLER_DS5000 Dallas DS5000 & DS2250 microcontroller
121 MICROCONTROLLER_DS5001 Dallas DS5001 & DS2251 microcontroller
122 MICROCONTROLLER_DS80C32X Dallas DS80C320 and DS80C323 microcontrollers
123 MICROCONTROLLER_DS80C390 Dallas DS80C390 microcontroller
124 MICROCONTROLLER_DS89C420 Dallas DS89C420 microcontroller
125 MICROCONTROLLER_DS8XC520 Dallas DS87C520 and DS83C520 microcontrollers
126 MICROCONTROLLER_P80C552 Philips P80C552
127 MICROCONTROLLER_SAB80515 Infineon / Siemens SAB80515 & SAB80535
128 MICROCONTROLLER_SAB80515A Infineon / Siemens SAB80515A
129 MICROCONTROLLER_SAB80517 Infineon / Siemens SAB80517
131 Additional definitions (use them prior the #include mcs51reg.h statement):
133 Ports P0 & P2 are not available for the programmer if external ROM used.
134 Use statement "#define MCS51REG_EXTERNAL_RAM" to undefine P0 & P2.
136 Ports P0, P2, P3_6, WR, P3_7 & RD are not available for the programmer if
137 external RAM is used.
138 Use statement "#define MCS51REG_EXTERNAL_RAM" to undefine P0, P2,
141 #define MCS51REG_ENABLE_WARNINGS -> enable warnings
143 -----------------------------------------------------------------------*/
146 #ifndef HEADER_MCS51REG
147 #define HEADER_MCS51REG
149 ///////////////////////////////////////////////////////
150 /// Insert header here (for developers only) ///
151 /// remove "//" from the begining of the next line ///
152 /// #include "mcs51reg_update.h" ///
153 ///////////////////////////////////////////////////////
155 //////////////////////////////////
156 /// Describe microcontrollers ///
157 /// (inventory of registers) ///
158 //////////////////////////////////
160 // definitions for the 8051
161 #ifdef MICROCONTROLLER_8051
162 #ifdef MICROCONTROLLER_DEFINED
163 #define MCS51REG_ERROR
165 #ifndef MICROCONTROLLER_DEFINED
166 #define MICROCONTROLLER_DEFINED
168 #ifdef MCS51REG_ENABLE_WARNINGS
169 #warning Selected HW: 8051
175 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
186 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
188 #define IP__x__x__x__PS__PT1__PX1__PT0__PX0
193 // end of definitions for the 8051
196 // definitions for the 8052 microcontroller
197 #ifdef MICROCONTROLLER_8052
198 #ifdef MICROCONTROLLER_DEFINED
199 #define MCS51REG_ERROR
201 #ifndef MICROCONTROLLER_DEFINED
202 #define MICROCONTROLLER_DEFINED
204 #ifdef MCS51REG_ENABLE_WARNINGS
205 #warning Selected HW: 8052
212 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
223 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
225 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
229 // 8052 specific registers
230 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
236 // end of definitions for the 8052 microcontroller
239 // definitionsons for the Atmel
240 // AT89C1051, AT89C2051 and AT89C4051 microcontrollers
241 #ifdef MICROCONTROLLER_AT89CX051
242 #ifdef MICROCONTROLLER_DEFINED
243 #define MCS51REG_ERROR
245 #ifndef MICROCONTROLLER_DEFINED
246 #define MICROCONTROLLER_DEFINED
248 #ifdef MCS51REG_ENABLE_WARNINGS
249 #warning Selected HW: Atmel AT89Cx051
251 // 8051 register set without P0 & P2
255 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
265 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
267 #define IP__x__x__x__PS__PT1__PX1__PT0__PX0
272 // end of definitionsons for the Atmel
273 // AT89C1051, AT89C2051 and AT89C4051 microcontrollers
276 // definitions for the Atmel AT89S53
277 #ifdef MICROCONTROLLER_AT89S53
278 #ifdef MICROCONTROLLER_DEFINED
279 #define MCS51REG_ERROR
281 #ifndef MICROCONTROLLER_DEFINED
282 #define MICROCONTROLLER_DEFINED
284 #ifdef MCS51REG_ENABLE_WARNINGS
285 #warning Selected HW: AT89S53
292 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
303 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
305 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
309 // 8052 specific registers
310 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
315 // AT89S53 specific register
316 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
317 #define P1_EXT__x__x__x__x__x__x__T2EX__T2
325 // end of definitions for the Atmel AT89S53 microcontroller
328 // definitions for the Atmel AT89C52 and AT89LV52 microcontrollers
329 #ifdef MICROCONTROLLER_AT89X52
330 #ifdef MICROCONTROLLER_DEFINED
331 #define MCS51REG_ERROR
333 #ifndef MICROCONTROLLER_DEFINED
334 #define MICROCONTROLLER_DEFINED
336 #ifdef MCS51REG_ENABLE_WARNINGS
337 #warning Selected HW: AT89C52 or AT89LV52
344 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
355 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
357 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
361 // 8052 specific registers
362 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
367 // AT89X55 specific register
368 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
369 #define P1_EXT__x__x__x__x__x__x__T2EX__T2
371 // end of definitions for the Atmel AT89C52 and AT89LV52 microcontrollers
374 // definitions for the Atmel AT89C55 and AT89LV55 microcontrollers
375 #ifdef MICROCONTROLLER_AT89X55
376 #ifdef MICROCONTROLLER_DEFINED
377 #define MCS51REG_ERROR
379 #ifndef MICROCONTROLLER_DEFINED
380 #define MICROCONTROLLER_DEFINED
382 #ifdef MCS51REG_ENABLE_WARNINGS
383 #warning Selected HW: AT89C55 or AT89LV55
390 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
401 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
403 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
407 // 8052 specific registers
408 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
413 // AT89X55 specific register
414 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
415 #define P1_EXT__x__x__x__x__x__x__T2EX__T2
417 // end of definitions for the Atmel AT89C55 and AT89LV55 microcontrollers
420 // definitions for the Dallas DS5000
421 #ifdef MICROCONTROLLER_DS5000
422 #ifdef MICROCONTROLLER_DEFINED
423 #define MCS51REG_ERROR
425 #ifndef MICROCONTROLLER_DEFINED
426 #define MICROCONTROLLER_DEFINED
428 #ifdef MCS51REG_ENABLE_WARNINGS
429 #warning Selected HW: DS5000
435 #define PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
446 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
448 #define IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
449 #define MCON__SL__PAA__ECE2__RA32_8__PA0__PA1__PA2__PA3
455 // end of definitions for the Dallas DS5000
458 // definitions for the Dallas DS5001
459 #ifdef MICROCONTROLLER_DS5001
460 #ifdef MICROCONTROLLER_DEFINED
461 #define MCS51REG_ERROR
463 #ifndef MICROCONTROLLER_DEFINED
464 #define MICROCONTROLLER_DEFINED
466 #ifdef MCS51REG_ENABLE_WARNINGS
467 #warning Selected HW: DS5001
473 #define PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
484 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
486 #define IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
490 #define MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL
495 #define STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF
499 // end of definitions for the Dallas DS5001
502 // definitions for the Dallas DS80C320 and DS80C323 microcontrollers
503 #ifdef MICROCONTROLLER_DS80C32X
504 #ifdef MICROCONTROLLER_DEFINED
505 #define MCS51REG_ERROR
507 #ifndef MICROCONTROLLER_DEFINED
508 #define MICROCONTROLLER_DEFINED
510 #ifdef MCS51REG_ENABLE_WARNINGS
511 #warning Selected HW: Dallas DS80C320 or DS80C323
518 #define PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
530 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
532 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
536 // 8052 specific registers
537 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
542 // DS80C320 specific register
545 #define DPS__x__x__x__x__x__x__x__SEL
547 #define EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
554 #define STATUS__PIP__HIP__LIP__x__x__x__x__x
556 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
557 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
559 #define EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
560 #define EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2
562 // end of definitions for the Dallas DS80C320 and DS80C323 microcontrollers
565 // definitions for the Dallas DS80C390
566 #ifdef MICROCONTROLLER_DS80C390
567 #ifdef MICROCONTROLLER_DEFINED
568 #define MCS51REG_ERROR
570 #ifndef MICROCONTROLLER_DEFINED
571 #define MICROCONTROLLER_DEFINED
573 #ifdef MCS51REG_ENABLE_WARNINGS
574 #warning Selected HW: Dallas DS80C390
581 #define PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
593 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
595 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
599 // 8052 specific registers
600 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
605 // DS80C390 specific register
609 #define DPS__ID1__ID0__TSL__x__x__x__x__SEL
611 #define EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
619 #define ACON__x__x__x__x__x__SA__AM1__AM0
650 #define PMR__CD1__CD0__SWB__CTM__4X_2X__ALEOFF__x__x
651 #define STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
652 #define MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0
654 #define T2MOD__x__x__x__D13T1__D13T2__x__T2OE__DCEN
671 #define EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2
682 #define EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
689 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
691 // end of definitions for the Dallas DS80C390
693 // definitions for the Dallas DS89C420 microcontroller
694 #ifdef MICROCONTROLLER_DS89C420
695 #ifdef MICROCONTROLLER_DEFINED
696 #define MCS51REG_ERROR
698 #ifndef MICROCONTROLLER_DEFINED
699 #define MICROCONTROLLER_DEFINED
701 #ifdef MCS51REG_ENABLE_WARNINGS
702 #warning Selected HW: Dallas DS89C420
709 #define PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
721 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
723 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
727 // 8052 specific registers
728 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
733 // DS8XC420 specific registers
734 #define ACON__PAGEE__PAGES1__PAGES0__x__x__x__x__x
737 #define DPS__ID1__ID0__TSL__AID__x__x__x__SEL
740 #define IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
741 #define IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
742 #define EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
743 #define PMR__CD1__CD0__SWB__CTM__4X_2X__ALEON__DME1__DME0
750 #define STATUS__PIS2__PIS1__PIS0__x__SPTA1__SPRA1__SPTA0__SPRA0
752 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
753 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
754 #define ROMSIZE__x__x__x__x__PRAME__RMS2__RMS1__RMS0
756 #define EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
757 #define EIP0__x__x__x__LPWDI__LPX5__LPX4__LPX3__LPX2
758 #define EIP1__x__x__x__MPWDI__MPX5__MPX4__MPX3__MPX2
759 #define FCNTL__FBUSY__FERR__x__x__FC3__FC2__FC1__FC0
761 // end of definitions for the Dallas DS89C420 microcontroller
763 // definitions for the Dallas DS87C520 and DS83C520 microcontrollers
764 #ifdef MICROCONTROLLER_DS8XC520
765 #ifdef MICROCONTROLLER_DEFINED
766 #define MCS51REG_ERROR
768 #ifndef MICROCONTROLLER_DEFINED
769 #define MICROCONTROLLER_DEFINED
771 #ifdef MCS51REG_ENABLE_WARNINGS
772 #warning Selected HW: Dallas DS87C520 or DS85C520
779 #define PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
791 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
793 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
797 // 8052 specific registers
798 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
803 // DS8XC520 specific registers
806 #define DPS__x__x__x__x__x__x__x__SEL
808 #define EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
809 #define PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1__DME0
816 #define STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
818 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
819 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
821 #define ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0
824 #define EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
825 #define EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2
827 // end of definitions for the Dallas DS87C520 and DS83C520 microcontrollers
830 // definitions for the Philips P80C552 microcontroller
831 #ifdef MICROCONTROLLER_P80C552
832 #ifdef MICROCONTROLLER_DEFINED
833 #define MCS51REG_ERROR
835 #ifndef MICROCONTROLLER_DEFINED
836 #define MICROCONTROLLER_DEFINED
838 #ifdef MCS51REG_ENABLE_WARNINGS
839 #warning Selected HW: Philips P80C552
846 #define PCON__SMOD__x__x__WLE__GF1__GF0__PD__IDL
857 #define IE__EA__EAD__ES1__ES0__ET1__EX1__ET0__EX0
859 #define IP__x__PAD__PS1__PS0__PT1__PX1__PT0__PX0
863 // P80C552 specific register-names
864 #define S0BUF // same as SBUF, set in mcs51reg.h
865 #define S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI
866 // P80C552 specific registers
868 #define ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0
869 #define CTCON__CTN3__CTP3__CTN2__CTP2__CTN1__CTP1__CTN0__CTP0
884 #define IEN1__ET2__ECM2__ECM1__ECM0__ECT3__ECT2__ECT1__ECT0
885 #define IP1__PT2__PCM2__PCM1__PCM0__PCT3__PCT2__PCT1__PCT0
889 #define P1_EXT__SDA__SCL__RT2__T2__CT3I__CT2I__CT1I__CT0I
892 #define RTE__TP47__TP46__RP45__RP44__RP43__RP42__RP41__RP40
893 #define S1ADR__x__x__x__x__x__x__x__GC
894 #define S1DAT_AT_0XDA
895 #define S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x
896 #define S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0
897 #define STE__TG47__TG46__SP45__SP44__SP43__SP42__SP41__SP40
900 #define TM2CON__T2IS1__T2IS0__T2ER__T2B0__T2P1__T2P0__T2MS1__T2MS0
901 #define TM2IR__T20V__CMI2__CMI1__CMI0__CTI3__CTI2__CTI1__CTI0
904 // end of definitions for the Philips P80C552 microcontroller
907 // definitions for the Infineon / Siemens SAB80515 & SAB80535
908 #ifdef MICROCONTROLLER_SAB80515
909 #ifdef MICROCONTROLLER_DEFINED
910 #define MCS51REG_ERROR
912 #ifndef MICROCONTROLLER_DEFINED
913 #define MICROCONTROLLER_DEFINED
915 #ifdef MCS51REG_ENABLE_WARNINGS
916 #warning Selected HW: Infineon / Siemens SAB80515 & SAB80535
918 // 8051 register set without IP
923 #define PCON__SMOD__x__x__x__x__x__x__x
934 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
939 // SAB80515 specific registers
940 #define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
941 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
942 #define IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
951 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
958 #define DAPR__SAB80515
962 // end of definitions for the Infineon / Siemens SAB80515
965 // definitions for the Infineon / Siemens SAB80515A
966 #ifdef MICROCONTROLLER_SAB80515A
967 #ifdef MICROCONTROLLER_DEFINED
968 #define MCS51REG_ERROR
970 #ifndef MICROCONTROLLER_DEFINED
971 #define MICROCONTROLLER_DEFINED
973 #ifdef MCS51REG_ENABLE_WARNINGS
974 #warning Selected HW: Infineon / Siemens SAB80515A
976 // 8051 register set without IP
981 #define PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
992 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
997 // SAB80515A specific registers
998 #define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
999 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
1000 #define IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
1001 #define IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
1010 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
1027 // end of definitions for the Infineon / Siemens SAB80515A
1030 // definitions for the Infineon / Siemens SAB80517
1031 #ifdef MICROCONTROLLER_SAB80517
1032 #ifdef MICROCONTROLLER_DEFINED
1033 #define MCS51REG_ERROR
1035 #ifndef MICROCONTROLLER_DEFINED
1036 #define MICROCONTROLLER_DEFINED
1038 #ifdef MCS51REG_ENABLE_WARNINGS
1039 #warning Selected HW: Infineon / Siemens SAB80517
1041 // 8051 register set without IP, SCON & SBUF
1046 #define PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
1057 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
1062 // SAB80517 specific registers
1063 #define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
1064 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
1065 #define IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
1066 #define IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
1067 #define IEN2__SAB80517
1097 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
1100 #define CTCOM_AT_0XE1
1108 #define DAPR__SAB80517
1123 #define S0CON__SM0__SM1__SM20__REN0__TB80__RB80__TI0__RI0
1127 #define S1CON_AT_0X9B
1134 // end of definitions for the Infineon / Siemens SAB80517
1137 /////////////////////////////////////////////////////////
1138 /// don't specify microcontrollers below this line! ///
1139 /////////////////////////////////////////////////////////
1142 // default microcontroller -> 8051
1143 // use default if no microcontroller specified
1144 #ifndef MICROCONTROLLER_DEFINED
1145 #define MICROCONTROLLER_DEFINED
1146 #ifdef MCS51REG_ENABLE_WARNINGS
1147 #warning No microcontroller defined!
1148 #warning Code generated for the 8051
1150 // 8051 register set
1155 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
1166 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
1168 #define IP__x__x__x__PS__PT1__PX1__PT0__PX0
1173 // end of definitions for the default microcontroller
1176 #ifdef MCS51REG_ERROR
1177 #error Two or more microcontrollers defined!
1180 #ifdef MCS51REG_EXTERNAL_ROM
1181 #ifndef MCS51REG_UNDEFINE_P0
1182 #define MCS51REG_UNDEFINE_P0
1184 #ifndef MCS51REG_UNDEFINE_P2
1185 #define MCS51REG_UNDEFINE_P2
1189 #ifdef MCS51REG_EXTERNAL_RAM
1190 #ifndef MCS51REG_UNDEFINE_P0
1191 #define MCS51REG_UNDEFINE_P0
1193 #ifndef MCS51REG_UNDEFINE_P2
1194 #define MCS51REG_UNDEFINE_P2
1198 #ifdef MCS51REG_UNDEFINE_P0
1202 #ifdef MCS51REG_UNDEFINE_P2
1206 ////////////////////////////////
1207 /// Register definitions ///
1208 /// (In alphabetical order) ///
1209 ////////////////////////////////
1216 #ifdef ACON__PAGEE__PAGES1__PAGES0__x__x__x__x__x
1217 #undef ACON__PAGEE__PAGES1__PAGES0__x__x__x__x__x
1218 sfr at 0x9D ACON ; // DS89C420 specific
1219 // Not directly accessible bits
1225 #ifdef ACON__x__x__x__x__x__SA__AM1__AM0
1226 #undef ACON__x__x__x__x__x__SA__AM1__AM0
1227 sfr at 0x9D ACON ; // DS89C390 specific
1228 // Not directly accessible bits
1236 sfr at 0xC6 ADCH ; // A/D converter high
1241 sfr at 0xD8 ADCON ; // A/D-converter control register SAB80515 specific
1252 // ADCON0 ... Infineon / Siemens also called this register ADCON in the User Manual
1255 sfr at 0xD8 ADCON0 ; // A/D-converter control register 0 SAB80515A &
1256 // Bit registers // SAB80517 specific
1265 // Not directly accessible ADCON0
1266 #define ADCON0_MX0 0x01
1267 #define ADCON0_MX1 0x02
1268 #define ADCON0_MX2 0x04
1269 #define ADCON0_ADM 0x08
1270 #define ADCON0_BSY 0x10
1271 #define ADCON0_ADEX 0x20
1272 #define ADCON0_CLK 0x40
1273 #define ADCON0_BD 0x80
1278 sfr at 0xDC ADCON1 ; // A/D-converter control register 1 SAB80515A & SAB80517 specific
1279 // Not directly accessible ADCON1
1280 #define ADCON1_MX0 0x01
1281 #define ADCON1_MX1 0x02
1282 #define ADCON1_MX2 0x04
1283 #define ADCON1_ADCL 0x80
1286 #ifdef ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0
1287 #undef ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0
1288 sfr at 0xC5 ADCON ; // A/D control, P80C552 specific
1289 // Not directly accessible Bits.
1296 #define ADC_0 0x40 // different name as ADC0 in P5
1297 #define ADC_1 0x80 // different name as ADC1 in P5
1302 sfr at 0xD9 ADDAT ; // A/D-converter data register SAB80515 specific
1307 sfr at 0xD9 ADDATH ; // A/D data high byte SAB80515A specific
1312 sfr at 0xDA ADDATL ; // A/D data low byte SAB80515A specific
1317 sfr at 0xEF ARCON ; // arithmetic control register SAB80517
1322 sfr at 0x9C AP ; // DS80C390
1329 sbit at 0xF0 BREG_F0 ;
1330 sbit at 0xF1 BREG_F1 ;
1331 sbit at 0xF2 BREG_F2 ;
1332 sbit at 0xF3 BREG_F3 ;
1333 sbit at 0xF4 BREG_F4 ;
1334 sbit at 0xF5 BREG_F5 ;
1335 sbit at 0xF6 BREG_F6 ;
1336 sbit at 0xF7 BREG_F7 ;
1342 // Not directly accessible bits
1353 sfr at 0xA3 C0C ; // DS80C390 specific
1354 // Not directly accessible bits
1367 sfr at 0xA5 C0IR ; // DS80C390 specific
1368 // Not directly accessible bits
1381 sfr at 0xAB C0M1C ; // DS80C390 specific
1382 // Not directly accessible bits
1384 #define ROW_TIH 0x02
1395 sfr at 0xAC C0M2C ; // DS80C390 specific
1400 sfr at 0xAD C0M3C ; // DS80C390 specific
1405 sfr at 0xAE C0M4C ; // DS80C390 specific
1410 sfr at 0xAF C0M5C ; // DS80C390 specific
1415 sfr at 0xB3 C0M6C ; // DS80C390 specific
1420 sfr at 0xB4 C0M7C ; // DS80C390 specific
1425 sfr at 0xB5 C0M8C ; // DS80C390 specific
1430 sfr at 0xB6 C0M9C ; // DS80C390 specific
1435 sfr at 0xB7 C0M10C ; // DS80C390 specific
1440 sfr at 0xBB C0M11C ; // DS80C390 specific
1445 sfr at 0xBC C0M12C ; // DS80C390 specific
1450 sfr at 0xBD C0M13C ; // DS80C390 specific
1455 sfr at 0xBE C0M14C ; // DS80C390 specific
1460 sfr at 0xBF C0M15C ; // DS80C390 specific
1465 sfr at 0xA7 C0RE ; // DS80C390 specific
1470 sfr at 0x96 C0RMS0 ; // DS80C390 specific
1475 sfr at 0x97 C0RMS1 ; // DS80C390 specific
1480 sfr at 0xA4 C0S ; // DS80C390 specific
1481 // Not directly accessible bits
1488 #define EC96_128 0x40
1494 sfr at 0xA6 C0TE ; // DS80C390 specific
1499 sfr at 0x9E C0TMA0 ; // DS80C390 specific
1504 sfr at 0x9F C0TMA1 ; // DS80C390 specific
1509 sfr at 0xE3 C1C ; // DS80C390 specific
1510 // Not directly accessible bits
1523 sfr at 0xE5 C1IR ; // DS80C390 specific
1524 // Not directly accessible bits
1537 sfr at 0xE7 C1RE ; // DS80C390 specific
1542 sfr at 0xEB C1M1C ; // DS80C390 specific
1547 sfr at 0xEC C1M2C ; // DS80C390 specific
1552 sfr at 0xED C1M3C ; // DS80C390 specific
1557 sfr at 0xEE C1M4C ; // DS80C390 specific
1562 sfr at 0xEF C1M5C ; // DS80C390 specific
1567 sfr at 0xF3 C1M6C ; // DS80C390 specific
1572 sfr at 0xF4 C1M7C ; // DS80C390 specific
1577 sfr at 0xF5 C1M8C ; // DS80C390 specific
1582 sfr at 0xF6 C1M9C ; // DS80C390 specific
1587 sfr at 0xF7 C1M10C ; // DS80C390 specific
1592 sfr at 0xFB C1M11C ; // DS80C390 specific
1597 sfr at 0xFC C1M12C ; // DS80C390 specific
1602 sfr at 0xFD C1M13C ; // DS80C390 specific
1607 sfr at 0xFE C1M14C ; // DS80C390 specific
1612 sfr at 0xFF C1M15C ; // DS80C390 specific
1617 sfr at 0xE4 C1S ; // DS80C390 specific
1618 // Not directly accessible bits
1631 sfr at 0xE6 C1TE ; // DS80C390 specific
1636 sfr at 0xD6 C1RSM0 ; // DS80C390 specific
1641 sfr at 0xD7 C1RSM1 ; // DS80C390 specific
1646 sfr at 0xDE C1TMA0 ; // DS80C390 specific
1651 sfr at 0xDF C1TMA1 ; // DS80C390 specific
1656 sfr at 0xC9 CC4EN ; // compare/capture 4 enable register SAB80517 specific
1661 sfr at 0xC1 CCEN ; // compare/capture enable register SAB80515 specific
1666 sfr at 0xC3 CCH1 ; // compare/capture register 1, high byte SAB80515 specific
1671 sfr at 0xC5 CCH2 ; // compare/capture register 2, high byte SAB80515 specific
1676 sfr at 0xC7 CCH3 ; // compare/capture register 3, high byte SAB80515 specific
1681 sfr at 0xCF CCH4 ; // compare/capture register 4, high byte SAB80515 specific
1686 sfr at 0xC2 CCL1 ; // compare/capture register 1, low byte SAB80515 specific
1691 sfr at 0xC4 CCL2 ; // compare/capture register 2, low byte SAB80515 specific
1696 sfr at 0xC6 CCL3 ; // compare/capture register 3, low byte SAB80515 specific
1701 sfr at 0xCE CCL4 ; // compare/capture register 4, low byte SAB80515 specific
1706 sfr at 0x8E CKCON ; // DS80C320 & DS80C390 specific
1707 // Not directly accessible Bits.
1720 sfr at 0x96 CKMOD ; // DS89C420 specific
1721 // Not directly accessible Bits.
1729 sfr at 0xF6 CMEN ; // compare enable register SAB80517 specific
1734 sfr at 0xD3 CMH0 ; // compare register 0 high byte SAB80517 specific
1739 sfr at 0xD5 CMH1 ; // compare register 1 high byte SAB80517 specific
1744 sfr at 0xD7 CMH2 ; // compare register 2 high byte SAB80517 specific
1749 sfr at 0xE3 CMH3 ; // compare register 3 high byte SAB80517 specific
1754 sfr at 0xE5 CMH4 ; // compare register 4 high byte SAB80517 specific
1759 sfr at 0xE7 CMH5 ; // compare register 5 high byte SAB80517 specific
1764 sfr at 0xF3 CMH6 ; // compare register 6 high byte SAB80517 specific
1769 sfr at 0xF5 CMH7 ; // compare register 7 high byte SAB80517 specific
1774 sfr at 0xC9 CMH0 ; // Compare high 0, P80C552 specific
1779 sfr at 0xCA CMH1 ; // Compare high 1, P80C552 specific
1784 sfr at 0xCB CMH2 ; // Compare high 2, P80C552 specific
1789 sfr at 0xD2 CML0 ; // compare register 0 low byte SAB80517 specific
1794 sfr at 0xD4 CML1 ; // compare register 1 low byte SAB80517 specific
1799 sfr at 0xD6 CML2 ; // compare register 2 low byte SAB80517 specific
1804 sfr at 0xE2 CML3 ; // compare register 3 low byte SAB80517 specific
1809 sfr at 0xE4 CML4 ; // compare register 4 low byte SAB80517 specific
1814 sfr at 0xE6 CML5 ; // compare register 5 low byte SAB80517 specific
1819 sfr at 0xF2 CML6 ; // compare register 6 low byte SAB80517 specific
1824 sfr at 0xF4 CML7 ; // compare register 7 low byte SAB80517 specific
1829 sfr at 0xA9 CML0 ; // Compare low 0, P80C552 specific
1834 sfr at 0xAA CML1 ; // Compare low 1, P80C552 specific
1839 sfr at 0xAB CML2 ; // Compare low 2, P80C552 specific
1844 sfr at 0xF7 CMSEL ; // compare input select SAB80517
1849 sfr at 0xCE COR ; // Dallas DS80C390 specific
1862 sfr at 0xC1 CRC ; // Dallas DS5001 specific
1873 sfr at 0xCB CRCH ; // compare/reload/capture register, high byte SAB80515 specific
1878 sfr at 0xC3 CRCHIGH ; // DS5001 specific
1883 sfr at 0xCA CRCL ; // compare/reload/capture register, low byte SAB80515 specific
1888 sfr at 0xC2 CRCLOW ; // DS5001 specific
1891 #ifdef CTCOM_AT_0XE1
1892 #undef CTCOM_AT_0XE1
1893 sfr at 0xE1 CTCON ; // com.timer control register SAB80517
1896 #ifdef CTCON__CTN3__CTP3__CTN2__CTP2__CTN1__CTP1__CTN0__CTP0
1897 #undef CTCON__CTN3__CTP3__CTN2__CTP2__CTN1__CTP1__CTN0__CTP0
1898 sfr at 0xEB CTCON ; // Capture control, P80C552 specific
1899 // Not directly accessible Bits.
1912 sfr at 0xCC CTH0 ; // Capture high 0, P80C552 specific
1917 sfr at 0xCD CTH1 ; // Capture high 1, P80C552 specific
1922 sfr at 0xCE CTH2 ; // Capture high 2, P80C552 specific
1927 sfr at 0xCF CTH3 ; // Capture high 3, P80C552 specific
1932 sfr at 0xAC CTL0 ; // Capture low 0, P80C552 specific
1937 sfr at 0xAD CTL1 ; // Capture low 1, P80C552 specific
1942 sfr at 0xAE CTL2 ; // Capture low 2, P80C552 specific
1947 sfr at 0xAF CTL3 ; // Capture low 3, P80C552 specific
1952 sfr at 0xDF CTRELH ; // com.timer rel register high byte SAB80517
1957 sfr at 0xDE CTRELL ; // com.timer rel register low byte SAB80517
1960 #ifdef DAPR__SAB80515
1961 #undef DAPR__SAB80515
1962 sfr at 0xD8 DAPR ; // D/A-converter program register SAB80515 specific
1965 #ifdef DAPR__SAB80517
1966 #undef DAPR__SAB80517
1967 sfr at 0xDA DAPR ; // D/A-converter program register SAB80517 specific
1973 sfr at 0x83 DP0H ; // Alternate name for AT89S53
1978 sfr at 0x85 DPH1 ; // DS80C320 specific
1979 sfr at 0x85 DP1H ; // Alternate name for AT89S53
1984 sfr at 0x82 DPL ; // Alternate name for AT89S53
1990 sfr at 0x84 DPL1 ; // DS80C320 specific
1991 sfr at 0x84 DP1L ; // Alternate name for AT89S53
1994 #ifdef DPS__x__x__x__x__x__x__x__SEL
1995 #undef DPS__x__x__x__x__x__x__x__SEL
1997 // Not directly accessible DPS Bit. DS80C320 & DPS8XC520 specific
2001 #ifdef DPS__ID1__ID0__TSL__x__x__x__x__SEL
2002 #undef DPS__ID1__ID0__TSL__x__x__x__x__SEL
2004 // Not directly accessible DPS Bit. DS89C390 specific
2011 #ifdef DPS__ID1__ID0__TSL__AID__x__x__x__SEL
2012 #undef DPS__ID1__ID0__TSL__AID__x__x__x__SEL
2014 // Not directly accessible DPS Bit. DS89C420 specific
2024 sfr at 0x92 DPSEL ; // data pointer select register SAB80517
2029 sfr at 0x93 DPX1 ; // DS80C390 specific
2034 sfr at 0x95 DPX1 ; // DS80C390 specific
2037 #ifdef EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
2038 #undef EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
2040 // Bit registers DS80C320 specific
2048 #ifdef EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2
2049 #undef EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2
2051 // Bit registers DS80C390 specific
2059 sbit at 0xEF CANBIE ;
2062 #ifdef EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2
2063 #undef EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2
2065 // Bit registers DS80C320 specific
2073 #ifdef EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
2074 #undef EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
2076 // Bit registers DS80C320 specific
2084 sbit at 0xFF CANBIP ;
2087 #ifdef EIP0__x__x__x__LPWDI__LPX5__LPX4__LPX3__LPX2
2088 #undef EIP0__x__x__x__LPWDI__LPX5__LPX4__LPX3__LPX2
2090 // Bit registers DS89C420 specific
2095 sbit at 0xFC LPWDI ;
2098 #ifdef EIP1__x__x__x__MPWDI__MPX5__MPX4__MPX3__MPX2
2099 #undef EIP1__x__x__x__MPWDI__MPX5__MPX4__MPX3__MPX2
2101 // Not directly accessible Bits DS89C420 specific
2112 // Not directly accessible Bits DS80C390 specific
2117 #ifdef EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
2118 #undef EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
2120 // Not directly accessible EXIF Bits DS80C320 specific
2130 #ifdef EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
2131 #undef EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
2133 // Not directly accessible EXIF Bits DS87C520 specific
2144 #ifdef EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
2145 #undef EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
2147 // Not directly accessible EXIF Bits DS80C390 & DS89C420 specific
2158 #ifdef FCNTL__FBUSY__FERR__x__x__FC3__FC2__FC1__FC0
2159 #undef FCNTL__FBUSY__FERR__x__x__FC3__FC2__FC1__FC0
2161 // Not directly accessible DS89C420 specific
2175 #ifdef IE__EA__x__x__ES__ET1__EX1__ET0__EX0
2176 #undef IE__EA__x__x__ES__ET1__EX1__ET0__EX0
2187 #ifdef IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
2188 #undef IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
2196 sbit at 0xAD ET2 ; // Enable timer2 interrupt
2200 #ifdef IE__EA__EAD__ES1__ES0__ET1__EX1__ET0__EX0
2201 #undef IE__EA__EAD__ES1__ES0__ET1__EX1__ET0__EX0
2202 sfr at 0xA8 IE ; // same as IEN0 - Interrupt enable 0, P80C552 specific
2203 sfr at 0xA8 IEN0 ; // alternate name
2215 #ifdef IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
2216 #undef IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
2224 sbit at 0xAC ES0 ; // Alternate name
2225 sbit at 0xAD ET2 ; // Enable timer2 interrupt
2230 #ifdef IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
2231 #undef IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
2233 sfr at 0xA8 IEN0 ; // Alternate name
2234 // Bit registers for the SAB80515 and compatible IE
2241 sbit at 0xAD ET2 ; // Enable timer 2 overflow SAB80515 specific
2242 sbit at 0xAE WDT ; // watchdog timer reset - SAB80515 specific
2244 sbit at 0xAF EAL ; // EA as called by Infineon / Siemens
2247 #ifdef IEN1__ET2__ECM2__ECM1__ECM0__ECT3__ECT2__ECT1__ECT0
2248 #undef IEN1__ET2__ECM2__ECM1__ECM0__ECT3__ECT2__ECT1__ECT0
2249 sfr at 0xE8 IEN1 ; // Interrupt enable 1, P80C552 specific
2261 #ifdef IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
2262 #undef IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
2263 sfr at 0xB8 IEN1 ; // interrupt enable register - SAB80515 specific
2265 sbit at 0xB8 EADC ; // A/D converter interrupt enable
2271 sbit at 0xBE SWDT ; // watchdog timer start/reset
2272 sbit at 0xBF EXEN2 ; // timer2 external reload interrupt enable
2275 #ifdef IEN2__SAB80517
2276 #undef IEN2__SAB80517
2277 sfr at 0x9A IEN2 ; // interrupt enable register 2 SAB80517
2280 #ifdef IP__x__x__x__PS__PT1__PX1__PT0__PX0
2281 #undef IP__x__x__x__PS__PT1__PX1__PT0__PX0
2291 #ifdef IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
2292 #undef IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
2300 sbit at 0xBC PS0 ; // alternate name
2304 #ifdef IP__x__PAD__PS1__PS0__PT1__PX1__PT0__PX0
2305 #undef IP__x__PAD__PS1__PS0__PT1__PX1__PT0__PX0
2306 sfr at 0xB8 IP ; // Interrupt priority 0, P80C552 specific
2307 sfr at 0xB8 IP0 ; // alternate name
2318 #ifdef IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
2319 #undef IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
2331 #ifdef IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
2332 #undef IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
2343 #ifdef IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
2344 #undef IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
2345 sfr at 0xA9 IP0 ; // interrupt priority register SAB80515 specific
2346 // Not directly accessible IP0 bits
2356 #ifdef IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
2357 #undef IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
2358 sfr at 0xB8 IP0 ; // interrupt priority register DS89C420 specific
2359 // Not directly accessible IP0 bits
2369 #ifdef IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
2370 #undef IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
2371 sfr at 0xB9 IP1 ; // interrupt priority register SAB80515 specific
2372 // Not directly accessible IP1 bits
2381 #ifdef IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
2382 #undef IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
2383 sfr at 0xB1 IP1 ; // interrupt priority register DS89C420 specific
2384 // Not directly accessible IP0 bits
2394 #ifdef IP1__PT2__PCM2__PCM1__PCM0__PCT3__PCT2__PCT1__PCT0
2395 #undef IP1__PT2__PCM2__PCM1__PCM0__PCT3__PCT2__PCT1__PCT0
2396 sfr at 0xF8 IP1 ; // Interrupt priority 1, P80C552 specific
2410 sfr at 0xC0 IRCON ; // interrupt control register - SAB80515 specific
2412 sbit at 0xC0 IADC ; // A/D converter irq flag
2413 sbit at 0xC1 IEX2 ; // external interrupt edge detect flag
2418 sbit at 0xC6 TF2 ; // timer 2 owerflow flag
2419 sbit at 0xC7 EXF2 ; // timer2 reload flag
2424 sfr at 0xC0 IRCON0 ; // interrupt control register - SAB80515 specific
2426 sbit at 0xC0 IADC ; // A/D converter irq flag
2427 sbit at 0xC1 IEX2 ; // external interrupt edge detect flag
2432 sbit at 0xC6 TF2 ; // timer 2 owerflow flag
2433 sbit at 0xC7 EXF2 ; // timer2 reload flag
2438 sfr at 0xD1 IRCON1 ; // interrupt control register - SAB80515 specific
2443 sfr at 0xD3 MA ; // DS80C390
2448 sfr at 0xD4 MB ; // DS80C390
2453 sfr at 0xD5 MC ; // DS80C390
2458 sfr at 0xD1 MCNT0 ; // DS80C390
2471 sfr at 0xD2 MCNT1 ; // DS80C390
2477 #ifdef MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0
2478 #undef MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0
2479 sfr at 0xC6 MCON ; // DS80C390
2489 #ifdef MCON__PA3__PA2__PA1__PA0__RA32_8__ECE2__PAA__SL
2490 #undef MCON__PA3__PA2__PA1__PA0__RA32_8__ECE2__PAA__SL
2491 sfr at 0xC6 MCON ; // DS5000
2502 #ifdef MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL
2503 #undef MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL
2504 sfr at 0xC6 MCON ; // DS5001
2517 sfr at 0xE9 MD0 ; // MUL / DIV register 0 SAB80517
2522 sfr at 0xEA MD1 ; // MUL / DIV register 1 SAB80517
2527 sfr at 0xEB MD2 ; // MUL / DIV register 2 SAB80517
2532 sfr at 0xEC MD3 ; // MUL / DIV register 3 SAB80517
2537 sfr at 0xED MD4 ; // MUL / DIV register 4 SAB80517
2542 sfr at 0xEE MD5 ; // MUL / DIV register 5 SAB80517
2547 sfr at 0xEA MXAX ; // Dallas DS80C390
2578 #ifdef P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
2579 #undef P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
2580 // P1 alternate functions
2591 #ifdef P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
2592 sbit at 0x90 INT3_CC0 ; // P1 alternate functions - SAB80515 specific
2593 sbit at 0x91 INT4_CC1 ;
2594 sbit at 0x92 INT5_CC2 ;
2595 sbit at 0x93 INT6_CC3 ;
2598 sbit at 0x96 CLKOUT ;
2602 #ifdef P1_EXT__CT0I__CT1I__CT2I__CT3I__T2__RT2__SCL__SDA
2603 #undef P1_EXT__CT0I__CT1I__CT2I__CT3I__T2__RT2__SCL__SDA
2605 sbit at 0x90 CT0I ; // Port 1 alternate functions, P80C552 specific
2615 #ifdef P1_EXT__x__x__x__x__x__x__T2EX__T2
2616 #undef P1_EXT__x__x__x__x__x__x__T2EX__T2
2617 // P1 alternate functions
2646 #ifndef MCS51REG_EXTERNAL_RAM
2659 #ifndef MCS51REG_EXTERNAL_RAM
2667 sfr at 0x80 P4 ; // Port 4 - DS80C390
2681 sfr at 0xC0 P4 ; // Port 4, P80C552 specific
2683 sbit at 0xC0 CMSR0 ;
2684 sbit at 0xC1 CMSR1 ;
2685 sbit at 0xC2 CMSR2 ;
2686 sbit at 0xC3 CMSR3 ;
2687 sbit at 0xC4 CMSR4 ;
2688 sbit at 0xC5 CMSR5 ;
2695 sfr at 0xE8 P4 ; // Port 4 - SAB80515 & compatible microcontrollers
2709 sfr at 0x92 P4CNT ; // DS80C390
2710 // Not directly accessible bits
2711 #define P4CNT_0 0x01
2712 #define P4CNT_1 0x02
2713 #define P4CNT_2 0x04
2714 #define P4CNT_3 0x08
2715 #define P4CNT_4 0x10
2716 #define P4CNT_5 0x20
2722 sfr at 0xA1 P5 ; // Port 5 - DS80C390
2727 sfr at 0xA2 P5CNT ; // DS80C390
2728 // Not directly accessible bits
2729 #define P5CNT_0 0x01
2730 #define P5CNT_1 0x02
2731 #define P5CNT_2 0x04
2735 #define SBCAN0BA 0x40
2736 #define SBCAN1BA 0x80
2741 sfr at 0xC4 P5 ; // Port 5, P80C552 specific
2742 // Not directly accessible Bits.
2755 sfr at 0xF8 P5 ; // Port 5 - SAB80515 & compatible microcontrollers
2769 sfr at 0xDB P6 ; // Port 6 - SAB80515 & compatible microcontrollers
2774 sfr at 0xFA P6 ; // Port 6 - SAB80517 specific
2779 sfr at 0xDB P7 ; // Port 7 - SAB80517 specific
2784 sfr at 0xDD P8 ; // Port 6 - SAB80517 specific
2787 #ifdef PCON__SMOD__x__x__x__x__x__x__x
2788 #undef PCON__SMOD__x__x__x__x__x__x__x
2790 // Not directly accessible PCON bits
2794 #ifdef PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
2795 #undef PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
2797 // Not directly accessible PCON bits
2805 #ifdef PCON__SMOD__x__x__WLE__GF1__GF0__PD__IDL
2806 #undef PCON__SMOD__x__x__WLE__GF1__GF0__PD__IDL
2807 sfr at 0x87 PCON ; // PCON, P80C552 specific
2808 // Not directly accessible Bits.
2810 #define IDLE 0x01 ; same as IDL
2818 #ifdef PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
2819 #undef PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
2821 // Not directly accessible PCON bits
2823 #define IDLE 0x01 ; same as IDL
2825 #define PDE 0x02 ; same as PD
2830 #define PCON_IDLE 0x01
2831 #define PCON_PDE 0x02
2832 #define PCON_GF0 0x04
2833 #define PCON_GF1 0x08
2834 #define PCON_IDLS 0x20
2835 #define PCON_PDS 0x40
2836 #define PCON_SMOD 0x80
2839 #ifdef PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
2840 #undef PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
2842 // Not directly accessible PCON bits
2844 #define IDLE 0x01 ; same as IDL
2854 #ifdef PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
2855 #undef PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
2857 // Not directly accessible PCON bits
2859 #define IDLE 0x01 ; same as IDL
2867 #ifdef PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
2868 #undef PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
2870 // Not directly accessible PCON bits
2872 #define IDLE 0x01 ; same as IDL
2880 #define SMOD_0 0x80 ; same as SMOD
2883 #ifdef PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1__DME0
2884 #undef PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1__DME0
2885 sfr at 0xC4 PMR ; // DS87C520, DS83C520
2886 // Not directly accessible bits
2896 #ifdef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEOFF__x__x
2897 #undef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEOFF__x__x
2898 sfr at 0xC4 PMR ; // DS80C390
2899 // Not directly accessible bits
2908 #ifdef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEON__DME1__DME0
2909 #undef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEON__DME1__DME0
2910 sfr at 0xC4 PMR ; // DS89C420
2911 // Not directly accessible bits
2938 sfr at 0xFC PWM0 ; // PWM register 0, P80C552 specific
2943 sfr at 0xFD PWM1 ; // PWM register 1, P80C552 specific
2948 sfr at 0xFE PWMP ; // PWM prescaler, P80C552 specific
2953 sfr at 0xCB RCAP2H ;
2958 sfr at 0xCA RCAP2L ;
2966 #ifdef ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0
2967 #undef ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0
2968 sfr at 0xC2 ROMSIZE ; // DS87C520, DS83C520
2969 // Not directly accessible bits
2975 #ifdef ROMSIZE__x__x__x__x__PRAME__RMS2__RMS1__RMS0
2976 #undef ROMSIZE__x__x__x__x__PRAME__RMS2__RMS1__RMS0
2977 sfr at 0xC2 ROMSIZE ; // DS89C420
2978 // Not directly accessible bits
2985 #ifdef ROMSIZE__HBPF__BPF__TE__MOVCX__PRAME__RMS2__RMS1__RMS0
2986 #undef ROMSIZE__HBPF__BPF__TE__MOVCX__PRAME__RMS2__RMS1__RMS0
2987 sfr at 0xC2 ROMSIZE ; // DS87C520, DS83C520
2988 // Not directly accessible bits
3001 sfr at 0xD8 RPCTL ; // Dallas DS5001 specific
3003 sbit at 0xD9 RPCON ;
3008 sbit at 0xDF RNR_FLAG ;
3011 #ifdef RTE__TP47__TP46__RP45__RP44__RP43__RP42__RP41__RP40
3012 #undef RTE__TP47__TP46__RP45__RP44__RP43__RP42__RP41__RP40
3013 sfr at 0xEF RTE ; // Reset/toggle enable, P80C552 specific
3014 // Not directly accessible Bits.
3027 sfr at 0x99 S0BUF ; // serial channel 0 buffer register SAB80517 specific
3030 #ifdef S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI
3031 #undef S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI
3032 sfr at 0x98 S0CON ; // serial channel 0 control register P80C552 specific
3034 // Already defined in SCON
3035 //sbit at 0x98 RI0 ;
3036 //sbit at 0x99 TI0 ;
3037 //sbit at 0x9A RB8 ;
3038 //sbit at 0x9B TB8 ;
3039 //sbit at 0x9C REN ;
3040 //sbit at 0x9D SM2 ;
3041 //sbit at 0x9E SM1 ;
3042 //sbit at 0x9F SM0 ;
3045 #ifdef S0CON__SM0__SM1__SM20__REN0__TB80__RB80__TI0__RI0
3046 #undef S0CON__SM0__SM1__SM20__REN0__TB80__RB80__TI0__RI0
3047 // serial channel 0 buffer register SAB80517 specific(same as stock SCON)
3061 sfr at 0xAA S0RELL ; // serial channel 0 reload register low byte SAB80517 specific
3066 sfr at 0xBA S0RELH ; // serial channel 0 reload register high byte SAB80517 specific
3069 #ifdef S1ADR__x__x__x__x__x__x__x__GC
3070 #undef S1ADR__x__x__x__x__x__x__x__GC
3071 sfr at 0xDB S1ADR ; // Serial 1 address, P80C552 specific
3072 // Not directly accessible Bits.
3078 sfr at 0x9C S1BUF ; // serial channel 1 buffer register SAB80517 specific
3081 #ifdef S1CON_AT_0X9B
3082 #undef S1CON_AT_0X9B
3083 sfr at 0x9B S1CON ; // serial channel 1 control register SAB80517 specific
3086 #ifdef S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0
3087 #undef S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0
3088 sfr at 0xD8 S1CON ; // Serial 1 control, P80C552 specific
3089 sfr at 0xD8 SICON ; // sometimes called SICON
3101 #ifdef S1DAT_AT_0XDA
3102 #undef S1DAT_AT_0XDA
3103 sfr at 0xDA S1DAT ; // Serial 1 data, P80C552 specific
3104 sfr at 0xDA SIDAT ; // sometimes called SIDAT
3109 sfr at 0x9D S1RELL ; // serial channel 1 reload register low byte SAB80517 specific
3114 sfr at 0xBB S1RELH ; // serial channel 1 reload register high byte SAB80517 specific
3117 #ifdef S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x
3118 #undef S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x
3119 sfr at 0xD9 S1STA ; // Serial 1 status, P80C552 specific
3120 // Not directly accessible Bits.
3130 // DS80C320 specific
3131 sfr at 0xA9 SADDR0 ;
3136 // DS80C320 specific
3137 sfr at 0xAA SADDR1 ;
3142 // DS80C320 & DS80C390 specific
3143 sfr at 0xB9 SADEN0 ;
3148 // DS80C320 & DS80C390 specific
3149 sfr at 0xBA SADEN1 ;
3160 // DS80C320 & DS80C390 specific
3184 sbit at 0x9A RB8_0 ;
3185 sbit at 0x9B TB8_0 ;
3186 sbit at 0x9C REN_0 ;
3187 sbit at 0x9D SM2_0 ;
3188 sbit at 0x9E SM1_0 ;
3189 sbit at 0x9F SM0_0 ;
3191 sbit at 0x9F SM0_FE_0 ;
3196 // DS80C320 - 80C390 specific
3201 sbit at 0xC2 RB8_1 ;
3202 sbit at 0xC3 TB8_1 ;
3203 sbit at 0xC4 REN_1 ;
3204 sbit at 0xC5 SM2_1 ;
3205 sbit at 0xC6 SM1_1 ;
3206 sbit at 0xC7 SM0_1 ;
3208 sbit at 0xC7 SM0_FE_1 ;
3218 sfr at 0xD5 SPCR ; // AT89S53 specific
3219 // Not directly accesible bits
3232 sfr at 0x86 SPDR ; // AT89S53 specific
3233 // Not directly accesible bits
3246 sfr at 0xAA SPSR ; // AT89S53 specific
3247 // Not directly accesible bits
3254 sfr at 0xBA SRELH ; // Baudrate generator reload high
3259 sfr at 0xAA SRELL ; // Baudrate generator reload low
3262 #ifdef STATUS__PIP__HIP__LIP__x__x__x__x__x
3263 #undef STATUS__PIP__HIP__LIP__x__x__x__x__x
3264 // DS80C320 specific
3265 sfr at 0xC5 STATUS ;
3266 // Not directly accessible Bits. DS80C320 specific
3272 #ifdef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
3273 #undef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
3274 sfr at 0xC5 STATUS ; // DS80C390 specific
3275 // Not directly accessible Bits.
3285 #ifdef STATUS__PIS2__PIS1__PIS0__x__SPTA1__SPRA1__SPTA0__SPRA0
3286 #undef STATUS__PIS2__PIS1__PIS0__x__SPTA1__SPRA1__SPTA0__SPRA0
3287 sfr at 0xC5 STATUS ; // DS89C420 specific
3288 // Not directly accessible Bits.
3298 #ifdef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
3299 #undef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
3300 sfr at 0xC5 STATUS ; // DS80C390 specific
3301 // Not directly accessible Bits.
3311 #ifdef STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
3312 #undef STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
3313 sfr at 0xC5 STATUS ; // DS87C520 & DS83520specific
3314 // Not directly accessible Bits.
3325 #ifdef STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF
3326 #undef STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF
3327 sfr at 0xDA STATUS ; // DS5001specific
3328 // Not directly accessible Bits.
3339 #ifdef STE__TG47__TG46__SP45__SP44__SP43__SP42__SP41__SP40
3340 #undef STE__TG47__TG46__SP45__SP44__SP43__SP42__SP41__SP40
3341 sfr at 0xEE STE ; // Set enable, P80C552 specific
3342 // Not directly accessible Bits.
3355 sfr at 0xB1 SYSCON ; // XRAM Controller Access Control
3357 #define SYSCON_XMAP0 0x01
3358 #define SYSCON_XMAP1 0x02
3359 #define SYSCON_RMAP 0x10
3360 #define SYSCON_EALE 0x20
3363 #ifdef T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
3364 #undef T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
3366 // Definitions for the 8052 compatible microcontrollers.
3368 sbit at 0xC8 CP_RL2 ;
3371 sbit at 0xCB EXEN2 ;
3377 sbit at 0xC8 T2CON_0 ;
3378 sbit at 0xC9 T2CON_1 ;
3379 sbit at 0xCA T2CON_2 ;
3380 sbit at 0xCB T2CON_3 ;
3381 sbit at 0xCC T2CON_4 ;
3382 sbit at 0xCD T2CON_5 ;
3383 sbit at 0xCE T2CON_6 ;
3384 sbit at 0xCF T2CON_7 ;
3387 #ifdef T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
3388 #undef T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
3390 // Definitions for the Infineon / Siemens SAB80515, SAB80515A, SAB80517
3401 sbit at 0xC8 T2CON_0 ;
3402 sbit at 0xC9 T2CON_1 ;
3403 sbit at 0xCA T2CON_2 ;
3404 sbit at 0xCB T2CON_3 ;
3405 sbit at 0xCC T2CON_4 ;
3406 sbit at 0xCD T2CON_5 ;
3407 sbit at 0xCE T2CON_6 ;
3408 sbit at 0xCF T2CON_7 ;
3411 #ifdef T2MOD__x__x__x__D13T1__D13T2__x__T2OE__DCEN
3412 #undef T2MOD__x__x__x__D13T1__D13T2__x__T2OE__DCEN
3413 // Definitions for the timer/counter 2 of the Atmel & Dallas microcontrollers
3415 // Not not directly accessible T2MOD bits
3422 #ifdef T2MOD__x__x__x__x__x__x__T2OE__DCEN
3423 #undef T2MOD__x__x__x__x__x__x__T2OE__DCEN
3424 // Definitions for the timer/counter 2 of the Atmel 89x52 microcontroller
3426 // Not not directly accessible T2MOD bits
3436 sfr at 0xFF T3 ; // Timer 3, P80C552 specific
3441 // DS500x, DS80C320 & DS80C390 specific
3492 // Not directly accessible TMOD bits
3496 #define T0_GATE 0x08
3500 #define T1_GATE 0x80
3502 #define T0_MASK 0x0F
3503 #define T1_MASK 0xF0
3506 #ifdef TM2CON__T2IS1__T2IS0__T2ER__T2B0__T2P1__T2P0__T2MS1__T2MS0
3507 #undef TM2CON__T2IS1__T2IS0__T2ER__T2B0__T2P1__T2P0__T2MS1__T2MS0
3508 sfr at 0xEA TM2CON ; // Timer 2 control, P80C552 specific
3509 // Not directly accessible Bits.
3520 #ifdef TM2IR__T20V__CMI2__CMI1__CMI0__CTI3__CTI2__CTI1__CTI0
3521 #undef TM2IR__T20V__CMI2__CMI1__CMI0__CTI3__CTI2__CTI1__CTI0
3522 sfr at 0xC8 TM2IR ; // Timer 2 int flag reg, P80C552 specific
3536 sfr at 0xED TMH2 ; // Timer high 2, P80C552 specific
3541 sfr at 0xEC TML2 ; // Timer low 2, P80C552 specific
3546 sfr at 0x96 WCON ; // AT89S53 specific
3547 // Not directly accesible bits
3558 // DS80C320 - 390, DS89C420, etc. specific
3568 sbit at 0xDF SMOD_1 ;
3573 sfr at 0x86 WDTREL ; // Watchdof Timer reload register
3578 sfr at 0x91 XPAGE ; // Page Address Register for Extended On-Chip Ram - Infineon / Siemens SAB80515A specific
3581 /////////////////////////
3582 /// Interrupt vectors ///
3583 /////////////////////////
3585 // Interrupt numbers: address = (number * 8) + 3
3586 #define IE0_VECTOR 0 // 0x03 external interrupt 0
3587 #define TF0_VECTOR 1 // 0x0b timer 0
3588 #define IE1_VECTOR 2 // 0x13 external interrupt 1
3589 #define TF1_VECTOR 3 // 0x1b timer 1
3590 #define SI0_VECTOR 4 // 0x23 serial port 0
3592 #ifdef MICROCONTROLLER_AT89S53
3593 #define TF2_VECTOR 5 /* 0x2B timer 2 */
3594 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
3597 #ifdef MICROCONTROLLER_AT89X52
3598 #define TF2_VECTOR 5 /* 0x2B timer 2 */
3599 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
3602 #ifdef MICROCONTROLLER_AT89X55
3603 #define TF2_VECTOR 5 /* 0x2B timer 2 */
3604 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
3607 #ifdef MICROCONTROLLER_DS5000
3608 #define PFW_VECTOR 5 /* 0x2B */
3611 #ifdef MICROCONTROLLER_DS5001
3612 #define PFW_VECTOR 5 /* 0x2B */
3615 #ifdef MICROCONTROLLER_DS80C32X
3616 #define TF2_VECTOR 5 /* 0x2B */
3617 #define PFI_VECTOR 6 /* 0x33 */
3618 #define SIO1_VECTOR 7 /* 0x3B */
3619 #define IE2_VECTOR 8 /* 0x43 */
3620 #define IE3_VECTOR 9 /* 0x4B */
3621 #define IE4_VECTOR 10 /* 0x53 */
3622 #define IE5_VECTOR 11 /* 0x5B */
3623 #define WDI_VECTOR 12 /* 0x63 */
3626 #ifdef MICROCONTROLLER_DS8XC520
3627 #define TF2_VECTOR 5 /* 0x2B */
3628 #define PFI_VECTOR 6 /* 0x33 */
3629 #define SIO1_VECTOR 7 /* 0x3B */
3630 #define IE2_VECTOR 8 /* 0x43 */
3631 #define IE3_VECTOR 9 /* 0x4B */
3632 #define IE4_VECTOR 10 /* 0x53 */
3633 #define IE5_VECTOR 11 /* 0x5B */
3634 #define WDI_VECTOR 12 /* 0x63 */
3637 #ifdef MICROCONTROLLER_P80C552
3638 #define SIO1_VECTOR 5 // 0x2B SIO1 (I2C)
3639 #define CT0_VECTOR 6 // 0x33 T2 capture 0
3640 #define CT1_VECTOR 7 // 0x3B T2 capture 1
3641 #define CT2_VECTOR 8 // 0x43 T2 capture 2
3642 #define CT3_VECTOR 9 // 0x4B T2 capture 3
3643 #define ADC_VECTOR 10 // 0x53 ADC completion
3644 #define CM0_VECTOR 11 // 0x5B T2 compare 0
3645 #define CM1_VECTOR 12 // 0x63 T2 compare 1
3646 #define CM2_VECTOR 13 // 0x6B T2 compare 2
3647 #define TF2_VECTOR 14 // 0x73 T2 overflow
3650 #ifdef MICROCONTROLLER_SAB80515
3651 #define TF2_VECTOR 5 // 0x2B timer 2
3652 #define EX2_VECTOR 5 // 0x2B external interrupt 2
3653 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt
3654 #define IEX2_VECTOR 9 // 0x4B external interrupt 2
3655 #define IEX3_VECTOR 10 // 0x53 external interrupt 3
3656 #define IEX4_VECTOR 11 // 0x5B external interrupt 4
3657 #define IEX5_VECTOR 12 // 0x63 external interrupt 5
3658 #define IEX6_VECTOR 13 // 0x6B external interrupt 6
3661 #ifdef MICROCONTROLLER_SAB80515A
3662 #define TF2_VECTOR 5 // 0x2B timer 2
3663 #define EX2_VECTOR 5 // 0x2B external interrupt 2
3664 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt
3665 #define IEX2_VECTOR 9 // 0x4B external interrupt 2
3666 #define IEX3_VECTOR 10 // 0x53 external interrupt 3
3667 #define IEX4_VECTOR 11 // 0x5B external interrupt 4
3668 #define IEX5_VECTOR 12 // 0x63 external interrupt 5
3669 #define IEX6_VECTOR 13 // 0x6B external interrupt 6
3672 #ifdef MICROCONTROLLER_SAB80517
3673 #define TF2_VECTOR 5 // 0x2B timer 2
3674 #define EX2_VECTOR 5 // 0x2B external interrupt 2
3675 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt
3676 #define IEX2_VECTOR 9 // 0x4B external interrupt 2
3677 #define IEX3_VECTOR 10 // 0x53 external interrupt 3
3678 #define IEX4_VECTOR 11 // 0x5B external interrupt 4
3679 #define IEX5_VECTOR 12 // 0x63 external interrupt 5
3680 #define IEX6_VECTOR 13 // 0x6B external interrupt 6
3683 #define SI1_VECTOR 16 // 0x83 serial port 1
3686 #define COMPARE_VECTOR 19 // 0x9B compare
3689 #endif // End of the header -> #ifndef MCS51REG_H