1 /*-------------------------------------------------------------------------
2 Register Declarations for the mcs51 compatible microcontrollers
4 Written By - Bela Torok / bela.torok@kssg.ch (November 2000)
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the
8 Free Software Foundation; either version 2, or (at your option) any
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 In other words, you are welcome to use, share and improve this program.
21 You are forbidden to forbid anyone else to use, share and improve
22 what you give them. Help stamp out software-hoarding!
27 Version 1.0 Nov 2, 2000 - B. Torok / bela.torok@kssg.ch
28 Initial release, supported microcontrollers:
29 8051, 8052, Atmel AT89C1051, AT89C2051, AT89C4051,
30 Infineon / Siemens SAB80515, SAB80535, SAB80515A
32 Version 1.0.1 (Nov 3, 2000)
33 SAB80515A definitions revised by Michael Schmitt / michael.schmitt@t-online.de
35 Version 1.0.2 (Nov 6, 2000)
36 T2CON bug corrected 8052 and SABX microcontrollers have different T2CONs
37 Support for the Atmel AT89C52, AT80LV52, AT89C55, AT80LV55
38 Support for the Dallas DS80C320 and DS80C323
39 B. Torok / bela.torok@kssg.ch
41 Version 1.0.3 (Nov 7, 2000)
42 SAB80517 definitions added by Michael Schmitt / michael.schmitt@t-online.de
43 Dallas AT89S53 definitions added by B. Torok / bela.torok@kssg.ch
44 Dallas DS87C520 and DS83C520 definitions added by B. Torok / bela.torok@kssg.ch
46 Version 1.0.4 (Nov 9, 2000)
47 To simplify the identication of registers, a large number of definitios
48 were renamed. Long register names now (hopefully) clearly define the
49 function of the registers.
50 Dallas DS89C420 definitions added by B. Torok / bela.torok@kssg.ch
52 Version 1.0.5 (Dec 15, 2000)
53 Definitions added: #ifdef MCS51REG_EXTERNAL_ROM
54 #ifdef MCS51REG_EXTERNAL_RAM
55 #ifndef MCS51REG_DISABLE_WARNINGS
58 Version 1.0.6 (March 10, 2001)
59 Support for the Dallas DS5000 & DS2250
60 Support for the Dallas DS5001 & DS2251
61 Support for the Dallas DS80C390
62 microcontrollers - B. Torok / bela.torok@kssg.ch
64 Version 1.0.7 (June 7, 2001)
65 #ifndef MCS51REG_DISABLE_WARNINGS removed
66 #ifdef MCS51REG_DISABLE_WARNINGS added - B. Torok / bela.torok@kssg.ch
67 Support for the Philips P80C552 added - Bernhard Held / Bernhard.Held@otelo-online.de
69 Version 1.0.8 (Feb 28, 2002)
70 Dallas DS89C420 definitions corrected by B. Torok / bela.torok@kssg.ch
71 Revised by lanius@ewetel.net
73 Version 1.0.9 (Sept 9, 2002)
74 Register declarations for the Atmel T89C51RD2 added by Johannes Hoelzl / johannes.hoelzl@gmx.de
76 Version 1.0.10 (Sept 19, 2002)
77 Register declarations for the Philips P89C668 added by Eric Limpens / Eric@limpens.net
79 Version 1.0.11 (Sept 19, 2004)
80 Dallas DS5000 MCON Register declarations corrected by Radek Zadera / a2i@swipnet.se
82 Adding support for additional microcontrollers:
83 -----------------------------------------------
85 1. Don't modify this file!!!
87 2. Insert your code in a separate file e.g.: mcs51reg_update.h and include
88 this after the #define HEADER_MCS51REG statement in this file
90 3. The mcs51reg_update.h file should contain following definitions:
92 a. An entry with the inventory of the register set of the
93 microcontroller in the "Describe microcontrollers" section.
95 b. If necessary add entry(s) for registers not defined in this file
97 c. Define interrupt vectors
99 4. Compile a program for the microcontroller using the Preprocessor only, e.g.:,
100 sdcc -E test.c > t.txt
101 and check definitions for validity in the t.txt file.
103 5. If everithing seems to be OK send me the mcs51reg_update.h file. --> bela.torok@kssg.ch
104 I'm going to resolve conflicts & verify/merge new definitions to this file.
107 Microcontroller support:
109 Use one of the following options:
111 1. use #include <mcs51reg.h> in your program & define MICROCONTROLLER_XXXX in your makefile.
113 2. use following definitions prior the
114 #include <mcs51reg.h> line in your program:
116 #define MICROCONTROLLER_8052 -> 8052 type microcontroller
118 #define MICROCONTROLLER_AT89CX051 -> Atmel AT89C1051, AT89C2051 and AT89C4051 microcontrollers
121 Use only one of the following definitions!!!
123 Supported Microcontrollers:
126 MICROCONTROLLER_8051 8051
127 MICROCONTROLLER_8052 8052
128 MICROCONTROLLER_AT89CX051 Atmel AT89C1051, AT89C2051 and AT89C4051
129 MICROCONTROLLER_AT89S53 Atmel AT89S53 microcontroller
130 MICROCONTROLLER_AT89X52 Atmel AT89C52 and AT80LV52 microcontrollers
131 MICROCONTROLLER_AT89X55 Atmel AT89C55 and AT80LV55 microcontrollers
132 MICROCONTROLLER_DS5000 Dallas DS5000 & DS2250 microcontroller
133 MICROCONTROLLER_DS5001 Dallas DS5001 & DS2251 microcontroller
134 MICROCONTROLLER_DS80C32X Dallas DS80C320 and DS80C323 microcontrollers
135 MICROCONTROLLER_DS80C390 Dallas DS80C390 microcontroller
136 MICROCONTROLLER_DS89C420 Dallas DS89C420 microcontroller
137 MICROCONTROLLER_DS8XC520 Dallas DS87C520 and DS83C520 microcontrollers
138 MICROCONTROLLER_P80C552 Philips P80C552
139 MICROCONTROLLER_P89C668 Philips P89C668
140 MICROCONTROLLER_SAB80515 Infineon / Siemens SAB80515 & SAB80535
141 MICROCONTROLLER_SAB80515A Infineon / Siemens SAB80515A
142 MICROCONTROLLER_SAB80517 Infineon / Siemens SAB80517
143 MICROCONTROLLER_T89C51RD2 Atmel T89C51RD2
145 Additional definitions (use them prior the #include mcs51reg.h statement):
147 Ports P0 & P2 are not available if external ROM used.
148 Use statement "#define MCS51REG_EXTERNAL_ROM" to undefine P0 & P2.
150 Ports P0, P2, P3_6, WR, P3_7 & RD are not available if external RAM is used.
151 Use statement "#define MCS51REG_EXTERNAL_RAM" to undefine P0, P2,
154 #define MCS51REG_ENABLE_WARNINGS -> enable warnings
156 -----------------------------------------------------------------------*/
159 #ifndef HEADER_MCS51REG
160 #define HEADER_MCS51REG
162 ///////////////////////////////////////////////////////
163 /// Insert header here (for developers only) ///
164 /// remove "//" from the begining of the next line ///
165 //#include "mcs51reg_update.h" ///
166 ///////////////////////////////////////////////////////
168 //////////////////////////////////
169 /// Describe microcontrollers ///
170 /// (inventory of registers) ///
171 //////////////////////////////////
173 // definitions for the 8051
174 #ifdef MICROCONTROLLER_8051
175 #ifdef MICROCONTROLLER_DEFINED
176 #define MCS51REG_ERROR
178 #ifndef MICROCONTROLLER_DEFINED
179 #define MICROCONTROLLER_DEFINED
181 #ifdef MCS51REG_ENABLE_WARNINGS
182 #warning Selected HW: 8051
188 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
199 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
201 #define IP__x__x__x__PS__PT1__PX1__PT0__PX0
206 // end of definitions for the 8051
209 // definitions for the 8052 microcontroller
210 #ifdef MICROCONTROLLER_8052
211 #ifdef MICROCONTROLLER_DEFINED
212 #define MCS51REG_ERROR
214 #ifndef MICROCONTROLLER_DEFINED
215 #define MICROCONTROLLER_DEFINED
217 #ifdef MCS51REG_ENABLE_WARNINGS
218 #warning Selected HW: 8052
225 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
236 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
238 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
242 // 8052 specific registers
243 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
249 // end of definitions for the 8052 microcontroller
252 // definitionsons for the Atmel
253 // AT89C1051, AT89C2051 and AT89C4051 microcontrollers
254 #ifdef MICROCONTROLLER_AT89CX051
255 #ifdef MICROCONTROLLER_DEFINED
256 #define MCS51REG_ERROR
258 #ifndef MICROCONTROLLER_DEFINED
259 #define MICROCONTROLLER_DEFINED
261 #ifdef MCS51REG_ENABLE_WARNINGS
262 #warning Selected HW: Atmel AT89Cx051
264 // 8051 register set without P0 & P2
268 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
278 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
280 #define IP__x__x__x__PS__PT1__PX1__PT0__PX0
285 // end of definitionsons for the Atmel
286 // AT89C1051, AT89C2051 and AT89C4051 microcontrollers
289 // definitions for the Atmel AT89S53
290 #ifdef MICROCONTROLLER_AT89S53
291 #ifdef MICROCONTROLLER_DEFINED
292 #define MCS51REG_ERROR
294 #ifndef MICROCONTROLLER_DEFINED
295 #define MICROCONTROLLER_DEFINED
297 #ifdef MCS51REG_ENABLE_WARNINGS
298 #warning Selected HW: AT89S53
305 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
316 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
318 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
322 // 8052 specific registers
323 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
328 // AT89S53 specific register
329 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
330 #define P1_EXT__x__x__x__x__x__x__T2EX__T2
338 // end of definitions for the Atmel AT89S53 microcontroller
341 // definitions for the Atmel AT89C52 and AT89LV52 microcontrollers
342 #ifdef MICROCONTROLLER_AT89X52
343 #ifdef MICROCONTROLLER_DEFINED
344 #define MCS51REG_ERROR
346 #ifndef MICROCONTROLLER_DEFINED
347 #define MICROCONTROLLER_DEFINED
349 #ifdef MCS51REG_ENABLE_WARNINGS
350 #warning Selected HW: AT89C52 or AT89LV52
357 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
368 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
370 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
374 // 8052 specific registers
375 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
380 // AT89X55 specific register
381 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
382 #define P1_EXT__x__x__x__x__x__x__T2EX__T2
384 // end of definitions for the Atmel AT89C52 and AT89LV52 microcontrollers
387 // definitions for the Atmel AT89C55 and AT89LV55 microcontrollers
388 #ifdef MICROCONTROLLER_AT89X55
389 #ifdef MICROCONTROLLER_DEFINED
390 #define MCS51REG_ERROR
392 #ifndef MICROCONTROLLER_DEFINED
393 #define MICROCONTROLLER_DEFINED
395 #ifdef MCS51REG_ENABLE_WARNINGS
396 #warning Selected HW: AT89C55 or AT89LV55
403 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
414 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
416 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
420 // 8052 specific registers
421 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
426 // AT89X55 specific register
427 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
428 #define P1_EXT__x__x__x__x__x__x__T2EX__T2
430 // end of definitions for the Atmel AT89C55 and AT89LV55 microcontrollers
433 // definitions for the Dallas DS5000
434 #ifdef MICROCONTROLLER_DS5000
435 #ifdef MICROCONTROLLER_DEFINED
436 #define MCS51REG_ERROR
438 #ifndef MICROCONTROLLER_DEFINED
439 #define MICROCONTROLLER_DEFINED
441 #ifdef MCS51REG_ENABLE_WARNINGS
442 #warning Selected HW: DS5000
448 #define PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
459 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
461 #define IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
462 #define MCON__PA3__PA2__PA1__PA0__RA32_8__ECE2__PAA__SL
468 // end of definitions for the Dallas DS5000
471 // definitions for the Dallas DS5001
472 #ifdef MICROCONTROLLER_DS5001
473 #ifdef MICROCONTROLLER_DEFINED
474 #define MCS51REG_ERROR
476 #ifndef MICROCONTROLLER_DEFINED
477 #define MICROCONTROLLER_DEFINED
479 #ifdef MCS51REG_ENABLE_WARNINGS
480 #warning Selected HW: DS5001
486 #define PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
497 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
499 #define IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
503 #define MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL
508 #define STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF
512 // end of definitions for the Dallas DS5001
515 // definitions for the Dallas DS80C320 and DS80C323 microcontrollers
516 #ifdef MICROCONTROLLER_DS80C32X
517 #ifdef MICROCONTROLLER_DEFINED
518 #define MCS51REG_ERROR
520 #ifndef MICROCONTROLLER_DEFINED
521 #define MICROCONTROLLER_DEFINED
523 #ifdef MCS51REG_ENABLE_WARNINGS
524 #warning Selected HW: Dallas DS80C320 or DS80C323
531 #define PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
543 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
545 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
549 // 8052 specific registers
550 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
555 // DS80C320 specific register
558 #define DPS__x__x__x__x__x__x__x__SEL
559 #define CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
560 #define EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
567 #define STATUS__PIP__HIP__LIP__x__x__x__x__x
569 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
570 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
572 #define EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
573 #define EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2
575 // end of definitions for the Dallas DS80C320 and DS80C323 microcontrollers
578 // definitions for the Dallas DS80C390
579 #ifdef MICROCONTROLLER_DS80C390
580 #ifdef MICROCONTROLLER_DEFINED
581 #define MCS51REG_ERROR
583 #ifndef MICROCONTROLLER_DEFINED
584 #define MICROCONTROLLER_DEFINED
586 #ifdef MCS51REG_ENABLE_WARNINGS
587 #warning Selected HW: Dallas DS80C390
594 #define PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
606 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
608 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
612 // 8052 specific registers
613 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
618 // DS80C390 specific register
622 #define DPS__ID1__ID0__TSL__x__x__x__x__SEL
623 #define CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
624 #define EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
632 #define ACON__x__x__x__x__x__SA__AM1__AM0
663 #define PMR__CD1__CD0__SWB__CTM__4X_2X__ALEOFF__x__x
664 #define STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
665 #define MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0
667 #define T2MOD__x__x__x__D13T1__D13T2__x__T2OE__DCEN
684 #define EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2
695 #define EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
702 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
704 // end of definitions for the Dallas DS80C390
706 // definitions for the Dallas DS89C420 microcontroller
707 #ifdef MICROCONTROLLER_DS89C420
708 #ifdef MICROCONTROLLER_DEFINED
709 #define MCS51REG_ERROR
711 #ifndef MICROCONTROLLER_DEFINED
712 #define MICROCONTROLLER_DEFINED
714 #ifdef MCS51REG_ENABLE_WARNINGS
715 #warning Selected HW: Dallas DS89C420
722 #define PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
734 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
736 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
740 // 8052 specific registers
741 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
746 // DS8XC420 specific registers
747 #define ACON__PAGEE__PAGES1__PAGES0__x__x__x__x__x
750 #define DPS__ID1__ID0__TSL__AID__x__x__x__SEL
751 #define CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
753 #define IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
754 #define IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
755 #define EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
756 #define PMR__CD1__CD0__SWB__CTM__4X_2X__ALEON__DME1__DME0
763 #define STATUS__PIS2__PIS1__PIS0__x__SPTA1__SPRA1__SPTA0__SPRA0
765 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
766 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
767 #define ROMSIZE__x__x__x__x__PRAME__RMS2__RMS1__RMS0
769 #define EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
770 #define EIP0__x__x__x__LPWDI__LPX5__LPX4__LPX3__LPX2
771 #define EIP1__x__x__x__MPWDI__MPX5__MPX4__MPX3__MPX2
772 #define FCNTL__FBUSY__FERR__x__x__FC3__FC2__FC1__FC0
774 // end of definitions for the Dallas DS89C420 microcontroller
776 // definitions for the Dallas DS87C520 and DS83C520 microcontrollers
777 #ifdef MICROCONTROLLER_DS8XC520
778 #ifdef MICROCONTROLLER_DEFINED
779 #define MCS51REG_ERROR
781 #ifndef MICROCONTROLLER_DEFINED
782 #define MICROCONTROLLER_DEFINED
784 #ifdef MCS51REG_ENABLE_WARNINGS
785 #warning Selected HW: Dallas DS87C520 or DS85C520
792 #define PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
804 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
806 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
810 // 8052 specific registers
811 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
816 // DS8XC520 specific registers
819 #define DPS__x__x__x__x__x__x__x__SEL
820 #define CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
821 #define EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
822 #define PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1__DME0
829 #define STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
831 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
832 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
834 #define ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0
837 #define EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
838 #define EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2
840 // end of definitions for the Dallas DS87C520 and DS83C520 microcontrollers
843 // definitions for the Philips P80C552 microcontroller
844 #ifdef MICROCONTROLLER_P80C552
845 #ifdef MICROCONTROLLER_DEFINED
846 #define MCS51REG_ERROR
848 #ifndef MICROCONTROLLER_DEFINED
849 #define MICROCONTROLLER_DEFINED
851 #ifdef MCS51REG_ENABLE_WARNINGS
852 #warning Selected HW: Philips P80C552
859 #define PCON__SMOD__x__x__WLE__GF1__GF0__PD__IDL
870 #define IE__EA__EAD__ES1__ES0__ET1__EX1__ET0__EX0
872 #define IP__x__PAD__PS1__PS0__PT1__PX1__PT0__PX0
876 // P80C552 specific register-names
877 #define S0BUF // same as SBUF, set in mcs51reg.h
878 #define S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI
879 // P80C552 specific registers
881 #define ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0
882 #define CTCON__CTN3__CTP3__CTN2__CTP2__CTN1__CTP1__CTN0__CTP0
897 #define IEN1__ET2__ECM2__ECM1__ECM0__ECT3__ECT2__ECT1__ECT0
898 #define IP1__PT2__PCM2__PCM1__PCM0__PCT3__PCT2__PCT1__PCT0
902 #define P1_EXT__SDA__SCL__RT2__T2__CT3I__CT2I__CT1I__CT0I
903 #define P4_AT_0XC0__CMT0__CMT1__CMSR5__CMSR4__CMSR3__CMSR2__CMSR1__CMSR0
905 #define RTE__TP47__TP46__RP45__RP44__RP43__RP42__RP41__RP40
906 #define S1ADR__x__x__x__x__x__x__x__GC
907 #define S1DAT_AT_0XDA
908 #define S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x
909 #define S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0
910 #define STE__TG47__TG46__SP45__SP44__SP43__SP42__SP41__SP40
913 #define TM2CON__T2IS1__T2IS0__T2ER__T2B0__T2P1__T2P0__T2MS1__T2MS0
914 #define TM2IR__T20V__CMI2__CMI1__CMI0__CTI3__CTI2__CTI1__CTI0
917 // end of definitions for the Philips P80C552 microcontroller
920 // definitions for the Philips P89C668
921 #ifdef MICROCONTROLLER_P89C668
922 #ifdef MICROCONTROLLER_DEFINED
923 #define MCS51REG_ERROR
925 #ifndef MICROCONTROLLER_DEFINED
926 #define MICROCONTROLLER_DEFINED
928 #ifdef MCS51REG_ENABLE_WARNINGS
929 #warning Selected HW: P89C668
932 #define P0_EXT__AD7__AD6__AD5__AD4__AD3__AD2__AD1__AD0
934 #define P1_EXT__SDA__SCL__CEX2__CEX1__CEX0__ECI__T2EX__T2
936 #define P2_EXT__AD15__AD14__AD13__AD12__AD11__AD10__AD9__AD8
938 #define P3_EXT__x__x__CEX4__CEX3__x__x__x__x
944 #define PCON__SMOD1__SMOD0__x__POF__GF1__GF0__PD__IDL
950 #define S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI
951 #define S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0
958 #define SADEN_AT_0XB9
959 #define S1IST_AT_0XDC
960 #define S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x
961 #define S1DAT_AT_0XDA
962 #define S1ADR__x__x__x__x__x__x__x__GC
964 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
965 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
970 #define IEN0__EA__EC__ES1__ES0__ET1__EX1__ET0__EX0
971 #define IEN1__x__x__x__x__x__x__x__ET2
972 #define IP__PT2__PPC__PS1__PS0__PT1__PX1__PT0__PX0
973 #define IPH__PT2H__PPCH__PS1H__PS0H__PT1H__PX1H__PT0H__PX0H
974 #define CCON__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0
975 #define CMOD__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
976 #define AUXR__x__x__x__x__x__x__EXTRAM__A0
977 #define AUXR1__x__x__ENBOOT__x__GF2__0__x__DPS
978 #define WDTRST_AT_0XA6
979 #define CCAPM0_AT_0XC2
980 #define CCAPM1_AT_0XC3
981 #define CCAPM2_AT_0XC4
982 #define CCAPM3_AT_0XC5
983 #define CCAPM4_AT_0XC6
984 #define CCAP0L_AT_0XEA
985 #define CCAP1L_AT_0XEB
986 #define CCAP2L_AT_0XEC
987 #define CCAP3L_AT_0XED
988 #define CCAP4L_AT_0XEE
991 #define CCAP0H_AT_0XFA
992 #define CCAP1H_AT_0XFB
993 #define CCAP2H_AT_0XFC
994 #define CCAP3H_AT_0XFD
995 #define CCAP4H_AT_0XFE
997 // end of definitions for the Philips P89C668
1000 // definitions for the Infineon / Siemens SAB80515 & SAB80535
1001 #ifdef MICROCONTROLLER_SAB80515
1002 #ifdef MICROCONTROLLER_DEFINED
1003 #define MCS51REG_ERROR
1005 #ifndef MICROCONTROLLER_DEFINED
1006 #define MICROCONTROLLER_DEFINED
1008 #ifdef MCS51REG_ENABLE_WARNINGS
1009 #warning Selected HW: Infineon / Siemens SAB80515 & SAB80535
1011 // 8051 register set without IP
1016 #define PCON__SMOD__x__x__x__x__x__x__x
1027 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
1032 // SAB80515 specific registers
1033 #define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
1034 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
1035 #define IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
1044 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
1051 #define DAPR__SAB80515
1056 // end of definitions for the Infineon / Siemens SAB80515
1059 // definitions for the Infineon / Siemens SAB80515A
1060 #ifdef MICROCONTROLLER_SAB80515A
1061 #ifdef MICROCONTROLLER_DEFINED
1062 #define MCS51REG_ERROR
1064 #ifndef MICROCONTROLLER_DEFINED
1065 #define MICROCONTROLLER_DEFINED
1067 #ifdef MCS51REG_ENABLE_WARNINGS
1068 #warning Selected HW: Infineon / Siemens SAB80515A
1070 // 8051 register set without IP
1075 #define PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
1086 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
1091 // SAB80515A specific registers
1092 #define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
1093 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
1094 #define IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
1095 #define IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
1104 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
1121 // end of definitions for the Infineon / Siemens SAB80515A
1124 // definitions for the Infineon / Siemens SAB80517
1125 #ifdef MICROCONTROLLER_SAB80517
1126 #ifdef MICROCONTROLLER_DEFINED
1127 #define MCS51REG_ERROR
1129 #ifndef MICROCONTROLLER_DEFINED
1130 #define MICROCONTROLLER_DEFINED
1132 #ifdef MCS51REG_ENABLE_WARNINGS
1133 #warning Selected HW: Infineon / Siemens SAB80517
1135 // 8051 register set without IP, SCON & SBUF
1140 #define PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
1151 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
1156 // SAB80517 specific registers
1157 #define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
1158 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
1159 #define IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
1160 #define IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
1161 #define IEN2__SAB80517
1191 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
1194 #define CTCOM_AT_0XE1
1202 #define DAPR__SAB80517
1217 #define S0CON__SM0__SM1__SM20__REN0__TB80__RB80__TI0__RI0
1221 #define S1CON_AT_0X9B
1228 // end of definitions for the Infineon / Siemens SAB80517
1231 // definitions for the Atmel T89C51RD2
1232 #ifdef MICROCONTROLLER_T89C51RD2
1233 #ifdef MICROCONTROLLER_DEFINED
1234 #define MCS51REG_ERROR
1236 #ifndef MICROCONTROLLER_DEFINED
1237 #define MICROCONTROLLER_DEFINED
1239 #ifdef MCS51REG_ENABLE_WARNINGS
1240 #warning Selected HW: T89C51RD2
1243 // 8051 register set
1248 #define PCON__SMOD1__SMOD0__x__POF__GF1__GF0__PD__IDL
1259 #define IE__EA__EC__ET2__ES__ET1__EX1__ET0__EX0
1262 #define IP__x__PPC__PT2__PS__PT1__PX1__PT0__PX0
1267 // 8052 register set
1268 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
1274 // T89C51RD2 register set
1275 #define P4_AT_0XC0__P4_7__P4_6__P4_5__P4_3__P4_2__P4_1__P4_0
1279 #define AUXR1__x__x__x__x__GF3__x__x__DPS
1280 #define WDTRST_AT_0XA6
1281 #define WDTPRG_AT_0XA7
1282 #define AUXR__x__x__M0__x__XRS1__XRS0__EXTRAM__A0
1283 #define IPH__x__PPCH__PT2H__PSH__PT1H__PX1H__PT0H__PX0H
1287 #define CKCON__X2__T0X2__T1X2__T2X2__SiX2__PcaX2__WdX2__x
1288 #define CCON__0xD8__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0
1289 #define CMOD__0xD9__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
1290 #define CCAPM0_AT_0XDA
1291 #define CCAPM1_AT_0XDB
1292 #define CCAPM2_AT_0XDC
1293 #define CCAPM3_AT_0XDD
1294 #define CCAPM4_AT_0XDE
1296 #define CCAP0L_AT_0XEA
1297 #define CCAP1L_AT_0XEB
1298 #define CCAP2L_AT_0XEC
1299 #define CCAP3L_AT_0XED
1300 #define CCAP4L_AT_0XEE
1302 #define CCAP0H_AT_0XFA
1303 #define CCAP1H_AT_0XFB
1304 #define CCAP2H_AT_0XFC
1305 #define CCAP3H_AT_0XFD
1306 #define CCAP4H_AT_0XFE
1307 #endif /* MICROCONTROLLER_T89C51RD2 */
1308 /* end of definition for the Atmel T89C51RD2 */
1311 /////////////////////////////////////////////////////////
1312 /// don't specify microcontrollers below this line! ///
1313 /////////////////////////////////////////////////////////
1316 // default microcontroller -> 8051
1317 // use default if no microcontroller specified
1318 #ifndef MICROCONTROLLER_DEFINED
1319 #define MICROCONTROLLER_DEFINED
1320 #ifdef MCS51REG_ENABLE_WARNINGS
1321 #warning No microcontroller defined!
1322 #warning Code generated for the 8051
1324 // 8051 register set
1329 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
1340 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
1342 #define IP__x__x__x__PS__PT1__PX1__PT0__PX0
1347 // end of definitions for the default microcontroller
1350 #ifdef MCS51REG_ERROR
1351 #error Two or more microcontrollers defined!
1354 #ifdef MCS51REG_EXTERNAL_ROM
1355 #ifndef MCS51REG_UNDEFINE_P0
1356 #define MCS51REG_UNDEFINE_P0
1358 #ifndef MCS51REG_UNDEFINE_P2
1359 #define MCS51REG_UNDEFINE_P2
1363 #ifdef MCS51REG_EXTERNAL_RAM
1364 #ifndef MCS51REG_UNDEFINE_P0
1365 #define MCS51REG_UNDEFINE_P0
1367 #ifndef MCS51REG_UNDEFINE_P2
1368 #define MCS51REG_UNDEFINE_P2
1372 #ifdef MCS51REG_UNDEFINE_P0
1376 #ifdef MCS51REG_UNDEFINE_P2
1380 ////////////////////////////////
1381 /// Register definitions ///
1382 /// (In alphabetical order) ///
1383 ////////////////////////////////
1390 #ifdef ACON__PAGEE__PAGES1__PAGES0__x__x__x__x__x
1391 #undef ACON__PAGEE__PAGES1__PAGES0__x__x__x__x__x
1392 sfr at 0x9D ACON ; // DS89C420 specific
1393 // Not directly accessible bits
1399 #ifdef ACON__x__x__x__x__x__SA__AM1__AM0
1400 #undef ACON__x__x__x__x__x__SA__AM1__AM0
1401 sfr at 0x9D ACON ; // DS89C390 specific
1402 // Not directly accessible bits
1410 sfr at 0xC6 ADCH ; // A/D converter high
1415 sfr at 0xD8 ADCON ; // A/D-converter control register SAB80515 specific
1426 // ADCON0 ... Infineon / Siemens also called this register ADCON in the User Manual
1429 sfr at 0xD8 ADCON0 ; // A/D-converter control register 0 SAB80515A &
1430 // Bit registers // SAB80517 specific
1439 // Not directly accessible ADCON0
1440 #define ADCON0_MX0 0x01
1441 #define ADCON0_MX1 0x02
1442 #define ADCON0_MX2 0x04
1443 #define ADCON0_ADM 0x08
1444 #define ADCON0_BSY 0x10
1445 #define ADCON0_ADEX 0x20
1446 #define ADCON0_CLK 0x40
1447 #define ADCON0_BD 0x80
1452 sfr at 0xDC ADCON1 ; // A/D-converter control register 1 SAB80515A & SAB80517 specific
1453 // Not directly accessible ADCON1
1454 #define ADCON1_MX0 0x01
1455 #define ADCON1_MX1 0x02
1456 #define ADCON1_MX2 0x04
1457 #define ADCON1_ADCL 0x80
1460 #ifdef ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0
1461 #undef ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0
1462 sfr at 0xC5 ADCON ; // A/D control, P80C552 specific
1463 // Not directly accessible Bits.
1470 #define ADC_0 0x40 // different name as ADC0 in P5
1471 #define ADC_1 0x80 // different name as ADC1 in P5
1476 sfr at 0xD9 ADDAT ; // A/D-converter data register SAB80515 specific
1481 sfr at 0xD9 ADDATH ; // A/D data high byte SAB80515A specific
1486 sfr at 0xDA ADDATL ; // A/D data low byte SAB80515A specific
1491 sfr at 0xEF ARCON ; // arithmetic control register SAB80517
1496 sfr at 0x9C AP ; // DS80C390
1499 #ifdef AUXR__x__x__x__x__x__x__EXTRAM__A0
1500 #undef AUXR__x__x__x__x__x__x__EXTRAM__A0
1501 // P89C668 specific, Auxilary
1503 // not bit addressable:
1508 #ifdef AUXR__x__x__M0__x__XRS1__XRS0__EXTRAM__A0
1509 #undef AUXR__x__x__M0__x__XRS1__XRS0__EXTRAM__A0
1521 sbit at 0xF0 BREG_F0 ;
1522 sbit at 0xF1 BREG_F1 ;
1523 sbit at 0xF2 BREG_F2 ;
1524 sbit at 0xF3 BREG_F3 ;
1525 sbit at 0xF4 BREG_F4 ;
1526 sbit at 0xF5 BREG_F5 ;
1527 sbit at 0xF6 BREG_F6 ;
1528 sbit at 0xF7 BREG_F7 ;
1531 #ifdef AUXR1__x__x__x__x__GF3__x__x__DPS
1532 #undef AUXR1__x__x__x__x__GF3__x__x__DPS
1538 #ifdef AUXR1__x__x__ENBOOT__x__GF2__0__x__DPS
1539 #undef AUXR1__x__x__ENBOOT__x__GF2__0__x__DPS
1540 // P89C668 specific, Auxilary 1
1544 #define ALWAYS_ZERO 0x04
1551 // Not directly accessible bits
1562 sfr at 0xA3 C0C ; // DS80C390 specific
1563 // Not directly accessible bits
1576 sfr at 0xA5 C0IR ; // DS80C390 specific
1577 // Not directly accessible bits
1590 sfr at 0xAB C0M1C ; // DS80C390 specific
1591 // Not directly accessible bits
1593 #define ROW_TIH 0x02
1604 sfr at 0xAC C0M2C ; // DS80C390 specific
1609 sfr at 0xAD C0M3C ; // DS80C390 specific
1614 sfr at 0xAE C0M4C ; // DS80C390 specific
1619 sfr at 0xAF C0M5C ; // DS80C390 specific
1624 sfr at 0xB3 C0M6C ; // DS80C390 specific
1629 sfr at 0xB4 C0M7C ; // DS80C390 specific
1634 sfr at 0xB5 C0M8C ; // DS80C390 specific
1639 sfr at 0xB6 C0M9C ; // DS80C390 specific
1644 sfr at 0xB7 C0M10C ; // DS80C390 specific
1649 sfr at 0xBB C0M11C ; // DS80C390 specific
1654 sfr at 0xBC C0M12C ; // DS80C390 specific
1659 sfr at 0xBD C0M13C ; // DS80C390 specific
1664 sfr at 0xBE C0M14C ; // DS80C390 specific
1669 sfr at 0xBF C0M15C ; // DS80C390 specific
1674 sfr at 0xA7 C0RE ; // DS80C390 specific
1679 sfr at 0x96 C0RMS0 ; // DS80C390 specific
1684 sfr at 0x97 C0RMS1 ; // DS80C390 specific
1689 sfr at 0xA4 C0S ; // DS80C390 specific
1690 // Not directly accessible bits
1697 #define EC96_128 0x40
1703 sfr at 0xA6 C0TE ; // DS80C390 specific
1708 sfr at 0x9E C0TMA0 ; // DS80C390 specific
1713 sfr at 0x9F C0TMA1 ; // DS80C390 specific
1718 sfr at 0xE3 C1C ; // DS80C390 specific
1719 // Not directly accessible bits
1732 sfr at 0xE5 C1IR ; // DS80C390 specific
1733 // Not directly accessible bits
1746 sfr at 0xE7 C1RE ; // DS80C390 specific
1751 sfr at 0xEB C1M1C ; // DS80C390 specific
1756 sfr at 0xEC C1M2C ; // DS80C390 specific
1761 sfr at 0xED C1M3C ; // DS80C390 specific
1766 sfr at 0xEE C1M4C ; // DS80C390 specific
1771 sfr at 0xEF C1M5C ; // DS80C390 specific
1776 sfr at 0xF3 C1M6C ; // DS80C390 specific
1781 sfr at 0xF4 C1M7C ; // DS80C390 specific
1786 sfr at 0xF5 C1M8C ; // DS80C390 specific
1791 sfr at 0xF6 C1M9C ; // DS80C390 specific
1796 sfr at 0xF7 C1M10C ; // DS80C390 specific
1801 sfr at 0xFB C1M11C ; // DS80C390 specific
1806 sfr at 0xFC C1M12C ; // DS80C390 specific
1811 sfr at 0xFD C1M13C ; // DS80C390 specific
1816 sfr at 0xFE C1M14C ; // DS80C390 specific
1821 sfr at 0xFF C1M15C ; // DS80C390 specific
1826 sfr at 0xE4 C1S ; // DS80C390 specific
1827 // Not directly accessible bits
1840 sfr at 0xE6 C1TE ; // DS80C390 specific
1845 sfr at 0xD6 C1RSM0 ; // DS80C390 specific
1850 sfr at 0xD7 C1RSM1 ; // DS80C390 specific
1855 sfr at 0xDE C1TMA0 ; // DS80C390 specific
1860 sfr at 0xDF C1TMA1 ; // DS80C390 specific
1865 sfr at 0xC9 CC4EN ; // compare/capture 4 enable register SAB80517 specific
1868 #ifdef CCAP0H_AT_0XFA
1869 #undef CCAP0H_AT_0XFA
1870 sfr at 0xFA CCAP0H ;
1873 #ifdef CCAP1H_AT_0XFB
1874 #undef CCAP1H_AT_0XFB
1875 sfr at 0xFB CCAP1H ;
1878 #ifdef CCAP2H_AT_0XFC
1879 #undef CCAP2H_AT_0XFC
1880 sfr at 0xFC CCAP2H ;
1883 #ifdef CCAP3H_AT_0XFD
1884 #undef CCAP3H_AT_0XFD
1885 sfr at 0xFD CCAP3H ;
1888 #ifdef CCAP4H_AT_0XFE
1889 #undef CCAP4H_AT_0XFE
1890 sfr at 0xFE CCAP4H ;
1893 #ifdef CCAP0L_AT_0XEA
1894 #undef CCAP0L_AT_0XEA
1895 sfr at 0xEA CCAP0L ;
1898 #ifdef CCAP1L_AT_0XEB
1899 #undef CCAP1L_AT_0XEB
1900 sfr at 0xEB CCAP1L ;
1903 #ifdef CCAP2L_AT_0XEC
1904 #undef CCAP2L_AT_0XEC
1905 sfr at 0xEC CCAP2L ;
1908 #ifdef CCAP3L_AT_0XED
1909 #undef CCAP3L_AT_0XED
1910 sfr at 0xED CCAP3L ;
1913 #ifdef CCAP4L_AT_0XEE
1914 #undef CCAP4L_AT_0XEE
1915 sfr at 0xEE CCAP4L ;
1918 #ifdef CCAPM0_AT_0XC2
1919 #undef CCAPM0_AT_0XC2
1920 // P89C668 specific, Capture module:
1921 sfr at 0xC2 CCAPM0 ;
1924 #ifdef CCAPM0_AT_0XDA
1925 #undef CCAPM0_AT_0XDA
1926 sfr at 0xDA CCAPM0 ;
1936 #ifdef CCAPM1_AT_0XC3
1937 #undef CCAPM1_AT_0XC3
1938 sfr at 0xC3 CCAPM1 ;
1941 #ifdef CCAPM1_AT_0XDB
1942 #undef CCAPM1_AT_0XDB
1943 sfr at 0xDB CCAPM1 ;
1946 #ifdef CCAPM2_AT_0XC4
1947 #undef CCAPM2_AT_0XC4
1948 sfr at 0xC4 CCAPM2 ;
1951 #ifdef CCAPM2_AT_0XDC
1952 #undef CCAPM2_AT_0XDC
1953 sfr at 0x0DC CCAPM2 ;
1956 #ifdef CCAPM3_AT_0XC5
1957 #undef CCAPM3_AT_0XC5
1958 sfr at 0xC5 CCAPM3 ;
1961 #ifdef CCAPM3_AT_0XDD
1962 #undef CCAPM3_AT_0XDD
1963 sfr at 0x0DD CCAPM3 ;
1966 #ifdef CCAPM4_AT_0XDE
1967 #undef CCAPM4_AT_0XDE
1968 sfr at 0x0DE CCAPM4 ;
1971 #ifdef CCAPM4_AT_0XC6
1972 #undef CCAPM4_AT_0XC6
1973 sfr at 0xC6 CCAPM4 ;
1978 sfr at 0xC1 CCEN ; // compare/capture enable register SAB80515 specific
1983 sfr at 0xC3 CCH1 ; // compare/capture register 1, high byte SAB80515 specific
1988 sfr at 0xC5 CCH2 ; // compare/capture register 2, high byte SAB80515 specific
1993 sfr at 0xC7 CCH3 ; // compare/capture register 3, high byte SAB80515 specific
1998 sfr at 0xCF CCH4 ; // compare/capture register 4, high byte SAB80515 specific
2003 sfr at 0xC2 CCL1 ; // compare/capture register 1, low byte SAB80515 specific
2008 sfr at 0xC4 CCL2 ; // compare/capture register 2, low byte SAB80515 specific
2013 sfr at 0xC6 CCL3 ; // compare/capture register 3, low byte SAB80515 specific
2018 sfr at 0xCE CCL4 ; // compare/capture register 4, low byte SAB80515 specific
2021 #ifdef CCON__0xD8__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0
2022 #undef CCON__0xD8__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0
2023 sfr at 0xD8 CCON ; // T89C51RD2 specific register
2034 #ifdef CCON__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0
2035 #undef CCON__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0
2036 // P89C668 specific, PCA Counter control:
2054 #ifdef CMOD__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
2055 #undef CMOD__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
2056 // P89C668 specific, PCA Counter mode:
2058 // not bit addressable:
2066 #ifdef CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
2067 #undef CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
2068 sfr at 0x8E CKCON ; // DS80C320 & DS80C390 specific
2069 // Not directly accessible Bits.
2080 #ifdef CKCON__X2__T0X2__T1X2__T2X2__SiX2__PcaX2__WdX2__x
2081 #undef CKCON__X2__T0X2__T1X2__T2X2__SiX2__PcaX2__WdX2__x
2094 sfr at 0x96 CKMOD ; // DS89C420 specific
2095 // Not directly accessible Bits.
2108 sfr at 0xF6 CMEN ; // compare enable register SAB80517 specific
2113 sfr at 0xD3 CMH0 ; // compare register 0 high byte SAB80517 specific
2118 sfr at 0xD5 CMH1 ; // compare register 1 high byte SAB80517 specific
2123 sfr at 0xD7 CMH2 ; // compare register 2 high byte SAB80517 specific
2128 sfr at 0xE3 CMH3 ; // compare register 3 high byte SAB80517 specific
2133 sfr at 0xE5 CMH4 ; // compare register 4 high byte SAB80517 specific
2138 sfr at 0xE7 CMH5 ; // compare register 5 high byte SAB80517 specific
2143 sfr at 0xF3 CMH6 ; // compare register 6 high byte SAB80517 specific
2148 sfr at 0xF5 CMH7 ; // compare register 7 high byte SAB80517 specific
2153 sfr at 0xC9 CMH0 ; // Compare high 0, P80C552 specific
2158 sfr at 0xCA CMH1 ; // Compare high 1, P80C552 specific
2163 sfr at 0xCB CMH2 ; // Compare high 2, P80C552 specific
2168 sfr at 0xD2 CML0 ; // compare register 0 low byte SAB80517 specific
2173 sfr at 0xD4 CML1 ; // compare register 1 low byte SAB80517 specific
2178 sfr at 0xD6 CML2 ; // compare register 2 low byte SAB80517 specific
2183 sfr at 0xE2 CML3 ; // compare register 3 low byte SAB80517 specific
2188 sfr at 0xE4 CML4 ; // compare register 4 low byte SAB80517 specific
2193 sfr at 0xE6 CML5 ; // compare register 5 low byte SAB80517 specific
2198 sfr at 0xF2 CML6 ; // compare register 6 low byte SAB80517 specific
2203 sfr at 0xF4 CML7 ; // compare register 7 low byte SAB80517 specific
2208 sfr at 0xA9 CML0 ; // Compare low 0, P80C552 specific
2213 sfr at 0xAA CML1 ; // Compare low 1, P80C552 specific
2218 sfr at 0xAB CML2 ; // Compare low 2, P80C552 specific
2221 #ifdef CMOD__0xD9__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
2222 #undef CMOD__0xD9__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
2233 sfr at 0xF7 CMSEL ; // compare input select SAB80517
2238 sfr at 0xCE COR ; // Dallas DS80C390 specific
2251 sfr at 0xC1 CRC ; // Dallas DS5001 specific
2262 sfr at 0xCB CRCH ; // compare/reload/capture register, high byte SAB80515 specific
2267 sfr at 0xC3 CRCHIGH ; // DS5001 specific
2272 sfr at 0xCA CRCL ; // compare/reload/capture register, low byte SAB80515 specific
2277 sfr at 0xC2 CRCLOW ; // DS5001 specific
2280 #ifdef CTCOM_AT_0XE1
2281 #undef CTCOM_AT_0XE1
2282 sfr at 0xE1 CTCON ; // com.timer control register SAB80517
2285 #ifdef CTCON__CTN3__CTP3__CTN2__CTP2__CTN1__CTP1__CTN0__CTP0
2286 #undef CTCON__CTN3__CTP3__CTN2__CTP2__CTN1__CTP1__CTN0__CTP0
2287 sfr at 0xEB CTCON ; // Capture control, P80C552 specific
2288 // Not directly accessible Bits.
2301 sfr at 0xCC CTH0 ; // Capture high 0, P80C552 specific
2306 sfr at 0xCD CTH1 ; // Capture high 1, P80C552 specific
2311 sfr at 0xCE CTH2 ; // Capture high 2, P80C552 specific
2316 sfr at 0xCF CTH3 ; // Capture high 3, P80C552 specific
2321 sfr at 0xAC CTL0 ; // Capture low 0, P80C552 specific
2326 sfr at 0xAD CTL1 ; // Capture low 1, P80C552 specific
2331 sfr at 0xAE CTL2 ; // Capture low 2, P80C552 specific
2336 sfr at 0xAF CTL3 ; // Capture low 3, P80C552 specific
2341 sfr at 0xDF CTRELH ; // com.timer rel register high byte SAB80517
2346 sfr at 0xDE CTRELL ; // com.timer rel register low byte SAB80517
2349 #ifdef DAPR__SAB80515
2350 #undef DAPR__SAB80515
2351 sfr at 0xDA DAPR ; // D/A-converter program register SAB80515 specific
2354 #ifdef DAPR__SAB80517
2355 #undef DAPR__SAB80517
2356 sfr at 0xDA DAPR ; // D/A-converter program register SAB80517 specific
2362 sfr at 0x83 DP0H ; // Alternate name for AT89S53
2367 sfr at 0x85 DPH1 ; // DS80C320 specific
2368 sfr at 0x85 DP1H ; // Alternate name for AT89S53
2373 sfr at 0x82 DPL ; // Alternate name for AT89S53
2379 sfr at 0x84 DPL1 ; // DS80C320 specific
2380 sfr at 0x84 DP1L ; // Alternate name for AT89S53
2383 #ifdef DPS__x__x__x__x__x__x__x__SEL
2384 #undef DPS__x__x__x__x__x__x__x__SEL
2386 // Not directly accessible DPS Bit. DS80C320 & DPS8XC520 specific
2390 #ifdef DPS__ID1__ID0__TSL__x__x__x__x__SEL
2391 #undef DPS__ID1__ID0__TSL__x__x__x__x__SEL
2393 // Not directly accessible DPS Bit. DS89C390 specific
2400 #ifdef DPS__ID1__ID0__TSL__AID__x__x__x__SEL
2401 #undef DPS__ID1__ID0__TSL__AID__x__x__x__SEL
2403 // Not directly accessible DPS Bit. DS89C420 specific
2413 sfr at 0x92 DPSEL ; // data pointer select register SAB80517
2418 sfr at 0x93 DPX1 ; // DS80C390 specific
2423 sfr at 0x95 DPX1 ; // DS80C390 specific
2443 #ifdef EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
2444 #undef EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
2446 // Bit registers DS80C320 specific
2454 #ifdef EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2
2455 #undef EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2
2457 // Bit registers DS80C390 specific
2465 sbit at 0xEF CANBIE ;
2468 #ifdef EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2
2469 #undef EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2
2471 // Bit registers DS80C320 specific
2479 #ifdef EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
2480 #undef EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
2482 // Bit registers DS80C320 specific
2490 sbit at 0xFF CANBIP ;
2493 #ifdef EIP0__x__x__x__LPWDI__LPX5__LPX4__LPX3__LPX2
2494 #undef EIP0__x__x__x__LPWDI__LPX5__LPX4__LPX3__LPX2
2496 // Bit registers DS89C420 specific
2501 sbit at 0xFC LPWDI ;
2504 #ifdef EIP1__x__x__x__MPWDI__MPX5__MPX4__MPX3__MPX2
2505 #undef EIP1__x__x__x__MPWDI__MPX5__MPX4__MPX3__MPX2
2507 // Not directly accessible Bits DS89C420 specific
2518 // Not directly accessible Bits DS80C390 specific
2523 #ifdef EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
2524 #undef EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
2526 // Not directly accessible EXIF Bits DS80C320 specific
2536 #ifdef EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
2537 #undef EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
2539 // Not directly accessible EXIF Bits DS87C520 specific
2550 #ifdef EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
2551 #undef EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
2553 // Not directly accessible EXIF Bits DS80C390 & DS89C420 specific
2564 #ifdef FCNTL__FBUSY__FERR__x__x__FC3__FC2__FC1__FC0
2565 #undef FCNTL__FBUSY__FERR__x__x__FC3__FC2__FC1__FC0
2567 // Not directly accessible DS89C420 specific
2595 #ifdef IE__EA__x__x__ES__ET1__EX1__ET0__EX0
2596 #undef IE__EA__x__x__ES__ET1__EX1__ET0__EX0
2607 #ifdef IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
2608 #undef IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
2616 sbit at 0xAD ET2 ; // Enable timer2 interrupt
2620 #ifdef IE__EA__EAD__ES1__ES0__ET1__EX1__ET0__EX0
2621 #undef IE__EA__EAD__ES1__ES0__ET1__EX1__ET0__EX0
2622 sfr at 0xA8 IE ; // same as IEN0 - Interrupt enable 0, P80C552 specific
2623 sfr at 0xA8 IEN0 ; // alternate name
2635 #ifdef IE__EA__EC__ET2__ES__ET1__EX1__ET0__EX0
2636 #undef IE__EA__EC__ET2__ES__ET1__EX1__ET0__EX0
2648 #ifdef IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
2649 #undef IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
2657 sbit at 0xAC ES0 ; // Alternate name
2658 sbit at 0xAD ET2 ; // Enable timer2 interrupt
2663 #ifdef IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
2664 #undef IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
2666 sfr at 0xA8 IEN0 ; // Alternate name
2667 // Bit registers for the SAB80515 and compatible IE
2674 sbit at 0xAD ET2 ; // Enable timer 2 overflow SAB80515 specific
2675 sbit at 0xAE WDT ; // watchdog timer reset - SAB80515 specific
2677 sbit at 0xAF EAL ; // EA as called by Infineon / Siemens
2680 #ifdef IEN0__EA__EC__ES1__ES0__ET1__EX1__ET0__EX0
2681 #undef IEN0__EA__EC__ES1__ES0__ET1__EX1__ET0__EX0
2695 #ifdef IEN1__x__x__x__x__x__x__x__ET2
2696 #undef IEN1__x__x__x__x__x__x__x__ET2
2697 // P89C668 specific bit registers
2703 #ifdef IEN1__ET2__ECM2__ECM1__ECM0__ECT3__ECT2__ECT1__ECT0
2704 #undef IEN1__ET2__ECM2__ECM1__ECM0__ECT3__ECT2__ECT1__ECT0
2705 sfr at 0xE8 IEN1 ; // Interrupt enable 1, P80C552 specific
2717 #ifdef IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
2718 #undef IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
2719 sfr at 0xB8 IEN1 ; // interrupt enable register - SAB80515 specific
2721 sbit at 0xB8 EADC ; // A/D converter interrupt enable
2727 sbit at 0xBE SWDT ; // watchdog timer start/reset
2728 sbit at 0xBF EXEN2 ; // timer2 external reload interrupt enable
2731 #ifdef IEN2__SAB80517
2732 #undef IEN2__SAB80517
2733 sfr at 0x9A IEN2 ; // interrupt enable register 2 SAB80517
2736 #ifdef IP__x__x__x__PS__PT1__PX1__PT0__PX0
2737 #undef IP__x__x__x__PS__PT1__PX1__PT0__PX0
2747 #ifdef IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
2748 #undef IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
2756 sbit at 0xBC PS0 ; // alternate name
2760 #ifdef IP__x__PAD__PS1__PS0__PT1__PX1__PT0__PX0
2761 #undef IP__x__PAD__PS1__PS0__PT1__PX1__PT0__PX0
2762 sfr at 0xB8 IP ; // Interrupt priority 0, P80C552 specific
2763 sfr at 0xB8 IP0 ; // alternate name
2774 #ifdef IP__x__PPC__PT2__PS__PT1__PX1__PT0__PX0
2775 #undef IP__x__PPC__PT2__PS__PT1__PX1__PT0__PX0
2787 #ifdef IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
2788 #undef IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
2800 #ifdef IP__PT2__PPC__PS1__PS0__PT1__PX1__PT0__PX0
2801 #undef IP__PT2__PPC__PS1__PS0__PT1__PX1__PT0__PX0
2802 // P89C668 specific:
2815 #ifdef IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
2816 #undef IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
2827 #ifdef IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
2828 #undef IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
2829 sfr at 0xA9 IP0 ; // interrupt priority register SAB80515 specific
2830 // Not directly accessible IP0 bits
2840 #ifdef IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
2841 #undef IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
2842 sfr at 0xB8 IP0 ; // interrupt priority register DS89C420 specific
2843 // Not directly accessible IP0 bits
2853 #ifdef IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
2854 #undef IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
2855 sfr at 0xB9 IP1 ; // interrupt priority register SAB80515 specific
2856 // Not directly accessible IP1 bits
2865 #ifdef IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
2866 #undef IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
2867 sfr at 0xB1 IP1 ; // interrupt priority register DS89C420 specific
2868 // Not directly accessible IP0 bits
2878 #ifdef IP1__PT2__PCM2__PCM1__PCM0__PCT3__PCT2__PCT1__PCT0
2879 #undef IP1__PT2__PCM2__PCM1__PCM0__PCT3__PCT2__PCT1__PCT0
2880 sfr at 0xF8 IP1 ; // Interrupt priority 1, P80C552 specific
2892 #ifdef IPH__x__PPCH__PT2H__PSH__PT1H__PX1H__PT0H__PX0H
2893 #undef IPH__x__PPCH__PT2H__PSH__PT1H__PX1H__PT0H__PX0H
2904 #ifdef IPH__PT2H__PPCH__PS1H__PS0H__PT1H__PX1H__PT0H__PX0H
2905 #undef IPH__PT2H__PPCH__PS1H__PS0H__PT1H__PX1H__PT0H__PX0H
2906 // P89C668 specific:
2908 // not bit addressable:
2921 sfr at 0xC0 IRCON ; // interrupt control register - SAB80515 specific
2923 sbit at 0xC0 IADC ; // A/D converter irq flag
2924 sbit at 0xC1 IEX2 ; // external interrupt edge detect flag
2929 sbit at 0xC6 TF2 ; // timer 2 owerflow flag
2930 sbit at 0xC7 EXF2 ; // timer2 reload flag
2935 sfr at 0xC0 IRCON0 ; // interrupt control register - SAB80515 specific
2937 sbit at 0xC0 IADC ; // A/D converter irq flag
2938 sbit at 0xC1 IEX2 ; // external interrupt edge detect flag
2943 sbit at 0xC6 TF2 ; // timer 2 owerflow flag
2944 sbit at 0xC7 EXF2 ; // timer2 reload flag
2949 sfr at 0xD1 IRCON1 ; // interrupt control register - SAB80515 specific
2954 sfr at 0xD3 MA ; // DS80C390
2959 sfr at 0xD4 MB ; // DS80C390
2964 sfr at 0xD5 MC ; // DS80C390
2969 sfr at 0xD1 MCNT0 ; // DS80C390
2982 sfr at 0xD2 MCNT1 ; // DS80C390
2988 #ifdef MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0
2989 #undef MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0
2990 sfr at 0xC6 MCON ; // DS80C390
3000 #ifdef MCON__PA3__PA2__PA1__PA0__RA32_8__ECE2__PAA__SL
3001 #undef MCON__PA3__PA2__PA1__PA0__RA32_8__ECE2__PAA__SL
3002 sfr at 0xC6 MCON ; // DS5000
3013 #ifdef MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL
3014 #undef MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL
3015 sfr at 0xC6 MCON ; // DS5001
3028 sfr at 0xE9 MD0 ; // MUL / DIV register 0 SAB80517
3033 sfr at 0xEA MD1 ; // MUL / DIV register 1 SAB80517
3038 sfr at 0xEB MD2 ; // MUL / DIV register 2 SAB80517
3043 sfr at 0xEC MD3 ; // MUL / DIV register 3 SAB80517
3048 sfr at 0xED MD4 ; // MUL / DIV register 4 SAB80517
3053 sfr at 0xEE MD5 ; // MUL / DIV register 5 SAB80517
3058 sfr at 0xEA MXAX ; // Dallas DS80C390
3075 #ifdef P0_EXT__AD7__AD6__AD5__AD4__AD3__AD2__AD1__AD0
3076 #undef P0_EXT__AD7__AD6__AD5__AD4__AD3__AD2__AD1__AD0
3077 // P89C668 alternate names for bits in P0
3102 #ifdef P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
3103 #undef P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
3104 // P1 alternate functions
3115 #ifdef P1_EXT__SDA__SCL__CEX2__CEX1__CEX0__ECI__T2EX__T2
3116 #undef P1_EXT__SDA__SCL__CEX2__CEX1__CEX0__ECI__T2EX__T2
3117 // P89C669 alternate names for bits at P1
3118 // P1_EXT__SDA__SCL__CEX2__CEX1__CEX0__ECI__T2EX__T2
3129 #ifdef P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
3130 sbit at 0x90 INT3_CC0 ; // P1 alternate functions - SAB80515 specific
3131 sbit at 0x91 INT4_CC1 ;
3132 sbit at 0x92 INT5_CC2 ;
3133 sbit at 0x93 INT6_CC3 ;
3136 sbit at 0x96 CLKOUT ;
3140 #ifdef P1_EXT__CT0I__CT1I__CT2I__CT3I__T2__RT2__SCL__SDA
3141 #undef P1_EXT__CT0I__CT1I__CT2I__CT3I__T2__RT2__SCL__SDA
3143 sbit at 0x90 CT0I ; // Port 1 alternate functions, P80C552 specific
3153 #ifdef P1_EXT__x__x__x__x__x__x__T2EX__T2
3154 #undef P1_EXT__x__x__x__x__x__x__T2EX__T2
3155 // P1 alternate functions
3174 #ifdef P2_EXT__AD15__AD14__AD13__AD12__AD11__AD10__AD9__AD8
3175 #undef P2_EXT__AD15__AD14__AD13__AD12__AD11__AD10__AD9__AD8
3176 // P89C668 specific bit registers at P2:
3197 #ifndef MCS51REG_EXTERNAL_RAM
3210 #ifndef MCS51REG_EXTERNAL_RAM
3216 #ifdef P3_EXT__x__x__CEX4__CEX3__x__x__x__x
3217 #undef P3_EXT__x__x__CEX4__CEX3__x__x__x__x
3218 // P89C668 specific bit registers at P3 (alternate names)
3225 sfr at 0x80 P4 ; // Port 4 - DS80C390
3237 #ifdef P4_AT_0XC0__CMT0__CMT1__CMSR5__CMSR4__CMSR3__CMSR2__CMSR1__CMSR0
3238 #undef P4_AT_0XC0__CMT0__CMT1__CMSR5__CMSR4__CMSR3__CMSR2__CMSR1__CMSR0
3239 sfr at 0xC0 P4 ; // Port 4, P80C552 specific
3241 sbit at 0xC0 CMSR0 ;
3242 sbit at 0xC1 CMSR1 ;
3243 sbit at 0xC2 CMSR2 ;
3244 sbit at 0xC3 CMSR3 ;
3245 sbit at 0xC4 CMSR4 ;
3246 sbit at 0xC5 CMSR5 ;
3251 #ifdef P4_AT_0XC0__P4_7__P4_6__P4_5__P4_3__P4_2__P4_1__P4_0
3252 #undef P4_AT_0XC0__P4_7__P4_6__P4_5__P4_3__P4_2__P4_1__P4_0
3253 sfr at 0xC0 P4 ; // Port 4, T89C51 specific
3267 sfr at 0xE8 P4 ; // Port 4 - SAB80515 & compatible microcontrollers
3281 sfr at 0x92 P4CNT ; // DS80C390
3282 // Not directly accessible bits
3283 #define P4CNT_0 0x01
3284 #define P4CNT_1 0x02
3285 #define P4CNT_2 0x04
3286 #define P4CNT_3 0x08
3287 #define P4CNT_4 0x10
3288 #define P4CNT_5 0x20
3294 sfr at 0xA1 P5 ; // Port 5 - DS80C390
3299 sfr at 0xE8 P5 ; // Port 5 - T89C51RD2
3313 sfr at 0xA2 P5CNT ; // DS80C390
3314 // Not directly accessible bits
3315 #define P5CNT_0 0x01
3316 #define P5CNT_1 0x02
3317 #define P5CNT_2 0x04
3321 #define SBCAN0BA 0x40
3322 #define SBCAN1BA 0x80
3327 sfr at 0xC4 P5 ; // Port 5, P80C552 specific
3328 // Not directly accessible Bits.
3341 sfr at 0xF8 P5 ; // Port 5 - SAB80515 & compatible microcontrollers
3355 sfr at 0xDB P6 ; // Port 6 - SAB80515 & compatible microcontrollers
3360 sfr at 0xFA P6 ; // Port 6 - SAB80517 specific
3365 sfr at 0xDB P7 ; // Port 7 - SAB80517 specific
3370 sfr at 0xDD P8 ; // Port 6 - SAB80517 specific
3373 #ifdef PCON__SMOD__x__x__x__x__x__x__x
3374 #undef PCON__SMOD__x__x__x__x__x__x__x
3376 // Not directly accessible PCON bits
3380 #ifdef PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
3381 #undef PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
3383 // Not directly accessible PCON bits
3391 #ifdef PCON__SMOD__x__x__WLE__GF1__GF0__PD__IDL
3392 #undef PCON__SMOD__x__x__WLE__GF1__GF0__PD__IDL
3393 sfr at 0x87 PCON ; // PCON, P80C552 specific
3394 // Not directly accessible Bits.
3396 #define IDLE 0x01 /* same as IDL */
3404 #ifdef PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
3405 #undef PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
3407 // Not directly accessible PCON bits
3409 #define IDLE 0x01 /* same as IDL */
3411 #define PDE 0x02 /* same as PD */
3416 #define PCON_IDLE 0x01
3417 #define PCON_PDE 0x02
3418 #define PCON_GF0 0x04
3419 #define PCON_GF1 0x08
3420 #define PCON_IDLS 0x20
3421 #define PCON_PDS 0x40
3422 #define PCON_SMOD 0x80
3425 #ifdef PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
3426 #undef PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
3428 // Not directly accessible PCON bits
3430 #define IDLE 0x01 /* same as IDL */
3440 #ifdef PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
3441 #undef PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
3443 // Not directly accessible PCON bits
3445 #define IDLE 0x01 /* same as IDL */
3453 #ifdef PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
3454 #undef PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
3456 // Not directly accessible PCON bits
3458 #define IDLE 0x01 /* same as IDL */
3466 #define SMOD_0 0x80 /* same as SMOD */
3469 #ifdef PCON__SMOD1__SMOD0__x__POF__GF1__GF0__PD__IDL
3470 #undef PCON__SMOD1__SMOD0__x__POF__GF1__GF0__PD__IDL
3481 #ifdef PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1__DME0
3482 #undef PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1__DME0
3483 sfr at 0xC4 PMR ; // DS87C520, DS83C520
3484 // Not directly accessible bits
3494 #ifdef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEOFF__x__x
3495 #undef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEOFF__x__x
3496 sfr at 0xC4 PMR ; // DS80C390
3497 // Not directly accessible bits
3506 #ifdef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEON__DME1__DME0
3507 #undef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEON__DME1__DME0
3508 sfr at 0xC4 PMR ; // DS89C420
3509 // Not directly accessible bits
3536 sfr at 0xFC PWM0 ; // PWM register 0, P80C552 specific
3541 sfr at 0xFD PWM1 ; // PWM register 1, P80C552 specific
3546 sfr at 0xFE PWMP ; // PWM prescaler, P80C552 specific
3551 sfr at 0xCB RCAP2H ;
3556 sfr at 0xCA RCAP2L ;
3564 #ifdef ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0
3565 #undef ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0
3566 sfr at 0xC2 ROMSIZE ; // DS87C520, DS83C520
3567 // Not directly accessible bits
3573 #ifdef ROMSIZE__x__x__x__x__PRAME__RMS2__RMS1__RMS0
3574 #undef ROMSIZE__x__x__x__x__PRAME__RMS2__RMS1__RMS0
3575 sfr at 0xC2 ROMSIZE ; // DS89C420
3576 // Not directly accessible bits
3583 #ifdef ROMSIZE__HBPF__BPF__TE__MOVCX__PRAME__RMS2__RMS1__RMS0
3584 #undef ROMSIZE__HBPF__BPF__TE__MOVCX__PRAME__RMS2__RMS1__RMS0
3585 sfr at 0xC2 ROMSIZE ; // DS87C520, DS83C520
3586 // Not directly accessible bits
3599 sfr at 0xD8 RPCTL ; // Dallas DS5001 specific
3601 sbit at 0xD9 RPCON ;
3606 sbit at 0xDF RNR_FLAG ;
3609 #ifdef RTE__TP47__TP46__RP45__RP44__RP43__RP42__RP41__RP40
3610 #undef RTE__TP47__TP46__RP45__RP44__RP43__RP42__RP41__RP40
3611 sfr at 0xEF RTE ; // Reset/toggle enable, P80C552 specific
3612 // Not directly accessible Bits.
3625 sfr at 0x99 S0BUF ; // serial channel 0 buffer register SAB80517 specific
3628 #ifdef S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI
3629 #undef S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI
3630 sfr at 0x98 S0CON ; // serial channel 0 control register P80C552 specific
3632 // Already defined in SCON
3633 //sbit at 0x98 RI0 ;
3634 //sbit at 0x99 TI0 ;
3635 //sbit at 0x9A RB8 ;
3636 //sbit at 0x9B TB8 ;
3637 //sbit at 0x9C REN ;
3638 //sbit at 0x9D SM2 ;
3639 //sbit at 0x9E SM1 ;
3640 //sbit at 0x9F SM0 ;
3643 #ifdef S0CON__SM0__SM1__SM20__REN0__TB80__RB80__TI0__RI0
3644 #undef S0CON__SM0__SM1__SM20__REN0__TB80__RB80__TI0__RI0
3645 // serial channel 0 buffer register SAB80517 specific(same as stock SCON)
3659 sfr at 0xAA S0RELL ; // serial channel 0 reload register low byte SAB80517 specific
3664 sfr at 0xBA S0RELH ; // serial channel 0 reload register high byte SAB80517 specific
3667 #ifdef S1ADR__x__x__x__x__x__x__x__GC
3668 #undef S1ADR__x__x__x__x__x__x__x__GC
3669 sfr at 0xDB S1ADR ; // Serial 1 address, P80C552 specific
3670 // Not directly accessible Bits.
3676 sfr at 0x9C S1BUF ; // serial channel 1 buffer register SAB80517 specific
3679 #ifdef S1CON_AT_0X9B
3680 #undef S1CON_AT_0X9B
3681 sfr at 0x9B S1CON ; // serial channel 1 control register SAB80517 specific
3684 #ifdef S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0
3685 #undef S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0
3686 sfr at 0xD8 S1CON ; // Serial 1 control, P80C552 specific
3687 sfr at 0xD8 SICON ; // sometimes called SICON
3699 #ifdef S1DAT_AT_0XDA
3700 #undef S1DAT_AT_0XDA
3701 sfr at 0xDA S1DAT ; // Serial 1 data, P80C552 specific
3702 sfr at 0xDA SIDAT ; // sometimes called SIDAT
3705 #ifdef S1IST_AT_0XDC
3706 #undef S1IST_AT_0XDC
3713 sfr at 0x9D S1RELL ; // serial channel 1 reload register low byte SAB80517 specific
3718 sfr at 0xBB S1RELH ; // serial channel 1 reload register high byte SAB80517 specific
3721 #ifdef S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x
3722 #undef S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x
3723 sfr at 0xD9 S1STA ; // Serial 1 status, P80C552 specific
3724 // Not directly accessible Bits.
3739 // DS80C320 specific
3740 sfr at 0xA9 SADDR0 ;
3745 // DS80C320 specific
3746 sfr at 0xAA SADDR1 ;
3749 #ifdef SADEN_AT_0XB9
3750 #undef SADEN_AT_0XB9
3756 // DS80C320 & DS80C390 specific
3757 sfr at 0xB9 SADEN0 ;
3762 // DS80C320 & DS80C390 specific
3763 sfr at 0xBA SADEN1 ;
3774 // DS80C320 & DS80C390 specific
3798 sbit at 0x9A RB8_0 ;
3799 sbit at 0x9B TB8_0 ;
3800 sbit at 0x9C REN_0 ;
3801 sbit at 0x9D SM2_0 ;
3802 sbit at 0x9E SM1_0 ;
3803 sbit at 0x9F SM0_0 ;
3805 sbit at 0x9F SM0_FE_0 ;
3810 // DS80C320 - 80C390 specific
3815 sbit at 0xC2 RB8_1 ;
3816 sbit at 0xC3 TB8_1 ;
3817 sbit at 0xC4 REN_1 ;
3818 sbit at 0xC5 SM2_1 ;
3819 sbit at 0xC6 SM1_1 ;
3820 sbit at 0xC7 SM0_1 ;
3822 sbit at 0xC7 SM0_FE_1 ;
3832 sfr at 0xD5 SPCR ; // AT89S53 specific
3833 // Not directly accesible bits
3846 sfr at 0x86 SPDR ; // AT89S53 specific
3847 // Not directly accesible bits
3860 sfr at 0xAA SPSR ; // AT89S53 specific
3861 // Not directly accesible bits
3868 sfr at 0xBA SRELH ; // Baudrate generator reload high
3873 sfr at 0xAA SRELL ; // Baudrate generator reload low
3876 #ifdef STATUS__PIP__HIP__LIP__x__x__x__x__x
3877 #undef STATUS__PIP__HIP__LIP__x__x__x__x__x
3878 // DS80C320 specific
3879 sfr at 0xC5 STATUS ;
3880 // Not directly accessible Bits. DS80C320 specific
3886 #ifdef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
3887 #undef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
3888 sfr at 0xC5 STATUS ; // DS80C390 specific
3889 // Not directly accessible Bits.
3899 #ifdef STATUS__PIS2__PIS1__PIS0__x__SPTA1__SPRA1__SPTA0__SPRA0
3900 #undef STATUS__PIS2__PIS1__PIS0__x__SPTA1__SPRA1__SPTA0__SPRA0
3901 sfr at 0xC5 STATUS ; // DS89C420 specific
3902 // Not directly accessible Bits.
3912 #ifdef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
3913 #undef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
3914 sfr at 0xC5 STATUS ; // DS80C390 specific
3915 // Not directly accessible Bits.
3925 #ifdef STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
3926 #undef STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
3927 sfr at 0xC5 STATUS ; // DS87C520 & DS83520specific
3928 // Not directly accessible Bits.
3939 #ifdef STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF
3940 #undef STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF
3941 sfr at 0xDA STATUS ; // DS5001specific
3942 // Not directly accessible Bits.
3953 #ifdef STE__TG47__TG46__SP45__SP44__SP43__SP42__SP41__SP40
3954 #undef STE__TG47__TG46__SP45__SP44__SP43__SP42__SP41__SP40
3955 sfr at 0xEE STE ; // Set enable, P80C552 specific
3956 // Not directly accessible Bits.
3969 sfr at 0xB1 SYSCON ; // XRAM Controller Access Control
3971 #define SYSCON_XMAP0 0x01
3972 #define SYSCON_XMAP1 0x02
3973 #define SYSCON_RMAP 0x10
3974 #define SYSCON_EALE 0x20
3977 #ifdef T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
3978 #undef T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
3980 // Definitions for the 8052 compatible microcontrollers.
3982 sbit at 0xC8 CP_RL2 ;
3985 sbit at 0xCB EXEN2 ;
3991 sbit at 0xC8 T2CON_0 ;
3992 sbit at 0xC9 T2CON_1 ;
3993 sbit at 0xCA T2CON_2 ;
3994 sbit at 0xCB T2CON_3 ;
3995 sbit at 0xCC T2CON_4 ;
3996 sbit at 0xCD T2CON_5 ;
3997 sbit at 0xCE T2CON_6 ;
3998 sbit at 0xCF T2CON_7 ;
4001 #ifdef T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
4002 #undef T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
4004 // Definitions for the Infineon / Siemens SAB80515, SAB80515A, SAB80517
4015 sbit at 0xC8 T2CON_0 ;
4016 sbit at 0xC9 T2CON_1 ;
4017 sbit at 0xCA T2CON_2 ;
4018 sbit at 0xCB T2CON_3 ;
4019 sbit at 0xCC T2CON_4 ;
4020 sbit at 0xCD T2CON_5 ;
4021 sbit at 0xCE T2CON_6 ;
4022 sbit at 0xCF T2CON_7 ;
4025 #ifdef T2MOD__x__x__x__D13T1__D13T2__x__T2OE__DCEN
4026 #undef T2MOD__x__x__x__D13T1__D13T2__x__T2OE__DCEN
4027 // Definitions for the timer/counter 2 of the Atmel & Dallas microcontrollers
4029 // Not not directly accessible T2MOD bits
4036 #ifdef T2MOD__x__x__x__x__x__x__T2OE__DCEN
4037 #undef T2MOD__x__x__x__x__x__x__T2OE__DCEN
4038 // Definitions for the timer/counter 2 of the Atmel 89x52 microcontroller
4040 // Not not directly accessible T2MOD bits
4050 sfr at 0xFF T3 ; // Timer 3, P80C552 specific
4055 // DS500x, DS80C320 & DS80C390 specific
4106 // Not directly accessible TMOD bits
4110 #define T0_GATE 0x08
4114 #define T1_GATE 0x80
4116 #define T0_MASK 0x0F
4117 #define T1_MASK 0xF0
4120 #ifdef TM2CON__T2IS1__T2IS0__T2ER__T2B0__T2P1__T2P0__T2MS1__T2MS0
4121 #undef TM2CON__T2IS1__T2IS0__T2ER__T2B0__T2P1__T2P0__T2MS1__T2MS0
4122 sfr at 0xEA TM2CON ; // Timer 2 control, P80C552 specific
4123 // Not directly accessible Bits.
4134 #ifdef TM2IR__T20V__CMI2__CMI1__CMI0__CTI3__CTI2__CTI1__CTI0
4135 #undef TM2IR__T20V__CMI2__CMI1__CMI0__CTI3__CTI2__CTI1__CTI0
4136 sfr at 0xC8 TM2IR ; // Timer 2 int flag reg, P80C552 specific
4150 sfr at 0xED TMH2 ; // Timer high 2, P80C552 specific
4155 sfr at 0xEC TML2 ; // Timer low 2, P80C552 specific
4160 sfr at 0x96 WCON ; // AT89S53 specific
4161 // Not directly accesible bits
4172 // DS80C320 - 390, DS89C420, etc. specific
4182 sbit at 0xDF SMOD_1 ;
4185 #ifdef WDTPRG_AT_0XA7
4186 #undef WDTPRG_AT_0XA7
4187 sfr at 0xA7 WDTPRG ;
4188 #define WDTRPRG_S0 0x01
4189 #define WDTRPRG_S1 0x02
4190 #define WDTRPRG_S2 0x04
4195 sfr at 0x86 WDTREL ; // Watchdof Timer reload register
4198 #ifdef WDTRST_AT_0XA6
4199 #undef WDTRST_AT_0XA6
4200 sfr at 0xA6 WDTRST ;
4205 sfr at 0x91 XPAGE ; // Page Address Register for Extended On-Chip Ram - Infineon / Siemens SAB80515A specific
4208 /////////////////////////
4209 /// Interrupt vectors ///
4210 /////////////////////////
4212 // Interrupt numbers: address = (number * 8) + 3
4213 #define IE0_VECTOR 0 // 0x03 external interrupt 0
4214 #define TF0_VECTOR 1 // 0x0b timer 0
4215 #define IE1_VECTOR 2 // 0x13 external interrupt 1
4216 #define TF1_VECTOR 3 // 0x1b timer 1
4217 #define SI0_VECTOR 4 // 0x23 serial port 0
4219 #ifdef MICROCONTROLLER_AT89S53
4220 #define TF2_VECTOR 5 /* 0x2B timer 2 */
4221 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
4224 #ifdef MICROCONTROLLER_AT89X52
4225 #define TF2_VECTOR 5 /* 0x2B timer 2 */
4226 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
4229 #ifdef MICROCONTROLLER_AT89X55
4230 #define TF2_VECTOR 5 /* 0x2B timer 2 */
4231 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
4234 #ifdef MICROCONTROLLER_DS5000
4235 #define PFW_VECTOR 5 /* 0x2B */
4238 #ifdef MICROCONTROLLER_DS5001
4239 #define PFW_VECTOR 5 /* 0x2B */
4242 #ifdef MICROCONTROLLER_DS80C32X
4243 #define TF2_VECTOR 5 /* 0x2B */
4244 #define PFI_VECTOR 6 /* 0x33 */
4245 #define SIO1_VECTOR 7 /* 0x3B */
4246 #define IE2_VECTOR 8 /* 0x43 */
4247 #define IE3_VECTOR 9 /* 0x4B */
4248 #define IE4_VECTOR 10 /* 0x53 */
4249 #define IE5_VECTOR 11 /* 0x5B */
4250 #define WDI_VECTOR 12 /* 0x63 */
4253 #ifdef MICROCONTROLLER_DS8XC520
4254 #define TF2_VECTOR 5 /* 0x2B */
4255 #define PFI_VECTOR 6 /* 0x33 */
4256 #define SIO1_VECTOR 7 /* 0x3B */
4257 #define IE2_VECTOR 8 /* 0x43 */
4258 #define IE3_VECTOR 9 /* 0x4B */
4259 #define IE4_VECTOR 10 /* 0x53 */
4260 #define IE5_VECTOR 11 /* 0x5B */
4261 #define WDI_VECTOR 12 /* 0x63 */
4264 #ifdef MICROCONTROLLER_P80C552
4265 #define SIO1_VECTOR 5 // 0x2B SIO1 (I2C)
4266 #define CT0_VECTOR 6 // 0x33 T2 capture 0
4267 #define CT1_VECTOR 7 // 0x3B T2 capture 1
4268 #define CT2_VECTOR 8 // 0x43 T2 capture 2
4269 #define CT3_VECTOR 9 // 0x4B T2 capture 3
4270 #define ADC_VECTOR 10 // 0x53 ADC completion
4271 #define CM0_VECTOR 11 // 0x5B T2 compare 0
4272 #define CM1_VECTOR 12 // 0x63 T2 compare 1
4273 #define CM2_VECTOR 13 // 0x6B T2 compare 2
4274 #define TF2_VECTOR 14 // 0x73 T2 overflow
4277 #ifdef MICROCONTROLLER_P89C668
4278 #define SIO1_VECTOR 5 // 0x2b SIO1 (i2c)
4279 #define PCA_VECTOR 6 // 0x33 (Programmable Counter Array)
4280 #define TF2_VECTOR 7 // 0x3B (Timer 2)
4283 #ifdef MICROCONTROLLER_SAB80515
4284 #define TF2_VECTOR 5 // 0x2B timer 2
4285 #define EX2_VECTOR 5 // 0x2B external interrupt 2
4286 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt
4287 #define IEX2_VECTOR 9 // 0x4B external interrupt 2
4288 #define IEX3_VECTOR 10 // 0x53 external interrupt 3
4289 #define IEX4_VECTOR 11 // 0x5B external interrupt 4
4290 #define IEX5_VECTOR 12 // 0x63 external interrupt 5
4291 #define IEX6_VECTOR 13 // 0x6B external interrupt 6
4294 #ifdef MICROCONTROLLER_SAB80515A
4295 #define TF2_VECTOR 5 // 0x2B timer 2
4296 #define EX2_VECTOR 5 // 0x2B external interrupt 2
4297 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt
4298 #define IEX2_VECTOR 9 // 0x4B external interrupt 2
4299 #define IEX3_VECTOR 10 // 0x53 external interrupt 3
4300 #define IEX4_VECTOR 11 // 0x5B external interrupt 4
4301 #define IEX5_VECTOR 12 // 0x63 external interrupt 5
4302 #define IEX6_VECTOR 13 // 0x6B external interrupt 6
4305 #ifdef MICROCONTROLLER_SAB80517
4306 #define TF2_VECTOR 5 // 0x2B timer 2
4307 #define EX2_VECTOR 5 // 0x2B external interrupt 2
4308 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt
4309 #define IEX2_VECTOR 9 // 0x4B external interrupt 2
4310 #define IEX3_VECTOR 10 // 0x53 external interrupt 3
4311 #define IEX4_VECTOR 11 // 0x5B external interrupt 4
4312 #define IEX5_VECTOR 12 // 0x63 external interrupt 5
4313 #define IEX6_VECTOR 13 // 0x6B external interrupt 6
4316 #define SI1_VECTOR 16 // 0x83 serial port 1
4319 #define COMPARE_VECTOR 19 // 0x9B compare
4322 #ifdef MICROCONTORLLER_T89C51RD2
4323 #define TF2_VECTOR 5 /* 0x2B timer 2 */
4324 #define PCA_VECTOR 6 /* 0x33 Programmable Counter Array interrupt */
4325 #endif /* MICROCONTORLLER_T89C51RD2 */
4327 #endif // End of the header -> #ifndef MCS51REG_H