1 /*-------------------------------------------------------------------------
2 Register Declarations for the mcs51 compatible microcontrollers
4 Written By - Bela Torok / bela.torok@kssg.ch (November 2000)
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the
8 Free Software Foundation; either version 2, or (at your option) any
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 In other words, you are welcome to use, share and improve this program.
21 You are forbidden to forbid anyone else to use, share and improve
22 what you give them. Help stamp out software-hoarding!
27 Version 1.0 Nov 2, 2000 - B. Torok / bela.torok@kssg.ch
28 Initial release, supported microcontrollers:
29 8051, 8052, Atmel AT89C1051, AT89C2051, AT89C4051,
30 Infineon / Siemens SAB80515, SAB80535, SAB80515A
32 Version 1.0.1 (Nov 3, 2000)
33 SAB80515A definitions revised by Michael Schmitt / michael.schmitt@t-online.de
35 Version 1.0.2 (Nov 6, 2000)
36 T2CON bug corrected 8052 and SABX microcontrollers have different T2CONs
37 Support for the Atmel AT89C52, AT80LV52, AT89C55, AT80LV55
38 Support for the Dallas DS80C320 and DS80C323
39 B. Torok / bela.torok@kssg.ch
41 Version 1.0.3 (Nov 7, 2000)
42 SAB80517 definitions added by Michael Schmitt / michael.schmitt@t-online.de
43 Dallas AT89S53 definitions added by B. Torok / bela.torok@kssg.ch
44 Dallas DS87C520 and DS83C520 definitions added by B. Torok / bela.torok@kssg.ch
46 Version 1.0.4 (Nov 9, 2000)
47 To simplify the identication of registers, a large number of definitios
48 were renamed. Long register names now (hopefully) clearly define the
49 function of the registers.
50 Dallas DS89C420 definitions added by B. Torok / bela.torok@kssg.ch
52 Version 1.0.5 (Dec 15, 2000)
53 Definitions added: #ifdef MCS51REG_EXTERNAL_ROM
54 #ifdef MCS51REG_EXTERNAL_RAM
55 #ifndef MCS51REG_DISABLE_WARNINGS
58 Version 1.0.6 (March 10, 2001)
59 Support for the Dallas DS5000 & DS2250
60 Support for the Dallas DS5001 & DS2251
61 Support for the Dallas DS80C390
62 microcontrollers - B. Torok / bela.torok@kssg.ch
64 Version 1.0.7 (June 7, 2001)
65 #ifndef MCS51REG_DISABLE_WARNINGS removed
66 #ifdef MCS51REG_DISABLE_WARNINGS added - B. Torok / bela.torok@kssg.ch
67 Support for the Philips P80C552 added - Bernhard Held / Bernhard.Held@otelo-online.de
69 Version 1.0.8 (Feb 28, 2002)
70 Dallas DS89C420 definitions corrected by B. Torok / bela.torok@kssg.ch
71 Revised by lanius@ewetel.net
73 Version 1.0.9 (Sept 9, 2002)
74 Register declarations for the Atmel T89C51RD2 added by Johannes Hoelzl / johannes.hoelzl@gmx.de
76 Version 1.0.10 (Sept 19, 2002)
77 Register declarations for the Philips P89C668 added by Eric Limpens / Eric@limpens.net
79 Adding support for additional microcontrollers:
80 -----------------------------------------------
82 1. Don't modify this file!!!
84 2. Insert your code in a separate file e.g.: mcs51reg_update.h and include
85 this after the #define HEADER_MCS51REG statement in this file
87 3. The mcs51reg_update.h file should contain following definitions:
89 a. An entry with the inventory of the register set of the
90 microcontroller in the "Describe microcontrollers" section.
92 b. If necessary add entry(s) for registers not defined in this file
94 c. Define interrupt vectors
96 4. Compile a program for the microcontroller using the Preprocessor only, e.g.:,
97 sdcc -E test.c > t.txt
98 and check definitions for validity in the t.txt file.
100 5. If everithing seems to be OK send me the mcs51reg_update.h file. --> bela.torok@kssg.ch
101 I'm going to resolve conflicts & verify/merge new definitions to this file.
104 Microcontroller support:
106 Use one of the following options:
108 1. use #include <mcs51reg.h> in your program & define MICROCONTROLLER_XXXX in your makefile.
110 2. use following definitions prior the
111 #include <mcs51reg.h> line in your program:
113 #define MICROCONTROLLER_8052 -> 8052 type microcontroller
115 #define MICROCONTROLLER_AT89CX051 -> Atmel AT89C1051, AT89C2051 and AT89C4051 microcontrollers
118 Use only one of the following definitions!!!
120 Supported Microcontrollers:
123 MICROCONTROLLER_8051 8051
124 MICROCONTROLLER_8052 8052
125 MICROCONTROLLER_AT89CX051 Atmel AT89C1051, AT89C2051 and AT89C4051
126 MICROCONTROLLER_AT89S53 Atmel AT89S53 microcontroller
127 MICROCONTROLLER_AT89X52 Atmel AT89C52 and AT80LV52 microcontrollers
128 MICROCONTROLLER_AT89X55 Atmel AT89C55 and AT80LV55 microcontrollers
129 MICROCONTROLLER_DS5000 Dallas DS5000 & DS2250 microcontroller
130 MICROCONTROLLER_DS5001 Dallas DS5001 & DS2251 microcontroller
131 MICROCONTROLLER_DS80C32X Dallas DS80C320 and DS80C323 microcontrollers
132 MICROCONTROLLER_DS80C390 Dallas DS80C390 microcontroller
133 MICROCONTROLLER_DS89C420 Dallas DS89C420 microcontroller
134 MICROCONTROLLER_DS8XC520 Dallas DS87C520 and DS83C520 microcontrollers
135 MICROCONTROLLER_P80C552 Philips P80C552
136 MICROCONTROLLER_P89C668 Philips P89C668
137 MICROCONTROLLER_SAB80515 Infineon / Siemens SAB80515 & SAB80535
138 MICROCONTROLLER_SAB80515A Infineon / Siemens SAB80515A
139 MICROCONTROLLER_SAB80517 Infineon / Siemens SAB80517
140 MICROCONTROLLER_T89C51RD2 Atmel T89C51RD2
142 Additional definitions (use them prior the #include mcs51reg.h statement):
144 Ports P0 & P2 are not available if external ROM used.
145 Use statement "#define MCS51REG_EXTERNAL_ROM" to undefine P0 & P2.
147 Ports P0, P2, P3_6, WR, P3_7 & RD are not available if external RAM is used.
148 Use statement "#define MCS51REG_EXTERNAL_RAM" to undefine P0, P2,
151 #define MCS51REG_ENABLE_WARNINGS -> enable warnings
153 -----------------------------------------------------------------------*/
156 #ifndef HEADER_MCS51REG
157 #define HEADER_MCS51REG
159 ///////////////////////////////////////////////////////
160 /// Insert header here (for developers only) ///
161 /// remove "//" from the begining of the next line ///
162 //#include "mcs51reg_update.h" ///
163 ///////////////////////////////////////////////////////
165 //////////////////////////////////
166 /// Describe microcontrollers ///
167 /// (inventory of registers) ///
168 //////////////////////////////////
170 // definitions for the 8051
171 #ifdef MICROCONTROLLER_8051
172 #ifdef MICROCONTROLLER_DEFINED
173 #define MCS51REG_ERROR
175 #ifndef MICROCONTROLLER_DEFINED
176 #define MICROCONTROLLER_DEFINED
178 #ifdef MCS51REG_ENABLE_WARNINGS
179 #warning Selected HW: 8051
185 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
196 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
198 #define IP__x__x__x__PS__PT1__PX1__PT0__PX0
203 // end of definitions for the 8051
206 // definitions for the 8052 microcontroller
207 #ifdef MICROCONTROLLER_8052
208 #ifdef MICROCONTROLLER_DEFINED
209 #define MCS51REG_ERROR
211 #ifndef MICROCONTROLLER_DEFINED
212 #define MICROCONTROLLER_DEFINED
214 #ifdef MCS51REG_ENABLE_WARNINGS
215 #warning Selected HW: 8052
222 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
233 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
235 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
239 // 8052 specific registers
240 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
246 // end of definitions for the 8052 microcontroller
249 // definitionsons for the Atmel
250 // AT89C1051, AT89C2051 and AT89C4051 microcontrollers
251 #ifdef MICROCONTROLLER_AT89CX051
252 #ifdef MICROCONTROLLER_DEFINED
253 #define MCS51REG_ERROR
255 #ifndef MICROCONTROLLER_DEFINED
256 #define MICROCONTROLLER_DEFINED
258 #ifdef MCS51REG_ENABLE_WARNINGS
259 #warning Selected HW: Atmel AT89Cx051
261 // 8051 register set without P0 & P2
265 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
275 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
277 #define IP__x__x__x__PS__PT1__PX1__PT0__PX0
282 // end of definitionsons for the Atmel
283 // AT89C1051, AT89C2051 and AT89C4051 microcontrollers
286 // definitions for the Atmel AT89S53
287 #ifdef MICROCONTROLLER_AT89S53
288 #ifdef MICROCONTROLLER_DEFINED
289 #define MCS51REG_ERROR
291 #ifndef MICROCONTROLLER_DEFINED
292 #define MICROCONTROLLER_DEFINED
294 #ifdef MCS51REG_ENABLE_WARNINGS
295 #warning Selected HW: AT89S53
302 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
313 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
315 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
319 // 8052 specific registers
320 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
325 // AT89S53 specific register
326 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
327 #define P1_EXT__x__x__x__x__x__x__T2EX__T2
335 // end of definitions for the Atmel AT89S53 microcontroller
338 // definitions for the Atmel AT89C52 and AT89LV52 microcontrollers
339 #ifdef MICROCONTROLLER_AT89X52
340 #ifdef MICROCONTROLLER_DEFINED
341 #define MCS51REG_ERROR
343 #ifndef MICROCONTROLLER_DEFINED
344 #define MICROCONTROLLER_DEFINED
346 #ifdef MCS51REG_ENABLE_WARNINGS
347 #warning Selected HW: AT89C52 or AT89LV52
354 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
365 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
367 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
371 // 8052 specific registers
372 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
377 // AT89X55 specific register
378 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
379 #define P1_EXT__x__x__x__x__x__x__T2EX__T2
381 // end of definitions for the Atmel AT89C52 and AT89LV52 microcontrollers
384 // definitions for the Atmel AT89C55 and AT89LV55 microcontrollers
385 #ifdef MICROCONTROLLER_AT89X55
386 #ifdef MICROCONTROLLER_DEFINED
387 #define MCS51REG_ERROR
389 #ifndef MICROCONTROLLER_DEFINED
390 #define MICROCONTROLLER_DEFINED
392 #ifdef MCS51REG_ENABLE_WARNINGS
393 #warning Selected HW: AT89C55 or AT89LV55
400 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
411 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
413 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
417 // 8052 specific registers
418 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
423 // AT89X55 specific register
424 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
425 #define P1_EXT__x__x__x__x__x__x__T2EX__T2
427 // end of definitions for the Atmel AT89C55 and AT89LV55 microcontrollers
430 // definitions for the Dallas DS5000
431 #ifdef MICROCONTROLLER_DS5000
432 #ifdef MICROCONTROLLER_DEFINED
433 #define MCS51REG_ERROR
435 #ifndef MICROCONTROLLER_DEFINED
436 #define MICROCONTROLLER_DEFINED
438 #ifdef MCS51REG_ENABLE_WARNINGS
439 #warning Selected HW: DS5000
445 #define PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
456 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
458 #define IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
459 #define MCON__SL__PAA__ECE2__RA32_8__PA0__PA1__PA2__PA3
465 // end of definitions for the Dallas DS5000
468 // definitions for the Dallas DS5001
469 #ifdef MICROCONTROLLER_DS5001
470 #ifdef MICROCONTROLLER_DEFINED
471 #define MCS51REG_ERROR
473 #ifndef MICROCONTROLLER_DEFINED
474 #define MICROCONTROLLER_DEFINED
476 #ifdef MCS51REG_ENABLE_WARNINGS
477 #warning Selected HW: DS5001
483 #define PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
494 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
496 #define IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
500 #define MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL
505 #define STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF
509 // end of definitions for the Dallas DS5001
512 // definitions for the Dallas DS80C320 and DS80C323 microcontrollers
513 #ifdef MICROCONTROLLER_DS80C32X
514 #ifdef MICROCONTROLLER_DEFINED
515 #define MCS51REG_ERROR
517 #ifndef MICROCONTROLLER_DEFINED
518 #define MICROCONTROLLER_DEFINED
520 #ifdef MCS51REG_ENABLE_WARNINGS
521 #warning Selected HW: Dallas DS80C320 or DS80C323
528 #define PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
540 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
542 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
546 // 8052 specific registers
547 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
552 // DS80C320 specific register
555 #define DPS__x__x__x__x__x__x__x__SEL
556 #define CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
557 #define EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
564 #define STATUS__PIP__HIP__LIP__x__x__x__x__x
566 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
567 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
569 #define EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
570 #define EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2
572 // end of definitions for the Dallas DS80C320 and DS80C323 microcontrollers
575 // definitions for the Dallas DS80C390
576 #ifdef MICROCONTROLLER_DS80C390
577 #ifdef MICROCONTROLLER_DEFINED
578 #define MCS51REG_ERROR
580 #ifndef MICROCONTROLLER_DEFINED
581 #define MICROCONTROLLER_DEFINED
583 #ifdef MCS51REG_ENABLE_WARNINGS
584 #warning Selected HW: Dallas DS80C390
591 #define PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
603 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
605 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
609 // 8052 specific registers
610 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
615 // DS80C390 specific register
619 #define DPS__ID1__ID0__TSL__x__x__x__x__SEL
620 #define CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
621 #define EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
629 #define ACON__x__x__x__x__x__SA__AM1__AM0
660 #define PMR__CD1__CD0__SWB__CTM__4X_2X__ALEOFF__x__x
661 #define STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
662 #define MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0
664 #define T2MOD__x__x__x__D13T1__D13T2__x__T2OE__DCEN
681 #define EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2
692 #define EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
699 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
701 // end of definitions for the Dallas DS80C390
703 // definitions for the Dallas DS89C420 microcontroller
704 #ifdef MICROCONTROLLER_DS89C420
705 #ifdef MICROCONTROLLER_DEFINED
706 #define MCS51REG_ERROR
708 #ifndef MICROCONTROLLER_DEFINED
709 #define MICROCONTROLLER_DEFINED
711 #ifdef MCS51REG_ENABLE_WARNINGS
712 #warning Selected HW: Dallas DS89C420
719 #define PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
731 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
733 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
737 // 8052 specific registers
738 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
743 // DS8XC420 specific registers
744 #define ACON__PAGEE__PAGES1__PAGES0__x__x__x__x__x
747 #define DPS__ID1__ID0__TSL__AID__x__x__x__SEL
748 #define CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
750 #define IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
751 #define IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
752 #define EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
753 #define PMR__CD1__CD0__SWB__CTM__4X_2X__ALEON__DME1__DME0
760 #define STATUS__PIS2__PIS1__PIS0__x__SPTA1__SPRA1__SPTA0__SPRA0
762 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
763 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
764 #define ROMSIZE__x__x__x__x__PRAME__RMS2__RMS1__RMS0
766 #define EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
767 #define EIP0__x__x__x__LPWDI__LPX5__LPX4__LPX3__LPX2
768 #define EIP1__x__x__x__MPWDI__MPX5__MPX4__MPX3__MPX2
769 #define FCNTL__FBUSY__FERR__x__x__FC3__FC2__FC1__FC0
771 // end of definitions for the Dallas DS89C420 microcontroller
773 // definitions for the Dallas DS87C520 and DS83C520 microcontrollers
774 #ifdef MICROCONTROLLER_DS8XC520
775 #ifdef MICROCONTROLLER_DEFINED
776 #define MCS51REG_ERROR
778 #ifndef MICROCONTROLLER_DEFINED
779 #define MICROCONTROLLER_DEFINED
781 #ifdef MCS51REG_ENABLE_WARNINGS
782 #warning Selected HW: Dallas DS87C520 or DS85C520
789 #define PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
801 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
803 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
807 // 8052 specific registers
808 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
813 // DS8XC520 specific registers
816 #define DPS__x__x__x__x__x__x__x__SEL
817 #define CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
818 #define EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
819 #define PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1__DME0
826 #define STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
828 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
829 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
831 #define ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0
834 #define EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
835 #define EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2
837 // end of definitions for the Dallas DS87C520 and DS83C520 microcontrollers
840 // definitions for the Philips P80C552 microcontroller
841 #ifdef MICROCONTROLLER_P80C552
842 #ifdef MICROCONTROLLER_DEFINED
843 #define MCS51REG_ERROR
845 #ifndef MICROCONTROLLER_DEFINED
846 #define MICROCONTROLLER_DEFINED
848 #ifdef MCS51REG_ENABLE_WARNINGS
849 #warning Selected HW: Philips P80C552
856 #define PCON__SMOD__x__x__WLE__GF1__GF0__PD__IDL
867 #define IE__EA__EAD__ES1__ES0__ET1__EX1__ET0__EX0
869 #define IP__x__PAD__PS1__PS0__PT1__PX1__PT0__PX0
873 // P80C552 specific register-names
874 #define S0BUF // same as SBUF, set in mcs51reg.h
875 #define S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI
876 // P80C552 specific registers
878 #define ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0
879 #define CTCON__CTN3__CTP3__CTN2__CTP2__CTN1__CTP1__CTN0__CTP0
894 #define IEN1__ET2__ECM2__ECM1__ECM0__ECT3__ECT2__ECT1__ECT0
895 #define IP1__PT2__PCM2__PCM1__PCM0__PCT3__PCT2__PCT1__PCT0
899 #define P1_EXT__SDA__SCL__RT2__T2__CT3I__CT2I__CT1I__CT0I
900 #define P4_AT_0XC0__CMT0__CMT1__CMSR5__CMSR4__CMSR3__CMSR2__CMSR1__CMSR0
902 #define RTE__TP47__TP46__RP45__RP44__RP43__RP42__RP41__RP40
903 #define S1ADR__x__x__x__x__x__x__x__GC
904 #define S1DAT_AT_0XDA
905 #define S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x
906 #define S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0
907 #define STE__TG47__TG46__SP45__SP44__SP43__SP42__SP41__SP40
910 #define TM2CON__T2IS1__T2IS0__T2ER__T2B0__T2P1__T2P0__T2MS1__T2MS0
911 #define TM2IR__T20V__CMI2__CMI1__CMI0__CTI3__CTI2__CTI1__CTI0
914 // end of definitions for the Philips P80C552 microcontroller
917 // definitions for the Philips P89C668
918 #ifdef MICROCONTROLLER_P89C668
919 #ifdef MICROCONTROLLER_DEFINED
920 #define MCS51REG_ERROR
922 #ifndef MICROCONTROLLER_DEFINED
923 #define MICROCONTROLLER_DEFINED
925 #ifdef MCS51REG_ENABLE_WARNINGS
926 #warning Selected HW: P89C668
929 #define P0_EXT__AD7__AD6__AD5__AD4__AD3__AD2__AD1__AD0
931 #define P1_EXT__SDA__SCL__CEX2__CEX1__CEX0__ECI__T2EX__T2
933 #define P2_EXT__AD15__AD14__AD13__AD12__AD11__AD10__AD9__AD8
935 #define P3_EXT__x__x__CEX4__CEX3__x__x__x__x
941 #define PCON__SMOD1__SMOD0__x__POF__GF1__GF0__PD__IDL
947 #define S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI
948 #define S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0
955 #define SADEN_AT_0XB9
956 #define S1IST_AT_0XDC
957 #define S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x
958 #define S1DAT_AT_0XDA
959 #define S1ADR__x__x__x__x__x__x__x__GC
961 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
962 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
967 #define IEN0__EA__EC__ES1__ES0__ET1__EX1__ET0__EX0
968 #define IEN1__x__x__x__x__x__x__x__ET2
969 #define IP__PT2__PPC__PS1__PS0__PT1__PX1__PT0__PX0
970 #define IPH__PT2H__PPCH__PS1H__PS0H__PT1H__PX1H__PT0H__PX0H
971 #define CCON__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0
972 #define CMOD__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
973 #define AUXR__x__x__x__x__x__x__EXTRAM__A0
974 #define AUXR1__x__x__ENBOOT__x__GF2__0__x__DPS
975 #define WDTRST_AT_0XA6
976 #define CCAPM0_AT_0XC2
977 #define CCAPM1_AT_0XC3
978 #define CCAPM2_AT_0XC4
979 #define CCAPM3_AT_0XC5
980 #define CCAPM4_AT_0XC6
981 #define CCAP0L_AT_0XEA
982 #define CCAP1L_AT_0XEB
983 #define CCAP2L_AT_0XEC
984 #define CCAP3L_AT_0XED
985 #define CCAP4L_AT_0XEE
988 #define CCAP0H_AT_0XFA
989 #define CCAP1H_AT_0XFB
990 #define CCAP2H_AT_0XFC
991 #define CCAP3H_AT_0XFD
992 #define CCAP4H_AT_0XFE
994 // end of definitions for the Philiüs P89C668
997 // definitions for the Infineon / Siemens SAB80515 & SAB80535
998 #ifdef MICROCONTROLLER_SAB80515
999 #ifdef MICROCONTROLLER_DEFINED
1000 #define MCS51REG_ERROR
1002 #ifndef MICROCONTROLLER_DEFINED
1003 #define MICROCONTROLLER_DEFINED
1005 #ifdef MCS51REG_ENABLE_WARNINGS
1006 #warning Selected HW: Infineon / Siemens SAB80515 & SAB80535
1008 // 8051 register set without IP
1013 #define PCON__SMOD__x__x__x__x__x__x__x
1024 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
1029 // SAB80515 specific registers
1030 #define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
1031 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
1032 #define IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
1041 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
1048 #define DAPR__SAB80515
1052 // end of definitions for the Infineon / Siemens SAB80515
1055 // definitions for the Infineon / Siemens SAB80515A
1056 #ifdef MICROCONTROLLER_SAB80515A
1057 #ifdef MICROCONTROLLER_DEFINED
1058 #define MCS51REG_ERROR
1060 #ifndef MICROCONTROLLER_DEFINED
1061 #define MICROCONTROLLER_DEFINED
1063 #ifdef MCS51REG_ENABLE_WARNINGS
1064 #warning Selected HW: Infineon / Siemens SAB80515A
1066 // 8051 register set without IP
1071 #define PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
1082 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
1087 // SAB80515A specific registers
1088 #define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
1089 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
1090 #define IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
1091 #define IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
1100 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
1117 // end of definitions for the Infineon / Siemens SAB80515A
1120 // definitions for the Infineon / Siemens SAB80517
1121 #ifdef MICROCONTROLLER_SAB80517
1122 #ifdef MICROCONTROLLER_DEFINED
1123 #define MCS51REG_ERROR
1125 #ifndef MICROCONTROLLER_DEFINED
1126 #define MICROCONTROLLER_DEFINED
1128 #ifdef MCS51REG_ENABLE_WARNINGS
1129 #warning Selected HW: Infineon / Siemens SAB80517
1131 // 8051 register set without IP, SCON & SBUF
1136 #define PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
1147 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
1152 // SAB80517 specific registers
1153 #define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
1154 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
1155 #define IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
1156 #define IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
1157 #define IEN2__SAB80517
1187 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
1190 #define CTCOM_AT_0XE1
1198 #define DAPR__SAB80517
1213 #define S0CON__SM0__SM1__SM20__REN0__TB80__RB80__TI0__RI0
1217 #define S1CON_AT_0X9B
1224 // end of definitions for the Infineon / Siemens SAB80517
1227 // definitions for the Atmel T89C51RD2
1228 #ifdef MICROCONTROLLER_T89C51RD2
1229 #ifdef MICROCONTROLLER_DEFINED
1230 #define MCS51REG_ERROR
1232 #ifndef MICROCONTROLLER_DEFINED
1233 #define MICROCONTROLLER_DEFINED
1235 #ifdef MCS51REG_ENABLE_WARNINGS
1236 #warning Selected HW: T89C51RD2
1239 // 8051 register set
1244 #define PCON__SMOD1__SMOD0__x__POF__GF1__GF0__PD__IDL
1255 #define IE__EA__EC__ET2__ES__ET1__EX1__ET0__EX0
1258 #define IP__x__PPC__PT2__PS__PT1__PX1__PT0__PX0
1263 // 8052 register set
1264 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
1270 // T89C51RD2 register set
1271 #define P4_AT_0XC0__P4_7__P4_6__P4_5__P4_3__P4_2__P4_1__P4_0
1275 #define AUXR1__x__x__x__x__GF3__x__x__DPS
1276 #define WDTRST_AT_0XA6
1277 #define WDTPRG_AT_0XA7
1278 #define AUXR__x__x__M0__x__XRS1__XRS0__EXTRAM__A0
1279 #define IPH__x__PPCH__PT2H__PSH__PT1H__PX1H__PT0H__PX0H
1283 #define CKCON__X2__T0X2__T1X2__T2X2__SiX2__PcaX2__WdX2__x
1284 #define CCON__x__CF__CR__CCF4__CCF3__CCF2__CCF1__CCF0
1285 #define CMOD__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
1286 #define CCAPM0_AT_0XDA
1287 #define CCAPM1_AT_0XDB
1288 #define CCAPM2_AT_0XDC
1289 #define CCAPM3_AT_0XDD
1290 #define CCAPM4_AT_0XDE
1292 #define CCAP0L_AT_0XEA
1293 #define CCAP1L_AT_0XEB
1294 #define CCAP2L_AT_0XEC
1295 #define CCAP3L_AT_0XED
1296 #define CCAP4L_AT_0XEE
1298 #define CCAP0H_AT_0XFA
1299 #define CCAP1H_AT_0XFB
1300 #define CCAP2H_AT_0XFC
1301 #define CCAP3H_AT_0XFD
1302 #define CCAP4H_AT_0XFE
1303 #endif /* MICROCONTROLLER_T89C51RD2 */
1304 /* end of definition for the Atmel T89C51RD2 */
1307 /////////////////////////////////////////////////////////
1308 /// don't specify microcontrollers below this line! ///
1309 /////////////////////////////////////////////////////////
1312 // default microcontroller -> 8051
1313 // use default if no microcontroller specified
1314 #ifndef MICROCONTROLLER_DEFINED
1315 #define MICROCONTROLLER_DEFINED
1316 #ifdef MCS51REG_ENABLE_WARNINGS
1317 #warning No microcontroller defined!
1318 #warning Code generated for the 8051
1320 // 8051 register set
1325 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
1336 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
1338 #define IP__x__x__x__PS__PT1__PX1__PT0__PX0
1343 // end of definitions for the default microcontroller
1346 #ifdef MCS51REG_ERROR
1347 #error Two or more microcontrollers defined!
1350 #ifdef MCS51REG_EXTERNAL_ROM
1351 #ifndef MCS51REG_UNDEFINE_P0
1352 #define MCS51REG_UNDEFINE_P0
1354 #ifndef MCS51REG_UNDEFINE_P2
1355 #define MCS51REG_UNDEFINE_P2
1359 #ifdef MCS51REG_EXTERNAL_RAM
1360 #ifndef MCS51REG_UNDEFINE_P0
1361 #define MCS51REG_UNDEFINE_P0
1363 #ifndef MCS51REG_UNDEFINE_P2
1364 #define MCS51REG_UNDEFINE_P2
1368 #ifdef MCS51REG_UNDEFINE_P0
1372 #ifdef MCS51REG_UNDEFINE_P2
1376 ////////////////////////////////
1377 /// Register definitions ///
1378 /// (In alphabetical order) ///
1379 ////////////////////////////////
1386 #ifdef ACON__PAGEE__PAGES1__PAGES0__x__x__x__x__x
1387 #undef ACON__PAGEE__PAGES1__PAGES0__x__x__x__x__x
1388 sfr at 0x9D ACON ; // DS89C420 specific
1389 // Not directly accessible bits
1395 #ifdef ACON__x__x__x__x__x__SA__AM1__AM0
1396 #undef ACON__x__x__x__x__x__SA__AM1__AM0
1397 sfr at 0x9D ACON ; // DS89C390 specific
1398 // Not directly accessible bits
1406 sfr at 0xC6 ADCH ; // A/D converter high
1411 sfr at 0xD8 ADCON ; // A/D-converter control register SAB80515 specific
1422 // ADCON0 ... Infineon / Siemens also called this register ADCON in the User Manual
1425 sfr at 0xD8 ADCON0 ; // A/D-converter control register 0 SAB80515A &
1426 // Bit registers // SAB80517 specific
1435 // Not directly accessible ADCON0
1436 #define ADCON0_MX0 0x01
1437 #define ADCON0_MX1 0x02
1438 #define ADCON0_MX2 0x04
1439 #define ADCON0_ADM 0x08
1440 #define ADCON0_BSY 0x10
1441 #define ADCON0_ADEX 0x20
1442 #define ADCON0_CLK 0x40
1443 #define ADCON0_BD 0x80
1448 sfr at 0xDC ADCON1 ; // A/D-converter control register 1 SAB80515A & SAB80517 specific
1449 // Not directly accessible ADCON1
1450 #define ADCON1_MX0 0x01
1451 #define ADCON1_MX1 0x02
1452 #define ADCON1_MX2 0x04
1453 #define ADCON1_ADCL 0x80
1456 #ifdef ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0
1457 #undef ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0
1458 sfr at 0xC5 ADCON ; // A/D control, P80C552 specific
1459 // Not directly accessible Bits.
1466 #define ADC_0 0x40 // different name as ADC0 in P5
1467 #define ADC_1 0x80 // different name as ADC1 in P5
1472 sfr at 0xD9 ADDAT ; // A/D-converter data register SAB80515 specific
1477 sfr at 0xD9 ADDATH ; // A/D data high byte SAB80515A specific
1482 sfr at 0xDA ADDATL ; // A/D data low byte SAB80515A specific
1487 sfr at 0xEF ARCON ; // arithmetic control register SAB80517
1492 sfr at 0x9C AP ; // DS80C390
1495 #ifdef AUXR__x__x__x__x__x__x__EXTRAM__A0
1496 #undef AUXR__x__x__x__x__x__x__EXTRAM__A0
1497 // P89C668 specific, Auxilary
1499 // not bit addressable:
1504 #ifdef AUXR__x__x__M0__x__XRS1__XRS0__EXTRAM__A0
1505 #undef AUXR__x__x__M0__x__XRS1__XRS0__EXTRAM__A0
1517 sbit at 0xF0 BREG_F0 ;
1518 sbit at 0xF1 BREG_F1 ;
1519 sbit at 0xF2 BREG_F2 ;
1520 sbit at 0xF3 BREG_F3 ;
1521 sbit at 0xF4 BREG_F4 ;
1522 sbit at 0xF5 BREG_F5 ;
1523 sbit at 0xF6 BREG_F6 ;
1524 sbit at 0xF7 BREG_F7 ;
1527 #ifdef AUXR1__x__x__x__x__GF3__x__x__DPS
1528 #undef AUXR1__x__x__x__x__GF3__x__x__DPS
1534 #ifdef AUXR1__x__x__ENBOOT__x__GF2__0__x__DPS
1535 #undef AUXR1__x__x__ENBOOT__x__GF2__0__x__DPS
1536 // P89C668 specific, Auxilary 1
1540 #define ALWAYS_ZERO 0x04
1547 // Not directly accessible bits
1558 sfr at 0xA3 C0C ; // DS80C390 specific
1559 // Not directly accessible bits
1572 sfr at 0xA5 C0IR ; // DS80C390 specific
1573 // Not directly accessible bits
1586 sfr at 0xAB C0M1C ; // DS80C390 specific
1587 // Not directly accessible bits
1589 #define ROW_TIH 0x02
1600 sfr at 0xAC C0M2C ; // DS80C390 specific
1605 sfr at 0xAD C0M3C ; // DS80C390 specific
1610 sfr at 0xAE C0M4C ; // DS80C390 specific
1615 sfr at 0xAF C0M5C ; // DS80C390 specific
1620 sfr at 0xB3 C0M6C ; // DS80C390 specific
1625 sfr at 0xB4 C0M7C ; // DS80C390 specific
1630 sfr at 0xB5 C0M8C ; // DS80C390 specific
1635 sfr at 0xB6 C0M9C ; // DS80C390 specific
1640 sfr at 0xB7 C0M10C ; // DS80C390 specific
1645 sfr at 0xBB C0M11C ; // DS80C390 specific
1650 sfr at 0xBC C0M12C ; // DS80C390 specific
1655 sfr at 0xBD C0M13C ; // DS80C390 specific
1660 sfr at 0xBE C0M14C ; // DS80C390 specific
1665 sfr at 0xBF C0M15C ; // DS80C390 specific
1670 sfr at 0xA7 C0RE ; // DS80C390 specific
1675 sfr at 0x96 C0RMS0 ; // DS80C390 specific
1680 sfr at 0x97 C0RMS1 ; // DS80C390 specific
1685 sfr at 0xA4 C0S ; // DS80C390 specific
1686 // Not directly accessible bits
1693 #define EC96_128 0x40
1699 sfr at 0xA6 C0TE ; // DS80C390 specific
1704 sfr at 0x9E C0TMA0 ; // DS80C390 specific
1709 sfr at 0x9F C0TMA1 ; // DS80C390 specific
1714 sfr at 0xE3 C1C ; // DS80C390 specific
1715 // Not directly accessible bits
1728 sfr at 0xE5 C1IR ; // DS80C390 specific
1729 // Not directly accessible bits
1742 sfr at 0xE7 C1RE ; // DS80C390 specific
1747 sfr at 0xEB C1M1C ; // DS80C390 specific
1752 sfr at 0xEC C1M2C ; // DS80C390 specific
1757 sfr at 0xED C1M3C ; // DS80C390 specific
1762 sfr at 0xEE C1M4C ; // DS80C390 specific
1767 sfr at 0xEF C1M5C ; // DS80C390 specific
1772 sfr at 0xF3 C1M6C ; // DS80C390 specific
1777 sfr at 0xF4 C1M7C ; // DS80C390 specific
1782 sfr at 0xF5 C1M8C ; // DS80C390 specific
1787 sfr at 0xF6 C1M9C ; // DS80C390 specific
1792 sfr at 0xF7 C1M10C ; // DS80C390 specific
1797 sfr at 0xFB C1M11C ; // DS80C390 specific
1802 sfr at 0xFC C1M12C ; // DS80C390 specific
1807 sfr at 0xFD C1M13C ; // DS80C390 specific
1812 sfr at 0xFE C1M14C ; // DS80C390 specific
1817 sfr at 0xFF C1M15C ; // DS80C390 specific
1822 sfr at 0xE4 C1S ; // DS80C390 specific
1823 // Not directly accessible bits
1836 sfr at 0xE6 C1TE ; // DS80C390 specific
1841 sfr at 0xD6 C1RSM0 ; // DS80C390 specific
1846 sfr at 0xD7 C1RSM1 ; // DS80C390 specific
1851 sfr at 0xDE C1TMA0 ; // DS80C390 specific
1856 sfr at 0xDF C1TMA1 ; // DS80C390 specific
1861 sfr at 0xC9 CC4EN ; // compare/capture 4 enable register SAB80517 specific
1864 #ifdef CCAP0H_AT_0XFA
1865 #undef CCAP0H_AT_0XFA
1869 #ifdef CCAP1H_AT_0XFB
1870 #undef CCAP1H_AT_0XFB
1874 #ifdef CCAP2H_AT_0XFC
1875 #undef CCAP2H_AT_0XFC
1879 #ifdef CCAP3H_AT_0XFD
1880 #undef CCAP3H_AT_0XFD
1884 #ifdef CCAP4H_AT_0XFE
1885 #undef CCAP4H_AT_0XFE
1889 #ifdef CCAP0L_AT_0XEA
1890 #undef CCAP0L_AT_0XEA
1894 #ifdef CCAP1L_AT_0XEB
1895 #undef CCAP1L_AT_0XEB
1899 #ifdef CCAP2L_AT_0XEC
1900 #undef CCAP2L_AT_0XEC
1904 #ifdef CCAP3L_AT_0XED
1905 #undef CCAP3L_AT_0XED
1909 #ifdef CCAP4L_AT_0XEE
1910 #undef CCAP4L_AT_0XEE
1914 #ifdef CCAPM0_AT_0XC2
1915 #undef CCAPM0_AT_0XC2
1916 // P89C668 specific, Capture module:
1917 sfr at 0xC2 CCAPM0 ;
1920 #ifdef CCAPM0_AT_0XDA
1921 #undef CCAPM0_AT_0XDA
1932 #ifdef CCAPM1_AT_0XC3
1933 #undef CCAPM1_AT_0XC3
1934 sfr at 0xC3 CCAPM1 ;
1937 #ifdef CCAPM1_AT_0XDB
1938 #undef CCAPM1_AT_0XDB
1942 #ifdef CCAPM2_AT_0XC4
1943 #undef CCAPM2_AT_0XC4
1944 sfr at 0xC4 CCAPM2 ;
1947 #ifdef CCAPM2_AT_0XDC
1948 #undef CCAPM2_AT_0XDC
1949 sfr at 0x0DC CCAPM2;
1952 #ifdef CCAPM3_AT_0XC5
1953 #undef CCAPM3_AT_0XC5
1954 sfr at 0xC5 CCAPM3 ;
1957 #ifdef CCAPM3_AT_0XDD
1958 #undef CCAPM3_AT_0XDD
1959 sfr at 0x0DD CCAPM3;
1962 #ifdef CCAPM4_AT_0XDE
1963 #undef CCAPM4_AT_0XDE
1964 sfr at 0x0DE CCAPM4;
1967 #ifdef CCAPM4_AT_0XC6
1968 #undef CCAPM4_AT_0XC6
1969 sfr at 0xC6 CCAPM4 ;
1974 sfr at 0xC1 CCEN ; // compare/capture enable register SAB80515 specific
1979 sfr at 0xC3 CCH1 ; // compare/capture register 1, high byte SAB80515 specific
1984 sfr at 0xC5 CCH2 ; // compare/capture register 2, high byte SAB80515 specific
1989 sfr at 0xC7 CCH3 ; // compare/capture register 3, high byte SAB80515 specific
1994 sfr at 0xCF CCH4 ; // compare/capture register 4, high byte SAB80515 specific
1999 sfr at 0xC2 CCL1 ; // compare/capture register 1, low byte SAB80515 specific
2004 sfr at 0xC4 CCL2 ; // compare/capture register 2, low byte SAB80515 specific
2009 sfr at 0xC6 CCL3 ; // compare/capture register 3, low byte SAB80515 specific
2014 sfr at 0xCE CCL4 ; // compare/capture register 4, low byte SAB80515 specific
2017 #ifdef CCON__x__CF__CR__CCF4__CCF3__CCF2__CCF1__CCF0
2018 #undef CCON__x__CF__CR__CCF4__CCF3__CCF2__CCF1__CCF0
2019 sfr at 0xD8 CCON; // T89C51RD2 specific register
2030 #ifdef CCON__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0
2031 #undef CCON__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0
2032 // P89C668 specific, PCA Counter control:
2050 #ifdef CMOD__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
2051 #undef CMOD__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
2052 // P89C668 specific, PCA Counter mode:
2054 // not bit addressable:
2062 #ifdef CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
2063 #undef CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
2064 sfr at 0x8E CKCON ; // DS80C320 & DS80C390 specific
2065 // Not directly accessible Bits.
2076 #ifdef CKCON__X2__T0X2__T1X2__T2X2__SiX2__PcaX2__WdX2__x
2077 #undef CKCON__X2__T0X2__T1X2__T2X2__SiX2__PcaX2__WdX2__x
2090 sfr at 0x96 CKMOD ; // DS89C420 specific
2091 // Not directly accessible Bits.
2104 sfr at 0xF6 CMEN ; // compare enable register SAB80517 specific
2109 sfr at 0xD3 CMH0 ; // compare register 0 high byte SAB80517 specific
2114 sfr at 0xD5 CMH1 ; // compare register 1 high byte SAB80517 specific
2119 sfr at 0xD7 CMH2 ; // compare register 2 high byte SAB80517 specific
2124 sfr at 0xE3 CMH3 ; // compare register 3 high byte SAB80517 specific
2129 sfr at 0xE5 CMH4 ; // compare register 4 high byte SAB80517 specific
2134 sfr at 0xE7 CMH5 ; // compare register 5 high byte SAB80517 specific
2139 sfr at 0xF3 CMH6 ; // compare register 6 high byte SAB80517 specific
2144 sfr at 0xF5 CMH7 ; // compare register 7 high byte SAB80517 specific
2149 sfr at 0xC9 CMH0 ; // Compare high 0, P80C552 specific
2154 sfr at 0xCA CMH1 ; // Compare high 1, P80C552 specific
2159 sfr at 0xCB CMH2 ; // Compare high 2, P80C552 specific
2164 sfr at 0xD2 CML0 ; // compare register 0 low byte SAB80517 specific
2169 sfr at 0xD4 CML1 ; // compare register 1 low byte SAB80517 specific
2174 sfr at 0xD6 CML2 ; // compare register 2 low byte SAB80517 specific
2179 sfr at 0xE2 CML3 ; // compare register 3 low byte SAB80517 specific
2184 sfr at 0xE4 CML4 ; // compare register 4 low byte SAB80517 specific
2189 sfr at 0xE6 CML5 ; // compare register 5 low byte SAB80517 specific
2194 sfr at 0xF2 CML6 ; // compare register 6 low byte SAB80517 specific
2199 sfr at 0xF4 CML7 ; // compare register 7 low byte SAB80517 specific
2204 sfr at 0xA9 CML0 ; // Compare low 0, P80C552 specific
2209 sfr at 0xAA CML1 ; // Compare low 1, P80C552 specific
2214 sfr at 0xAB CML2 ; // Compare low 2, P80C552 specific
2217 #ifdef CMOD__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
2218 #undef CMOD__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
2229 sfr at 0xF7 CMSEL ; // compare input select SAB80517
2234 sfr at 0xCE COR ; // Dallas DS80C390 specific
2247 sfr at 0xC1 CRC ; // Dallas DS5001 specific
2258 sfr at 0xCB CRCH ; // compare/reload/capture register, high byte SAB80515 specific
2263 sfr at 0xC3 CRCHIGH ; // DS5001 specific
2268 sfr at 0xCA CRCL ; // compare/reload/capture register, low byte SAB80515 specific
2273 sfr at 0xC2 CRCLOW ; // DS5001 specific
2276 #ifdef CTCOM_AT_0XE1
2277 #undef CTCOM_AT_0XE1
2278 sfr at 0xE1 CTCON ; // com.timer control register SAB80517
2281 #ifdef CTCON__CTN3__CTP3__CTN2__CTP2__CTN1__CTP1__CTN0__CTP0
2282 #undef CTCON__CTN3__CTP3__CTN2__CTP2__CTN1__CTP1__CTN0__CTP0
2283 sfr at 0xEB CTCON ; // Capture control, P80C552 specific
2284 // Not directly accessible Bits.
2297 sfr at 0xCC CTH0 ; // Capture high 0, P80C552 specific
2302 sfr at 0xCD CTH1 ; // Capture high 1, P80C552 specific
2307 sfr at 0xCE CTH2 ; // Capture high 2, P80C552 specific
2312 sfr at 0xCF CTH3 ; // Capture high 3, P80C552 specific
2317 sfr at 0xAC CTL0 ; // Capture low 0, P80C552 specific
2322 sfr at 0xAD CTL1 ; // Capture low 1, P80C552 specific
2327 sfr at 0xAE CTL2 ; // Capture low 2, P80C552 specific
2332 sfr at 0xAF CTL3 ; // Capture low 3, P80C552 specific
2337 sfr at 0xDF CTRELH ; // com.timer rel register high byte SAB80517
2342 sfr at 0xDE CTRELL ; // com.timer rel register low byte SAB80517
2345 #ifdef DAPR__SAB80515
2346 #undef DAPR__SAB80515
2347 sfr at 0xD8 DAPR ; // D/A-converter program register SAB80515 specific
2350 #ifdef DAPR__SAB80517
2351 #undef DAPR__SAB80517
2352 sfr at 0xDA DAPR ; // D/A-converter program register SAB80517 specific
2358 sfr at 0x83 DP0H ; // Alternate name for AT89S53
2363 sfr at 0x85 DPH1 ; // DS80C320 specific
2364 sfr at 0x85 DP1H ; // Alternate name for AT89S53
2369 sfr at 0x82 DPL ; // Alternate name for AT89S53
2375 sfr at 0x84 DPL1 ; // DS80C320 specific
2376 sfr at 0x84 DP1L ; // Alternate name for AT89S53
2379 #ifdef DPS__x__x__x__x__x__x__x__SEL
2380 #undef DPS__x__x__x__x__x__x__x__SEL
2382 // Not directly accessible DPS Bit. DS80C320 & DPS8XC520 specific
2386 #ifdef DPS__ID1__ID0__TSL__x__x__x__x__SEL
2387 #undef DPS__ID1__ID0__TSL__x__x__x__x__SEL
2389 // Not directly accessible DPS Bit. DS89C390 specific
2396 #ifdef DPS__ID1__ID0__TSL__AID__x__x__x__SEL
2397 #undef DPS__ID1__ID0__TSL__AID__x__x__x__SEL
2399 // Not directly accessible DPS Bit. DS89C420 specific
2409 sfr at 0x92 DPSEL ; // data pointer select register SAB80517
2414 sfr at 0x93 DPX1 ; // DS80C390 specific
2419 sfr at 0x95 DPX1 ; // DS80C390 specific
2439 #ifdef EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
2440 #undef EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
2442 // Bit registers DS80C320 specific
2450 #ifdef EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2
2451 #undef EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2
2453 // Bit registers DS80C390 specific
2461 sbit at 0xEF CANBIE ;
2464 #ifdef EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2
2465 #undef EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2
2467 // Bit registers DS80C320 specific
2475 #ifdef EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
2476 #undef EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
2478 // Bit registers DS80C320 specific
2486 sbit at 0xFF CANBIP ;
2489 #ifdef EIP0__x__x__x__LPWDI__LPX5__LPX4__LPX3__LPX2
2490 #undef EIP0__x__x__x__LPWDI__LPX5__LPX4__LPX3__LPX2
2492 // Bit registers DS89C420 specific
2497 sbit at 0xFC LPWDI ;
2500 #ifdef EIP1__x__x__x__MPWDI__MPX5__MPX4__MPX3__MPX2
2501 #undef EIP1__x__x__x__MPWDI__MPX5__MPX4__MPX3__MPX2
2503 // Not directly accessible Bits DS89C420 specific
2514 // Not directly accessible Bits DS80C390 specific
2519 #ifdef EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
2520 #undef EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
2522 // Not directly accessible EXIF Bits DS80C320 specific
2532 #ifdef EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
2533 #undef EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
2535 // Not directly accessible EXIF Bits DS87C520 specific
2546 #ifdef EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
2547 #undef EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
2549 // Not directly accessible EXIF Bits DS80C390 & DS89C420 specific
2560 #ifdef FCNTL__FBUSY__FERR__x__x__FC3__FC2__FC1__FC0
2561 #undef FCNTL__FBUSY__FERR__x__x__FC3__FC2__FC1__FC0
2563 // Not directly accessible DS89C420 specific
2591 #ifdef IE__EA__x__x__ES__ET1__EX1__ET0__EX0
2592 #undef IE__EA__x__x__ES__ET1__EX1__ET0__EX0
2603 #ifdef IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
2604 #undef IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
2612 sbit at 0xAD ET2 ; // Enable timer2 interrupt
2616 #ifdef IE__EA__EAD__ES1__ES0__ET1__EX1__ET0__EX0
2617 #undef IE__EA__EAD__ES1__ES0__ET1__EX1__ET0__EX0
2618 sfr at 0xA8 IE ; // same as IEN0 - Interrupt enable 0, P80C552 specific
2619 sfr at 0xA8 IEN0 ; // alternate name
2631 #ifdef IE__EA__EC__ET2__ES__ET1__EX1__ET0__EX0
2632 #undef IE__EA__EC__ET2__ES__ET1__EX1__ET0__EX0
2644 #ifdef IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
2645 #undef IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
2653 sbit at 0xAC ES0 ; // Alternate name
2654 sbit at 0xAD ET2 ; // Enable timer2 interrupt
2659 #ifdef IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
2660 #undef IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
2662 sfr at 0xA8 IEN0 ; // Alternate name
2663 // Bit registers for the SAB80515 and compatible IE
2670 sbit at 0xAD ET2 ; // Enable timer 2 overflow SAB80515 specific
2671 sbit at 0xAE WDT ; // watchdog timer reset - SAB80515 specific
2673 sbit at 0xAF EAL ; // EA as called by Infineon / Siemens
2676 #ifdef IEN0__EA__EC__ES1__ES0__ET1__EX1__ET0__EX0
2677 #undef IEN0__EA__EC__ES1__ES0__ET1__EX1__ET0__EX0
2691 #ifdef IEN1__x__x__x__x__x__x__x__ET2
2692 #undef IEN1__x__x__x__x__x__x__x__ET2
2693 // P89C668 specific bit registers
2699 #ifdef IEN1__ET2__ECM2__ECM1__ECM0__ECT3__ECT2__ECT1__ECT0
2700 #undef IEN1__ET2__ECM2__ECM1__ECM0__ECT3__ECT2__ECT1__ECT0
2701 sfr at 0xE8 IEN1 ; // Interrupt enable 1, P80C552 specific
2713 #ifdef IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
2714 #undef IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
2715 sfr at 0xB8 IEN1 ; // interrupt enable register - SAB80515 specific
2717 sbit at 0xB8 EADC ; // A/D converter interrupt enable
2723 sbit at 0xBE SWDT ; // watchdog timer start/reset
2724 sbit at 0xBF EXEN2 ; // timer2 external reload interrupt enable
2727 #ifdef IEN2__SAB80517
2728 #undef IEN2__SAB80517
2729 sfr at 0x9A IEN2 ; // interrupt enable register 2 SAB80517
2732 #ifdef IP__x__x__x__PS__PT1__PX1__PT0__PX0
2733 #undef IP__x__x__x__PS__PT1__PX1__PT0__PX0
2743 #ifdef IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
2744 #undef IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
2752 sbit at 0xBC PS0 ; // alternate name
2756 #ifdef IP__x__PAD__PS1__PS0__PT1__PX1__PT0__PX0
2757 #undef IP__x__PAD__PS1__PS0__PT1__PX1__PT0__PX0
2758 sfr at 0xB8 IP ; // Interrupt priority 0, P80C552 specific
2759 sfr at 0xB8 IP0 ; // alternate name
2770 #ifdef IP__x__PPC__PT2__PS__PT1__PX1__PT0__PX0
2771 #undef IP__x__PPC__PT2__PS__PT1__PX1__PT0__PX0
2783 #ifdef IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
2784 #undef IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
2796 #ifdef IP__PT2__PPC__PS1__PS0__PT1__PX1__PT0__PX0
2797 #undef IP__PT2__PPC__PS1__PS0__PT1__PX1__PT0__PX0
2798 // P89C668 specific:
2811 #ifdef IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
2812 #undef IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
2823 #ifdef IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
2824 #undef IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
2825 sfr at 0xA9 IP0 ; // interrupt priority register SAB80515 specific
2826 // Not directly accessible IP0 bits
2836 #ifdef IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
2837 #undef IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
2838 sfr at 0xB8 IP0 ; // interrupt priority register DS89C420 specific
2839 // Not directly accessible IP0 bits
2849 #ifdef IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
2850 #undef IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
2851 sfr at 0xB9 IP1 ; // interrupt priority register SAB80515 specific
2852 // Not directly accessible IP1 bits
2861 #ifdef IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
2862 #undef IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
2863 sfr at 0xB1 IP1 ; // interrupt priority register DS89C420 specific
2864 // Not directly accessible IP0 bits
2874 #ifdef IP1__PT2__PCM2__PCM1__PCM0__PCT3__PCT2__PCT1__PCT0
2875 #undef IP1__PT2__PCM2__PCM1__PCM0__PCT3__PCT2__PCT1__PCT0
2876 sfr at 0xF8 IP1 ; // Interrupt priority 1, P80C552 specific
2888 #ifdef IPH__x__PPCH__PT2H__PSH__PT1H__PX1H__PT0H__PX0H
2889 #undef IPH__x__PPCH__PT2H__PSH__PT1H__PX1H__PT0H__PX0H
2900 #ifdef IPH__PT2H__PPCH__PS1H__PS0H__PT1H__PX1H__PT0H__PX0H
2901 #undef IPH__PT2H__PPCH__PS1H__PS0H__PT1H__PX1H__PT0H__PX0H
2902 // P89C668 specific:
2904 // not bit addressable:
2917 sfr at 0xC0 IRCON ; // interrupt control register - SAB80515 specific
2919 sbit at 0xC0 IADC ; // A/D converter irq flag
2920 sbit at 0xC1 IEX2 ; // external interrupt edge detect flag
2925 sbit at 0xC6 TF2 ; // timer 2 owerflow flag
2926 sbit at 0xC7 EXF2 ; // timer2 reload flag
2931 sfr at 0xC0 IRCON0 ; // interrupt control register - SAB80515 specific
2933 sbit at 0xC0 IADC ; // A/D converter irq flag
2934 sbit at 0xC1 IEX2 ; // external interrupt edge detect flag
2939 sbit at 0xC6 TF2 ; // timer 2 owerflow flag
2940 sbit at 0xC7 EXF2 ; // timer2 reload flag
2945 sfr at 0xD1 IRCON1 ; // interrupt control register - SAB80515 specific
2950 sfr at 0xD3 MA ; // DS80C390
2955 sfr at 0xD4 MB ; // DS80C390
2960 sfr at 0xD5 MC ; // DS80C390
2965 sfr at 0xD1 MCNT0 ; // DS80C390
2978 sfr at 0xD2 MCNT1 ; // DS80C390
2984 #ifdef MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0
2985 #undef MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0
2986 sfr at 0xC6 MCON ; // DS80C390
2996 #ifdef MCON__PA3__PA2__PA1__PA0__RA32_8__ECE2__PAA__SL
2997 #undef MCON__PA3__PA2__PA1__PA0__RA32_8__ECE2__PAA__SL
2998 sfr at 0xC6 MCON ; // DS5000
3009 #ifdef MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL
3010 #undef MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL
3011 sfr at 0xC6 MCON ; // DS5001
3024 sfr at 0xE9 MD0 ; // MUL / DIV register 0 SAB80517
3029 sfr at 0xEA MD1 ; // MUL / DIV register 1 SAB80517
3034 sfr at 0xEB MD2 ; // MUL / DIV register 2 SAB80517
3039 sfr at 0xEC MD3 ; // MUL / DIV register 3 SAB80517
3044 sfr at 0xED MD4 ; // MUL / DIV register 4 SAB80517
3049 sfr at 0xEE MD5 ; // MUL / DIV register 5 SAB80517
3054 sfr at 0xEA MXAX ; // Dallas DS80C390
3071 #ifdef P0_EXT__AD7__AD6__AD5__AD4__AD3__AD2__AD1__AD0
3072 #undef P0_EXT__AD7__AD6__AD5__AD4__AD3__AD2__AD1__AD0
3073 // P89C668 alternate names for bits in P0
3098 #ifdef P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
3099 #undef P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
3100 // P1 alternate functions
3111 #ifdef P1_EXT__SDA__SCL__CEX2__CEX1__CEX0__ECI__T2EX__T2
3112 #undef P1_EXT__SDA__SCL__CEX2__CEX1__CEX0__ECI__T2EX__T2
3113 // P89C669 alternate names for bits at P1
3114 // P1_EXT__SDA__SCL__CEX2__CEX1__CEX0__ECI__T2EX__T2
3125 #ifdef P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
3126 sbit at 0x90 INT3_CC0 ; // P1 alternate functions - SAB80515 specific
3127 sbit at 0x91 INT4_CC1 ;
3128 sbit at 0x92 INT5_CC2 ;
3129 sbit at 0x93 INT6_CC3 ;
3132 sbit at 0x96 CLKOUT ;
3136 #ifdef P1_EXT__CT0I__CT1I__CT2I__CT3I__T2__RT2__SCL__SDA
3137 #undef P1_EXT__CT0I__CT1I__CT2I__CT3I__T2__RT2__SCL__SDA
3139 sbit at 0x90 CT0I ; // Port 1 alternate functions, P80C552 specific
3149 #ifdef P1_EXT__x__x__x__x__x__x__T2EX__T2
3150 #undef P1_EXT__x__x__x__x__x__x__T2EX__T2
3151 // P1 alternate functions
3170 #ifdef P2_EXT__AD15__AD14__AD13__AD12__AD11__AD10__AD9__AD8
3171 #undef P2_EXT__AD15__AD14__AD13__AD12__AD11__AD10__AD9__AD8
3172 // P89C668 specific bit registers at P2:
3193 #ifndef MCS51REG_EXTERNAL_RAM
3206 #ifndef MCS51REG_EXTERNAL_RAM
3212 #ifdef P3_EXT__x__x__CEX4__CEX3__x__x__x__x
3213 #undef P3_EXT__x__x__CEX4__CEX3__x__x__x__x
3214 // P89C668 specific bit registers at P3 (alternate names)
3221 sfr at 0x80 P4 ; // Port 4 - DS80C390
3233 #ifdef P4_AT_0XC0__CMT0__CMT1__CMSR5__CMSR4__CMSR3__CMSR2__CMSR1__CMSR0
3234 #undef P4_AT_0XC0__CMT0__CMT1__CMSR5__CMSR4__CMSR3__CMSR2__CMSR1__CMSR0
3235 sfr at 0xC0 P4 ; // Port 4, P80C552 specific
3237 sbit at 0xC0 CMSR0 ;
3238 sbit at 0xC1 CMSR1 ;
3239 sbit at 0xC2 CMSR2 ;
3240 sbit at 0xC3 CMSR3 ;
3241 sbit at 0xC4 CMSR4 ;
3242 sbit at 0xC5 CMSR5 ;
3247 #ifdef P4_AT_0XC0__P4_7__P4_6__P4_5__P4_3__P4_2__P4_1__P4_0
3248 #undef P4_AT_0XC0__P4_7__P4_6__P4_5__P4_3__P4_2__P4_1__P4_0
3249 sfr at 0xC0 P4 ; // Port 4, T89C51 specific
3263 sfr at 0xE8 P4 ; // Port 4 - SAB80515 & compatible microcontrollers
3277 sfr at 0x92 P4CNT ; // DS80C390
3278 // Not directly accessible bits
3279 #define P4CNT_0 0x01
3280 #define P4CNT_1 0x02
3281 #define P4CNT_2 0x04
3282 #define P4CNT_3 0x08
3283 #define P4CNT_4 0x10
3284 #define P4CNT_5 0x20
3290 sfr at 0xA1 P5 ; // Port 5 - DS80C390
3295 sfr at 0xE8 P5; // Port 5 - T89C51RD2
3309 sfr at 0xA2 P5CNT ; // DS80C390
3310 // Not directly accessible bits
3311 #define P5CNT_0 0x01
3312 #define P5CNT_1 0x02
3313 #define P5CNT_2 0x04
3317 #define SBCAN0BA 0x40
3318 #define SBCAN1BA 0x80
3323 sfr at 0xC4 P5 ; // Port 5, P80C552 specific
3324 // Not directly accessible Bits.
3337 sfr at 0xF8 P5 ; // Port 5 - SAB80515 & compatible microcontrollers
3351 sfr at 0xDB P6 ; // Port 6 - SAB80515 & compatible microcontrollers
3356 sfr at 0xFA P6 ; // Port 6 - SAB80517 specific
3361 sfr at 0xDB P7 ; // Port 7 - SAB80517 specific
3366 sfr at 0xDD P8 ; // Port 6 - SAB80517 specific
3369 #ifdef PCON__SMOD__x__x__x__x__x__x__x
3370 #undef PCON__SMOD__x__x__x__x__x__x__x
3372 // Not directly accessible PCON bits
3376 #ifdef PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
3377 #undef PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
3379 // Not directly accessible PCON bits
3387 #ifdef PCON__SMOD__x__x__WLE__GF1__GF0__PD__IDL
3388 #undef PCON__SMOD__x__x__WLE__GF1__GF0__PD__IDL
3389 sfr at 0x87 PCON ; // PCON, P80C552 specific
3390 // Not directly accessible Bits.
3392 #define IDLE 0x01 ; same as IDL
3400 #ifdef PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
3401 #undef PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
3403 // Not directly accessible PCON bits
3405 #define IDLE 0x01 ; same as IDL
3407 #define PDE 0x02 ; same as PD
3412 #define PCON_IDLE 0x01
3413 #define PCON_PDE 0x02
3414 #define PCON_GF0 0x04
3415 #define PCON_GF1 0x08
3416 #define PCON_IDLS 0x20
3417 #define PCON_PDS 0x40
3418 #define PCON_SMOD 0x80
3421 #ifdef PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
3422 #undef PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
3424 // Not directly accessible PCON bits
3426 #define IDLE 0x01 ; same as IDL
3436 #ifdef PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
3437 #undef PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
3439 // Not directly accessible PCON bits
3441 #define IDLE 0x01 ; same as IDL
3449 #ifdef PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
3450 #undef PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
3452 // Not directly accessible PCON bits
3454 #define IDLE 0x01 ; same as IDL
3462 #define SMOD_0 0x80 ; same as SMOD
3465 #ifdef PCON__SMOD1__SMOD0__x__POF__GF1__GF0__PD__IDL
3466 #undef PCON__SMOD1__SMOD0__x__POF__GF1__GF0__PD__IDL
3477 #ifdef PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1__DME0
3478 #undef PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1__DME0
3479 sfr at 0xC4 PMR ; // DS87C520, DS83C520
3480 // Not directly accessible bits
3490 #ifdef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEOFF__x__x
3491 #undef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEOFF__x__x
3492 sfr at 0xC4 PMR ; // DS80C390
3493 // Not directly accessible bits
3502 #ifdef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEON__DME1__DME0
3503 #undef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEON__DME1__DME0
3504 sfr at 0xC4 PMR ; // DS89C420
3505 // Not directly accessible bits
3532 sfr at 0xFC PWM0 ; // PWM register 0, P80C552 specific
3537 sfr at 0xFD PWM1 ; // PWM register 1, P80C552 specific
3542 sfr at 0xFE PWMP ; // PWM prescaler, P80C552 specific
3547 sfr at 0xCB RCAP2H ;
3552 sfr at 0xCA RCAP2L ;
3560 #ifdef ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0
3561 #undef ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0
3562 sfr at 0xC2 ROMSIZE ; // DS87C520, DS83C520
3563 // Not directly accessible bits
3569 #ifdef ROMSIZE__x__x__x__x__PRAME__RMS2__RMS1__RMS0
3570 #undef ROMSIZE__x__x__x__x__PRAME__RMS2__RMS1__RMS0
3571 sfr at 0xC2 ROMSIZE ; // DS89C420
3572 // Not directly accessible bits
3579 #ifdef ROMSIZE__HBPF__BPF__TE__MOVCX__PRAME__RMS2__RMS1__RMS0
3580 #undef ROMSIZE__HBPF__BPF__TE__MOVCX__PRAME__RMS2__RMS1__RMS0
3581 sfr at 0xC2 ROMSIZE ; // DS87C520, DS83C520
3582 // Not directly accessible bits
3595 sfr at 0xD8 RPCTL ; // Dallas DS5001 specific
3597 sbit at 0xD9 RPCON ;
3602 sbit at 0xDF RNR_FLAG ;
3605 #ifdef RTE__TP47__TP46__RP45__RP44__RP43__RP42__RP41__RP40
3606 #undef RTE__TP47__TP46__RP45__RP44__RP43__RP42__RP41__RP40
3607 sfr at 0xEF RTE ; // Reset/toggle enable, P80C552 specific
3608 // Not directly accessible Bits.
3621 sfr at 0x99 S0BUF ; // serial channel 0 buffer register SAB80517 specific
3624 #ifdef S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI
3625 #undef S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI
3626 sfr at 0x98 S0CON ; // serial channel 0 control register P80C552 specific
3628 // Already defined in SCON
3629 //sbit at 0x98 RI0 ;
3630 //sbit at 0x99 TI0 ;
3631 //sbit at 0x9A RB8 ;
3632 //sbit at 0x9B TB8 ;
3633 //sbit at 0x9C REN ;
3634 //sbit at 0x9D SM2 ;
3635 //sbit at 0x9E SM1 ;
3636 //sbit at 0x9F SM0 ;
3639 #ifdef S0CON__SM0__SM1__SM20__REN0__TB80__RB80__TI0__RI0
3640 #undef S0CON__SM0__SM1__SM20__REN0__TB80__RB80__TI0__RI0
3641 // serial channel 0 buffer register SAB80517 specific(same as stock SCON)
3655 sfr at 0xAA S0RELL ; // serial channel 0 reload register low byte SAB80517 specific
3660 sfr at 0xBA S0RELH ; // serial channel 0 reload register high byte SAB80517 specific
3663 #ifdef S1ADR__x__x__x__x__x__x__x__GC
3664 #undef S1ADR__x__x__x__x__x__x__x__GC
3665 sfr at 0xDB S1ADR ; // Serial 1 address, P80C552 specific
3666 // Not directly accessible Bits.
3672 sfr at 0x9C S1BUF ; // serial channel 1 buffer register SAB80517 specific
3675 #ifdef S1CON_AT_0X9B
3676 #undef S1CON_AT_0X9B
3677 sfr at 0x9B S1CON ; // serial channel 1 control register SAB80517 specific
3680 #ifdef S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0
3681 #undef S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0
3682 sfr at 0xD8 S1CON ; // Serial 1 control, P80C552 specific
3683 sfr at 0xD8 SICON ; // sometimes called SICON
3695 #ifdef S1DAT_AT_0XDA
3696 #undef S1DAT_AT_0XDA
3697 sfr at 0xDA S1DAT ; // Serial 1 data, P80C552 specific
3698 sfr at 0xDA SIDAT ; // sometimes called SIDAT
3701 #ifdef S1IST_AT_0XDC
3702 #undef S1IST_AT_0XDC
3709 sfr at 0x9D S1RELL ; // serial channel 1 reload register low byte SAB80517 specific
3714 sfr at 0xBB S1RELH ; // serial channel 1 reload register high byte SAB80517 specific
3717 #ifdef S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x
3718 #undef S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x
3719 sfr at 0xD9 S1STA ; // Serial 1 status, P80C552 specific
3720 // Not directly accessible Bits.
3735 // DS80C320 specific
3736 sfr at 0xA9 SADDR0 ;
3741 // DS80C320 specific
3742 sfr at 0xAA SADDR1 ;
3745 #ifdef SADEN_AT_0XB9
3746 #undef SADEN_AT_0XB9
3752 // DS80C320 & DS80C390 specific
3753 sfr at 0xB9 SADEN0 ;
3758 // DS80C320 & DS80C390 specific
3759 sfr at 0xBA SADEN1 ;
3770 // DS80C320 & DS80C390 specific
3794 sbit at 0x9A RB8_0 ;
3795 sbit at 0x9B TB8_0 ;
3796 sbit at 0x9C REN_0 ;
3797 sbit at 0x9D SM2_0 ;
3798 sbit at 0x9E SM1_0 ;
3799 sbit at 0x9F SM0_0 ;
3801 sbit at 0x9F SM0_FE_0 ;
3806 // DS80C320 - 80C390 specific
3811 sbit at 0xC2 RB8_1 ;
3812 sbit at 0xC3 TB8_1 ;
3813 sbit at 0xC4 REN_1 ;
3814 sbit at 0xC5 SM2_1 ;
3815 sbit at 0xC6 SM1_1 ;
3816 sbit at 0xC7 SM0_1 ;
3818 sbit at 0xC7 SM0_FE_1 ;
3828 sfr at 0xD5 SPCR ; // AT89S53 specific
3829 // Not directly accesible bits
3842 sfr at 0x86 SPDR ; // AT89S53 specific
3843 // Not directly accesible bits
3856 sfr at 0xAA SPSR ; // AT89S53 specific
3857 // Not directly accesible bits
3864 sfr at 0xBA SRELH ; // Baudrate generator reload high
3869 sfr at 0xAA SRELL ; // Baudrate generator reload low
3872 #ifdef STATUS__PIP__HIP__LIP__x__x__x__x__x
3873 #undef STATUS__PIP__HIP__LIP__x__x__x__x__x
3874 // DS80C320 specific
3875 sfr at 0xC5 STATUS ;
3876 // Not directly accessible Bits. DS80C320 specific
3882 #ifdef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
3883 #undef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
3884 sfr at 0xC5 STATUS ; // DS80C390 specific
3885 // Not directly accessible Bits.
3895 #ifdef STATUS__PIS2__PIS1__PIS0__x__SPTA1__SPRA1__SPTA0__SPRA0
3896 #undef STATUS__PIS2__PIS1__PIS0__x__SPTA1__SPRA1__SPTA0__SPRA0
3897 sfr at 0xC5 STATUS ; // DS89C420 specific
3898 // Not directly accessible Bits.
3908 #ifdef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
3909 #undef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
3910 sfr at 0xC5 STATUS ; // DS80C390 specific
3911 // Not directly accessible Bits.
3921 #ifdef STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
3922 #undef STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
3923 sfr at 0xC5 STATUS ; // DS87C520 & DS83520specific
3924 // Not directly accessible Bits.
3935 #ifdef STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF
3936 #undef STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF
3937 sfr at 0xDA STATUS ; // DS5001specific
3938 // Not directly accessible Bits.
3949 #ifdef STE__TG47__TG46__SP45__SP44__SP43__SP42__SP41__SP40
3950 #undef STE__TG47__TG46__SP45__SP44__SP43__SP42__SP41__SP40
3951 sfr at 0xEE STE ; // Set enable, P80C552 specific
3952 // Not directly accessible Bits.
3965 sfr at 0xB1 SYSCON ; // XRAM Controller Access Control
3967 #define SYSCON_XMAP0 0x01
3968 #define SYSCON_XMAP1 0x02
3969 #define SYSCON_RMAP 0x10
3970 #define SYSCON_EALE 0x20
3973 #ifdef T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
3974 #undef T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
3976 // Definitions for the 8052 compatible microcontrollers.
3978 sbit at 0xC8 CP_RL2 ;
3981 sbit at 0xCB EXEN2 ;
3987 sbit at 0xC8 T2CON_0 ;
3988 sbit at 0xC9 T2CON_1 ;
3989 sbit at 0xCA T2CON_2 ;
3990 sbit at 0xCB T2CON_3 ;
3991 sbit at 0xCC T2CON_4 ;
3992 sbit at 0xCD T2CON_5 ;
3993 sbit at 0xCE T2CON_6 ;
3994 sbit at 0xCF T2CON_7 ;
3997 #ifdef T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
3998 #undef T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
4000 // Definitions for the Infineon / Siemens SAB80515, SAB80515A, SAB80517
4011 sbit at 0xC8 T2CON_0 ;
4012 sbit at 0xC9 T2CON_1 ;
4013 sbit at 0xCA T2CON_2 ;
4014 sbit at 0xCB T2CON_3 ;
4015 sbit at 0xCC T2CON_4 ;
4016 sbit at 0xCD T2CON_5 ;
4017 sbit at 0xCE T2CON_6 ;
4018 sbit at 0xCF T2CON_7 ;
4021 #ifdef T2MOD__x__x__x__D13T1__D13T2__x__T2OE__DCEN
4022 #undef T2MOD__x__x__x__D13T1__D13T2__x__T2OE__DCEN
4023 // Definitions for the timer/counter 2 of the Atmel & Dallas microcontrollers
4025 // Not not directly accessible T2MOD bits
4032 #ifdef T2MOD__x__x__x__x__x__x__T2OE__DCEN
4033 #undef T2MOD__x__x__x__x__x__x__T2OE__DCEN
4034 // Definitions for the timer/counter 2 of the Atmel 89x52 microcontroller
4036 // Not not directly accessible T2MOD bits
4046 sfr at 0xFF T3 ; // Timer 3, P80C552 specific
4051 // DS500x, DS80C320 & DS80C390 specific
4102 // Not directly accessible TMOD bits
4106 #define T0_GATE 0x08
4110 #define T1_GATE 0x80
4112 #define T0_MASK 0x0F
4113 #define T1_MASK 0xF0
4116 #ifdef TM2CON__T2IS1__T2IS0__T2ER__T2B0__T2P1__T2P0__T2MS1__T2MS0
4117 #undef TM2CON__T2IS1__T2IS0__T2ER__T2B0__T2P1__T2P0__T2MS1__T2MS0
4118 sfr at 0xEA TM2CON ; // Timer 2 control, P80C552 specific
4119 // Not directly accessible Bits.
4130 #ifdef TM2IR__T20V__CMI2__CMI1__CMI0__CTI3__CTI2__CTI1__CTI0
4131 #undef TM2IR__T20V__CMI2__CMI1__CMI0__CTI3__CTI2__CTI1__CTI0
4132 sfr at 0xC8 TM2IR ; // Timer 2 int flag reg, P80C552 specific
4146 sfr at 0xED TMH2 ; // Timer high 2, P80C552 specific
4151 sfr at 0xEC TML2 ; // Timer low 2, P80C552 specific
4156 sfr at 0x96 WCON ; // AT89S53 specific
4157 // Not directly accesible bits
4168 // DS80C320 - 390, DS89C420, etc. specific
4178 sbit at 0xDF SMOD_1 ;
4181 #ifdef WDTPRG_AT_0XA7
4182 #undef WDTPRG_AT_0XA7
4184 #define WDTRPRG_S0 0x01
4185 #define WDTRPRG_S1 0x02
4186 #define WDTRPRG_S2 0x04
4191 sfr at 0x86 WDTREL ; // Watchdof Timer reload register
4194 #ifdef WDTRST_AT_0XA6
4195 #undef WDTRST_AT_0XA6
4201 sfr at 0x91 XPAGE ; // Page Address Register for Extended On-Chip Ram - Infineon / Siemens SAB80515A specific
4204 /////////////////////////
4205 /// Interrupt vectors ///
4206 /////////////////////////
4208 // Interrupt numbers: address = (number * 8) + 3
4209 #define IE0_VECTOR 0 // 0x03 external interrupt 0
4210 #define TF0_VECTOR 1 // 0x0b timer 0
4211 #define IE1_VECTOR 2 // 0x13 external interrupt 1
4212 #define TF1_VECTOR 3 // 0x1b timer 1
4213 #define SI0_VECTOR 4 // 0x23 serial port 0
4215 #ifdef MICROCONTROLLER_AT89S53
4216 #define TF2_VECTOR 5 /* 0x2B timer 2 */
4217 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
4220 #ifdef MICROCONTROLLER_AT89X52
4221 #define TF2_VECTOR 5 /* 0x2B timer 2 */
4222 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
4225 #ifdef MICROCONTROLLER_AT89X55
4226 #define TF2_VECTOR 5 /* 0x2B timer 2 */
4227 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
4230 #ifdef MICROCONTROLLER_DS5000
4231 #define PFW_VECTOR 5 /* 0x2B */
4234 #ifdef MICROCONTROLLER_DS5001
4235 #define PFW_VECTOR 5 /* 0x2B */
4238 #ifdef MICROCONTROLLER_DS80C32X
4239 #define TF2_VECTOR 5 /* 0x2B */
4240 #define PFI_VECTOR 6 /* 0x33 */
4241 #define SIO1_VECTOR 7 /* 0x3B */
4242 #define IE2_VECTOR 8 /* 0x43 */
4243 #define IE3_VECTOR 9 /* 0x4B */
4244 #define IE4_VECTOR 10 /* 0x53 */
4245 #define IE5_VECTOR 11 /* 0x5B */
4246 #define WDI_VECTOR 12 /* 0x63 */
4249 #ifdef MICROCONTROLLER_DS8XC520
4250 #define TF2_VECTOR 5 /* 0x2B */
4251 #define PFI_VECTOR 6 /* 0x33 */
4252 #define SIO1_VECTOR 7 /* 0x3B */
4253 #define IE2_VECTOR 8 /* 0x43 */
4254 #define IE3_VECTOR 9 /* 0x4B */
4255 #define IE4_VECTOR 10 /* 0x53 */
4256 #define IE5_VECTOR 11 /* 0x5B */
4257 #define WDI_VECTOR 12 /* 0x63 */
4260 #ifdef MICROCONTROLLER_P80C552
4261 #define SIO1_VECTOR 5 // 0x2B SIO1 (I2C)
4262 #define CT0_VECTOR 6 // 0x33 T2 capture 0
4263 #define CT1_VECTOR 7 // 0x3B T2 capture 1
4264 #define CT2_VECTOR 8 // 0x43 T2 capture 2
4265 #define CT3_VECTOR 9 // 0x4B T2 capture 3
4266 #define ADC_VECTOR 10 // 0x53 ADC completion
4267 #define CM0_VECTOR 11 // 0x5B T2 compare 0
4268 #define CM1_VECTOR 12 // 0x63 T2 compare 1
4269 #define CM2_VECTOR 13 // 0x6B T2 compare 2
4270 #define TF2_VECTOR 14 // 0x73 T2 overflow
4273 #ifdef MICROCONTROLLER_P89C668
4274 #define SIO1_VECTOR 5 // 0x2b SIO1 (i2c)
4275 #define PCA_VECTOR 6 // 0x33 (Programmable Counter Array)
4276 #define TF2_VECTOR 7 // 0x3B (Timer 2)
4279 #ifdef MICROCONTROLLER_SAB80515
4280 #define TF2_VECTOR 5 // 0x2B timer 2
4281 #define EX2_VECTOR 5 // 0x2B external interrupt 2
4282 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt
4283 #define IEX2_VECTOR 9 // 0x4B external interrupt 2
4284 #define IEX3_VECTOR 10 // 0x53 external interrupt 3
4285 #define IEX4_VECTOR 11 // 0x5B external interrupt 4
4286 #define IEX5_VECTOR 12 // 0x63 external interrupt 5
4287 #define IEX6_VECTOR 13 // 0x6B external interrupt 6
4290 #ifdef MICROCONTROLLER_SAB80515A
4291 #define TF2_VECTOR 5 // 0x2B timer 2
4292 #define EX2_VECTOR 5 // 0x2B external interrupt 2
4293 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt
4294 #define IEX2_VECTOR 9 // 0x4B external interrupt 2
4295 #define IEX3_VECTOR 10 // 0x53 external interrupt 3
4296 #define IEX4_VECTOR 11 // 0x5B external interrupt 4
4297 #define IEX5_VECTOR 12 // 0x63 external interrupt 5
4298 #define IEX6_VECTOR 13 // 0x6B external interrupt 6
4301 #ifdef MICROCONTROLLER_SAB80517
4302 #define TF2_VECTOR 5 // 0x2B timer 2
4303 #define EX2_VECTOR 5 // 0x2B external interrupt 2
4304 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt
4305 #define IEX2_VECTOR 9 // 0x4B external interrupt 2
4306 #define IEX3_VECTOR 10 // 0x53 external interrupt 3
4307 #define IEX4_VECTOR 11 // 0x5B external interrupt 4
4308 #define IEX5_VECTOR 12 // 0x63 external interrupt 5
4309 #define IEX6_VECTOR 13 // 0x6B external interrupt 6
4312 #define SI1_VECTOR 16 // 0x83 serial port 1
4315 #define COMPARE_VECTOR 19 // 0x9B compare
4318 #ifdef MICROCONTORLLER_T89C51RD2
4319 #define TF2_VECTOR 5 /* 0x2B timer 2 */
4320 #define PCA_VECTOR 6 /* 0x33 Programmable Counter Array interrupt */
4321 #endif /* MICROCONTORLLER_T89C51RD2 */
4323 #endif // End of the header -> #ifndef MCS51REG_H