1 /*-------------------------------------------------------------------------
2 Register Declarations for the mcs51 compatible microcontrollers
4 Written By - Bela Torok / bela.torok@kssg.ch (November 2000)
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the
8 Free Software Foundation; either version 2, or (at your option) any
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 In other words, you are welcome to use, share and improve this program.
21 You are forbidden to forbid anyone else to use, share and improve
22 what you give them. Help stamp out software-hoarding!
27 Version 1.0 Nov 2, 2000 - B. Torok / bela.torok@kssg.ch
28 Initial release, supported microcontrollers:
29 8051, 8052, Atmel AT89C1051, AT89C2051, AT89C4051,
30 Infineon / Siemens SAB80515, SAB80535, SAB80515A
32 Version 1.0.1 (Nov 3, 2000)
33 SAB80515A definitions revised by Michael Schmitt / michael.schmitt@t-online.de
35 Version 1.0.2 (Nov 6, 2000)
36 T2CON bug corrected 8052 and SABX microcontrollers have different T2CONs
37 Support for the Atmel AT89C52, AT80LV52, AT89C55, AT80LV55
38 Support for the Dallas DS80C320 and DS80C323
39 B. Torok / bela.torok@kssg.ch
41 Version 1.0.3 (Nov 7, 2000)
42 SAB80517 definitions added by Michael Schmitt / michael.schmitt@t-online.de
43 Dallas AT89S53 definitions added by B. Torok / bela.torok@kssg.ch
44 Dallas DS87C520 and DS83C520 definitions added by B. Torok / bela.torok@kssg.ch
46 Version 1.0.4 (Nov 9, 2000)
47 To simplify the identication of registers, a large number of definitios
48 were renamed. Long register names now (hopefully) clearly define the
49 function of the registers.
50 Dallas DS89C420 definitions added by B. Torok / bela.torok@kssg.ch
52 Version 1.0.5 (Dec 15, 2000)
53 Definitions added: #ifdef MCS51REG_EXTERNAL_ROM
54 #ifdef MCS51REG_EXTERNAL_RAM
55 #ifndef MCS51REG_DISABLE_WARNINGS
58 Version 1.0.6 (March 10, 2001)
59 Support for the Dallas DS5000 & DS2250
60 Support for the Dallas DS5001 & DS2251
61 Support for the Dallas DS80C390
62 microcontrollers - B. Torok / bela.torok@kssg.ch
64 Version 1.0.7 (June 7, 2001)
65 #ifndef MCS51REG_DISABLE_WARNINGS removed
66 #ifdef MCS51REG_DISABLE_WARNINGS added - B. Torok / bela.torok@kssg.ch
67 Support for the Philips P80C552 added - Bernhard Held / Bernhard.Held@otelo-online.de
70 Adding support for additional microcontrollers:
71 -----------------------------------------------
73 1. Don't modify this file!!!
75 2. Insert your code in a separate file e.g.: mcs51reg_update.h and include
76 this after the #define HEADER_MCS51REG statement in this file
78 3. The mcs51reg_update.h file should contain following definitions:
80 a. An entry with the inventory of the register set of the
81 microcontroller in the "Describe microcontrollers" section.
83 b. If necessary add entry(s) in for registers not defined in this file
85 c. Define interrupt vectors
87 4. Send me the file mcs51reg_update.h ( bela.torok@kssg.ch ).
88 I'm going to verify/merge new definitions to this file.
91 Microcontroller support:
93 Use one of the following options:
95 1. use #include <mcs51reg.h> in your program & define MICROCONTROLLER_XXXX in your makefile.
97 2. use following definitions prior the
98 #include <mcs51reg.h> line in your program:
100 #define MICROCONTROLLER_8052 -> 8052 type microcontroller
102 #define MICROCONTROLLER_AT89CX051 -> Atmel AT89C1051, AT89C2051 and AT89C4051 microcontrollers
105 Use only one of the following definitions!!!
107 Supported Microcontrollers:
110 MICROCONTROLLER_8051 8051
111 MICROCONTROLLER_8052 8052
112 MICROCONTROLLER_AT89CX051 Atmel AT89C1051, AT89C2051 and AT89C4051
113 MICROCONTROLLER_AT89S53 Atmel AT89S53 microcontroller
114 MICROCONTROLLER_AT89X52 Atmel AT89C52 and AT80LV52 microcontrollers
115 MICROCONTROLLER_AT89X55 Atmel AT89C55 and AT80LV55 microcontrollers
116 MICROCONTROLLER_DS5000 Dallas DS5000 & DS2250 microcontroller
117 MICROCONTROLLER_DS5001 Dallas DS5001 & DS2251 microcontroller
118 MICROCONTROLLER_DS80C32X Dallas DS80C320 and DS80C323 microcontrollers
119 MICROCONTROLLER_DS80C390 Dallas DS80C390 microcontroller
120 MICROCONTROLLER_DS89C420 Dallas DS89C420 microcontroller
121 MICROCONTROLLER_DS8XC520 Dallas DS87C520 and DS83C520 microcontrollers
122 MICROCONTROLLER_SAB80515 Infineon / Siemens SAB80515 & SAB80535
123 MICROCONTROLLER_SAB80515A Infineon / Siemens SAB80515A
124 MICROCONTROLLER_SAB80517 Infineon / Siemens SAB80517
126 Additional definitions (use them prior the #include mcs51reg.h statement):
128 Ports P0 & P2 are not available for the programmer if external ROM used.
129 Use statement "#define MCS51REG_EXTERNAL_RAM" to undefine P0 & P2.
131 Ports P0, P2, P3_6, WR, P3_7 & RD are not available for the programmer if
132 external RAM is used.
133 Use statement "#define MCS51REG_EXTERNAL_RAM" to undefine P0, P2,
136 #define MCS51REG_ENABLE_WARNINGS -> enable warnings
138 -----------------------------------------------------------------------*/
141 #ifndef HEADER_MCS51REG
142 #define HEADER_MCS51REG
144 ///////////////////////////////////////////////////////
145 /// Insert header here (for developers only) ///
146 /// remove "//" from the begining of the next line ///
147 /// #include "mcs51reg_update.h" ///
148 ///////////////////////////////////////////////////////
150 //////////////////////////////////
151 /// Describe microcontrollers ///
152 /// (inventory of registers) ///
153 //////////////////////////////////
155 // definitions for the 8051
156 #ifdef MICROCONTROLLER_8051
157 #ifdef MICROCONTROLLER_DEFINED
158 #define MCS51REG_ERROR
160 #ifndef MICROCONTROLLER_DEFINED
161 #define MICROCONTROLLER_DEFINED
163 #ifdef MCS51REG_ENABLE_WARNINGS
164 #warning Selected HW: 8051
170 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
181 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
183 #define IP__x__x__x__PS__PT1__PX1__PT0__PX0
188 // end of definitions for the 8051
191 // definitions for the 8052 microcontroller
192 #ifdef MICROCONTROLLER_8052
193 #ifdef MICROCONTROLLER_DEFINED
194 #define MCS51REG_ERROR
196 #ifndef MICROCONTROLLER_DEFINED
197 #define MICROCONTROLLER_DEFINED
199 #ifdef MCS51REG_ENABLE_WARNINGS
200 #warning Selected HW: 8052
207 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
218 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
220 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
224 // 8052 specific registers
225 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
231 // end of definitions for the 8052 microcontroller
234 // definitionsons for the Atmel
235 // AT89C1051, AT89C2051 and AT89C4051 microcontrollers
236 #ifdef MICROCONTROLLER_AT89CX051
237 #ifdef MICROCONTROLLER_DEFINED
238 #define MCS51REG_ERROR
240 #ifndef MICROCONTROLLER_DEFINED
241 #define MICROCONTROLLER_DEFINED
243 #ifdef MCS51REG_ENABLE_WARNINGS
244 #warning Selected HW: Atmel AT89Cx051
246 // 8051 register set without P0 & P2
250 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
260 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
262 #define IP__x__x__x__PS__PT1__PX1__PT0__PX0
267 // end of definitionsons for the Atmel
268 // AT89C1051, AT89C2051 and AT89C4051 microcontrollers
271 // definitions for the Atmel AT89S53
272 #ifdef MICROCONTROLLER_AT89S53
273 #ifdef MICROCONTROLLER_DEFINED
274 #define MCS51REG_ERROR
276 #ifndef MICROCONTROLLER_DEFINED
277 #define MICROCONTROLLER_DEFINED
279 #ifdef MCS51REG_ENABLE_WARNINGS
280 #warning Selected HW: AT89S53
287 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
298 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
300 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
304 // 8052 specific registers
305 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
310 // AT89S53 specific register
311 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
312 #define P1_EXT__x__x__x__x__x__x__T2EX__T2
320 // end of definitions for the Atmel AT89S53 microcontroller
323 // definitions for the Atmel AT89C52 and AT89LV52 microcontrollers
324 #ifdef MICROCONTROLLER_AT89X52
325 #ifdef MICROCONTROLLER_DEFINED
326 #define MCS51REG_ERROR
328 #ifndef MICROCONTROLLER_DEFINED
329 #define MICROCONTROLLER_DEFINED
331 #ifdef MCS51REG_ENABLE_WARNINGS
332 #warning Selected HW: AT89C52 or AT89LV52
339 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
350 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
352 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
356 // 8052 specific registers
357 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
362 // AT89X55 specific register
363 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
364 #define P1_EXT__x__x__x__x__x__x__T2EX__T2
366 // end of definitions for the Atmel AT89C52 and AT89LV52 microcontrollers
369 // definitions for the Atmel AT89C55 and AT89LV55 microcontrollers
370 #ifdef MICROCONTROLLER_AT89X55
371 #ifdef MICROCONTROLLER_DEFINED
372 #define MCS51REG_ERROR
374 #ifndef MICROCONTROLLER_DEFINED
375 #define MICROCONTROLLER_DEFINED
377 #ifdef MCS51REG_ENABLE_WARNINGS
378 #warning Selected HW: AT89C55 or AT89LV55
385 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
396 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
398 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
402 // 8052 specific registers
403 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
408 // AT89X55 specific register
409 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
410 #define P1_EXT__x__x__x__x__x__x__T2EX__T2
412 // end of definitions for the Atmel AT89C55 and AT89LV55 microcontrollers
415 // definitions for the Dallas DS5000
416 #ifdef MICROCONTROLLER_DS5000
417 #ifdef MICROCONTROLLER_DEFINED
418 #define MCS51REG_ERROR
420 #ifndef MICROCONTROLLER_DEFINED
421 #define MICROCONTROLLER_DEFINED
423 #ifdef MCS51REG_ENABLE_WARNINGS
424 #warning Selected HW: DS5000
430 #define PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
441 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
443 #define IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
444 #define MCON__SL__PAA__ECE2__RA32_8__PA0__PA1__PA2__PA3
450 // end of definitions for the Dallas DS5000
453 // definitions for the Dallas DS5001
454 #ifdef MICROCONTROLLER_DS5001
455 #ifdef MICROCONTROLLER_DEFINED
456 #define MCS51REG_ERROR
458 #ifndef MICROCONTROLLER_DEFINED
459 #define MICROCONTROLLER_DEFINED
461 #ifdef MCS51REG_ENABLE_WARNINGS
462 #warning Selected HW: DS5001
468 #define PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
479 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
481 #define IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
485 #define MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL
490 #define STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF
494 // end of definitions for the Dallas DS5001
497 // definitions for the Dallas DS80C320 and DS80C323 microcontrollers
498 #ifdef MICROCONTROLLER_DS80C32X
499 #ifdef MICROCONTROLLER_DEFINED
500 #define MCS51REG_ERROR
502 #ifndef MICROCONTROLLER_DEFINED
503 #define MICROCONTROLLER_DEFINED
505 #ifdef MCS51REG_ENABLE_WARNINGS
506 #warning Selected HW: Dallas DS80C320 or DS80C323
513 #define PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
525 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
527 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
531 // 8052 specific registers
532 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
537 // DS80C320 specific register
540 #define DPS__x__x__x__x__x__x__x__SEL
542 #define EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
549 #define STATUS__PIP__HIP__LIP__x__x__x__x__x
551 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
552 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
554 #define EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
555 #define EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
557 // end of definitions for the Dallas DS80C320 and DS80C323 microcontrollers
560 // definitions for the Dallas DS80C390
561 #ifdef MICROCONTROLLER_DS80C390
562 #ifdef MICROCONTROLLER_DEFINED
563 #define MCS51REG_ERROR
565 #ifndef MICROCONTROLLER_DEFINED
566 #define MICROCONTROLLER_DEFINED
568 #ifdef MCS51REG_ENABLE_WARNINGS
569 #warning Selected HW: Dallas DS80C390
576 #define PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
588 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
590 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
594 // 8052 specific registers
595 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
600 // DS80C390 specific register
604 #define DPS__ID1__ID0__TSL__x__x__x__x__SEL
606 #define EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
614 #define ACON__x__x__x__x__x__SA__AM1__AM0
645 #define PMR__CD1__CD0__SWB__CTM__4X_2X__ALEOFF__x__x
646 #define STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
647 #define MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0
649 #define T2MOD__x__x__x__D13T1__D13T2__x__T2OE__DCEN
666 #define EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2
677 #define EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
684 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
686 // end of definitions for the Dallas DS80C390
689 // definitions for the Dallas DS89C420 microcontroller
690 #ifdef MICROCONTROLLER_DS89C420
691 #ifdef MICROCONTROLLER_DEFINED
692 #define MCS51REG_ERROR
694 #ifndef MICROCONTROLLER_DEFINED
695 #define MICROCONTROLLER_DEFINED
697 #ifdef MCS51REG_ENABLE_WARNINGS
698 #warning Selected HW: Dallas DS89C420
705 #define PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
717 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
719 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
723 // 8052 specific registers
724 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
729 // DS8XC420 specific registers
730 #define ACON__PAGEE__PAGES__PAGE0__x__x__x__x__x
733 #define DPS__ID1__ID0__TSL__AID__x__x__x__SEL
736 #define IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
737 #define IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
738 #define EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
739 #define PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1_DME0
746 #define STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
749 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
750 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
752 #define ROMSIZE__HBPF__BPF__TE__MOVCX__PRAME__RMS2__RMS1__RMS0
754 #define EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
755 #define EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
757 // end of definitions for the Dallas DS89C420 microcontroller
760 // definitions for the Dallas DS87C520 and DS83C520 microcontrollers
761 #ifdef MICROCONTROLLER_DS8XC520
762 #ifdef MICROCONTROLLER_DEFINED
763 #define MCS51REG_ERROR
765 #ifndef MICROCONTROLLER_DEFINED
766 #define MICROCONTROLLER_DEFINED
768 #ifdef MCS51REG_ENABLE_WARNINGS
769 #warning Selected HW: Dallas DS87C520 or DS85C520
776 #define PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
788 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
790 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
794 // 8052 specific registers
795 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
800 // DS8XC520 specific registers
803 #define DPS__x__x__x__x__x__x__x__SEL
805 #define EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
806 #define PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1_DME0
813 #define STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
815 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
816 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
818 #define ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0
821 #define EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
822 #define EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
824 // end of definitions for the Dallas DS87C520 and DS83C520 microcontrollers
827 // definitions for the Philips P80C552 microcontroller
828 #ifdef MICROCONTROLLER_P80C552
829 #ifdef MICROCONTROLLER_DEFINED
830 #define MCS51REG_ERROR
832 #ifndef MICROCONTROLLER_DEFINED
833 #define MICROCONTROLLER_DEFINED
835 #ifdef MCS51REG_ENABLE_WARNINGS
836 #warning Selected HW: Philips P80C552
843 #define PCON__SMOD__x__x__WLE__GF1__GF0__PD__IDL
854 #define IE__EA__EAD__ES1__ES0__ET1__EX1__ET0__EX0
856 #define IP__x__PAD__PS1__PS0__PT1__PX1__PT0__PX0
860 // P80C552 specific register-names
861 #define S0BUF // same as SBUF, set in mcs51reg.h
862 #define S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI
863 // P80C552 specific registers
865 #define ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0
866 #define CTCON__CTN3__CTP3__CTN2__CTP2__CTN1__CTP1__CTN0__CTP0
881 #define IEN1__ET2__ECM2__ECM1__ECM0__ECT3__ECT2__ECT1__ECT0
882 #define IP1__PT2__PCM2__PCM1__PCM0__PCT3__PCT2__PCT1__PCT0
886 #define P1_EXT__SDA__SCL__RT2__T2__CT3I__CT2I__CT1I__CT0I
889 #define RTE__TP47__TP46__RP45__RP44__RP43__RP42__RP41__RP40
890 #define S1ADR__x__x__x__x__x__x__x__GC
891 #define S1DAT_AT_0XDA
892 #define S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x
893 #define S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0
894 #define STE__TG47__TG46__SP45__SP44__SP43__SP42__SP41__SP40
897 #define TM2CON__T2IS1__T2IS0__T2ER__T2B0__T2P1__T2P0__T2MS1__T2MS0
898 #define TM2IR__T20V__CMI2__CMI1__CMI0__CTI3__CTI2__CTI1__CTI0
901 // end of definitions for the Philips P80C552 microcontroller
904 // definitions for the Infineon / Siemens SAB80515 & SAB80535
905 #ifdef MICROCONTROLLER_SAB80515
906 #ifdef MICROCONTROLLER_DEFINED
907 #define MCS51REG_ERROR
909 #ifndef MICROCONTROLLER_DEFINED
910 #define MICROCONTROLLER_DEFINED
912 #ifdef MCS51REG_ENABLE_WARNINGS
913 #warning Selected HW: Infineon / Siemens SAB80515 & SAB80535
915 // 8051 register set without IP
920 #define PCON__SMOD__x__x__x__x__x__x__x
931 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
936 // SAB80515 specific registers
937 #define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
938 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
939 #define IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
948 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
955 #define DAPR__SAB80515
959 // end of definitions for the Infineon / Siemens SAB80515
962 // definitions for the Infineon / Siemens SAB80515A
963 #ifdef MICROCONTROLLER_SAB80515A
964 #ifdef MICROCONTROLLER_DEFINED
965 #define MCS51REG_ERROR
967 #ifndef MICROCONTROLLER_DEFINED
968 #define MICROCONTROLLER_DEFINED
970 #ifdef MCS51REG_ENABLE_WARNINGS
971 #warning Selected HW: Infineon / Siemens SAB80515A
973 // 8051 register set without IP
978 #define PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
989 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
994 // SAB80515A specific registers
995 #define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
996 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
997 #define IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
998 #define IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
1007 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
1024 // end of definitions for the Infineon / Siemens SAB80515A
1027 // definitions for the Infineon / Siemens SAB80517
1028 #ifdef MICROCONTROLLER_SAB80517
1029 #ifdef MICROCONTROLLER_DEFINED
1030 #define MCS51REG_ERROR
1032 #ifndef MICROCONTROLLER_DEFINED
1033 #define MICROCONTROLLER_DEFINED
1035 #ifdef MCS51REG_ENABLE_WARNINGS
1036 #warning Selected HW: Infineon / Siemens SAB80517
1038 // 8051 register set without IP, SCON & SBUF
1043 #define PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
1054 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
1059 // SAB80517 specific registers
1060 #define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
1061 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
1062 #define IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
1063 #define IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
1064 #define IEN2__SAB80517
1094 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
1097 #define CTCOM_AT_0XE1
1105 #define DAPR__SAB80517
1120 #define S0CON__SM0__SM1__SM20__REN0__TB80__RB80__TI0__RI0
1124 #define S1CON_AT_0X9B
1131 // end of definitions for the Infineon / Siemens SAB80517
1134 /////////////////////////////////////////////////////////
1135 /// don't specify microcontrollers below this line! ///
1136 /////////////////////////////////////////////////////////
1139 // default microcontroller -> 8051
1140 // use default if no microcontroller specified
1141 #ifndef MICROCONTROLLER_DEFINED
1142 #define MICROCONTROLLER_DEFINED
1143 #ifdef MCS51REG_ENABLE_WARNINGS
1144 #warning No microcontroller defined!
1145 #warning Code generated for the 8051
1147 // 8051 register set
1152 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
1163 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
1165 #define IP__x__x__x__PS__PT1__PX1__PT0__PX0
1170 // end of definitions for the default microcontroller
1173 #ifdef MCS51REG_ERROR
1174 #error Two or more microcontrollers defined!
1177 #ifdef MCS51REG_EXTERNAL_ROM
1178 #ifndef MCS51REG_UNDEFINE_P0
1179 #define MCS51REG_UNDEFINE_P0
1181 #ifndef MCS51REG_UNDEFINE_P2
1182 #define MCS51REG_UNDEFINE_P2
1186 #ifdef MCS51REG_EXTERNAL_RAM
1187 #ifndef MCS51REG_UNDEFINE_P0
1188 #define MCS51REG_UNDEFINE_P0
1190 #ifndef MCS51REG_UNDEFINE_P2
1191 #define MCS51REG_UNDEFINE_P2
1195 #ifdef MCS51REG_UNDEFINE_P0
1199 #ifdef MCS51REG_UNDEFINE_P2
1203 ////////////////////////////////
1204 /// Register definitions ///
1205 /// (In alphabetical order) ///
1206 ////////////////////////////////
1213 #ifdef ACON__PAGEE__PAGES__PAGE0__x__x__x__x__x
1214 #undef ACON__PAGEE__PAGES__PAGE0__x__x__x__x__x
1215 sfr at 0x9D ACON ; // DS89C420 specific
1216 // Not directly accessible bits
1222 #ifdef ACON__x__x__x__x__x__SA__AM1__AM0
1223 #undef ACON__x__x__x__x__x__SA__AM1__AM0
1224 sfr at 0x9D ACON ; // DS89C390 specific
1225 // Not directly accessible bits
1233 sfr at 0xC6 ADCH ; // A/D converter high
1238 sfr at 0xD8 ADCON ; // A/D-converter control register SAB80515 specific
1249 // ADCON0 ... Infineon / Siemens also called this register ADCON in the User Manual
1252 sfr at 0xD8 ADCON0 ; // A/D-converter control register 0 SAB80515A &
1253 // Bit registers // SAB80517 specific
1262 // Not directly accessible ADCON0
1263 #define ADCON0_MX0 0x01
1264 #define ADCON0_MX1 0x02
1265 #define ADCON0_MX2 0x04
1266 #define ADCON0_ADM 0x08
1267 #define ADCON0_BSY 0x10
1268 #define ADCON0_ADEX 0x20
1269 #define ADCON0_CLK 0x40
1270 #define ADCON0_BD 0x80
1275 sfr at 0xDC ADCON1 ; // A/D-converter control register 1 SAB80515A & SAB80517 specific
1276 // Not directly accessible ADCON1
1277 #define ADCON1_MX0 0x01
1278 #define ADCON1_MX1 0x02
1279 #define ADCON1_MX2 0x04
1280 #define ADCON1_ADCL 0x80
1283 #ifdef ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0
1284 #undef ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0
1285 sfr at 0xC5 ADCON ; // A/D control, P80C552 specific
1286 // Not directly accessible Bits.
1293 #define ADC_0 0x40 // different name as ADC0 in P5
1294 #define ADC_1 0x80 // different name as ADC1 in P5
1299 sfr at 0xD9 ADDAT ; // A/D-converter data register SAB80515 specific
1304 sfr at 0xD9 ADDATH ; // A/D data high byte SAB80515A specific
1309 sfr at 0xDA ADDATL ; // A/D data low byte SAB80515A specific
1314 sfr at 0xEF ARCON ; // arithmetic control register SAB80517
1319 sfr at 0x9C AP ; // DS80C390
1326 sbit at 0xF0 BREG_F0 ;
1327 sbit at 0xF1 BREG_F1 ;
1328 sbit at 0xF2 BREG_F2 ;
1329 sbit at 0xF3 BREG_F3 ;
1330 sbit at 0xF4 BREG_F4 ;
1331 sbit at 0xF5 BREG_F5 ;
1332 sbit at 0xF6 BREG_F6 ;
1333 sbit at 0xF7 BREG_F7 ;
1339 // Not directly accessible bits
1350 sfr at 0xA3 C0C ; // DS80C390 specific
1351 // Not directly accessible bits
1364 sfr at 0xA5 C0IR ; // DS80C390 specific
1365 // Not directly accessible bits
1378 sfr at 0xAB C0M1C ; // DS80C390 specific
1379 // Not directly accessible bits
1381 #define ROW_TIH 0x02
1392 sfr at 0xAC C0M2C ; // DS80C390 specific
1397 sfr at 0xAD C0M3C ; // DS80C390 specific
1402 sfr at 0xAE C0M4C ; // DS80C390 specific
1407 sfr at 0xAF C0M5C ; // DS80C390 specific
1412 sfr at 0xB3 C0M6C ; // DS80C390 specific
1417 sfr at 0xB4 C0M7C ; // DS80C390 specific
1422 sfr at 0xB5 C0M8C ; // DS80C390 specific
1427 sfr at 0xB6 C0M9C ; // DS80C390 specific
1432 sfr at 0xB7 C0M10C ; // DS80C390 specific
1437 sfr at 0xBB C0M11C ; // DS80C390 specific
1442 sfr at 0xBC C0M12C ; // DS80C390 specific
1447 sfr at 0xBD C0M13C ; // DS80C390 specific
1452 sfr at 0xBE C0M14C ; // DS80C390 specific
1457 sfr at 0xBF C0M15C ; // DS80C390 specific
1462 sfr at 0xA7 C0RE ; // DS80C390 specific
1467 sfr at 0x96 C0RMS0 ; // DS80C390 specific
1472 sfr at 0x97 C0RMS1 ; // DS80C390 specific
1477 sfr at 0xA4 C0S ; // DS80C390 specific
1478 // Not directly accessible bits
1485 #define EC96_128 0x40
1491 sfr at 0xA6 C0TE ; // DS80C390 specific
1496 sfr at 0x9E C0TMA0 ; // DS80C390 specific
1501 sfr at 0x9F C0TMA1 ; // DS80C390 specific
1506 sfr at 0xE3 C1C ; // DS80C390 specific
1507 // Not directly accessible bits
1520 sfr at 0xE5 C1IR ; // DS80C390 specific
1521 // Not directly accessible bits
1534 sfr at 0xE7 C1RE ; // DS80C390 specific
1539 sfr at 0xEB C1M1C ; // DS80C390 specific
1544 sfr at 0xEC C1M2C ; // DS80C390 specific
1549 sfr at 0xED C1M3C ; // DS80C390 specific
1554 sfr at 0xEE C1M4C ; // DS80C390 specific
1559 sfr at 0xEF C1M5C ; // DS80C390 specific
1564 sfr at 0xF3 C1M6C ; // DS80C390 specific
1569 sfr at 0xF4 C1M7C ; // DS80C390 specific
1574 sfr at 0xF5 C1M8C ; // DS80C390 specific
1579 sfr at 0xF6 C1M9C ; // DS80C390 specific
1584 sfr at 0xF7 C1M10C ; // DS80C390 specific
1589 sfr at 0xFB C1M11C ; // DS80C390 specific
1594 sfr at 0xFC C1M12C ; // DS80C390 specific
1599 sfr at 0xFD C1M13C ; // DS80C390 specific
1604 sfr at 0xFE C1M14C ; // DS80C390 specific
1609 sfr at 0xFF C1M15C ; // DS80C390 specific
1614 sfr at 0xE4 C1S ; // DS80C390 specific
1615 // Not directly accessible bits
1628 sfr at 0xE6 C1TE ; // DS80C390 specific
1633 sfr at 0xD6 C1RSM0 ; // DS80C390 specific
1638 sfr at 0xD7 C1RSM1 ; // DS80C390 specific
1643 sfr at 0xDE C1TMA0 ; // DS80C390 specific
1648 sfr at 0xDF C1TMA1 ; // DS80C390 specific
1653 sfr at 0xC9 CC4EN ; // compare/capture 4 enable register SAB80517 specific
1658 sfr at 0xC1 CCEN ; // compare/capture enable register SAB80515 specific
1663 sfr at 0xC3 CCH1 ; // compare/capture register 1, high byte SAB80515 specific
1668 sfr at 0xC5 CCH2 ; // compare/capture register 2, high byte SAB80515 specific
1673 sfr at 0xC7 CCH3 ; // compare/capture register 3, high byte SAB80515 specific
1678 sfr at 0xCF CCH4 ; // compare/capture register 4, high byte SAB80515 specific
1683 sfr at 0xC2 CCL1 ; // compare/capture register 1, low byte SAB80515 specific
1688 sfr at 0xC4 CCL2 ; // compare/capture register 2, low byte SAB80515 specific
1693 sfr at 0xC6 CCL3 ; // compare/capture register 3, low byte SAB80515 specific
1698 sfr at 0xCE CCL4 ; // compare/capture register 4, low byte SAB80515 specific
1703 sfr at 0x8E CKCON ; // DS80C320 & DS80C390 specific
1704 // Not directly accessible Bits.
1717 sfr at 0x96 CKMOD ; // DS89C420 specific
1718 // Not directly accessible Bits.
1726 sfr at 0xF6 CMEN ; // compare enable register SAB80517 specific
1731 sfr at 0xD3 CMH0 ; // compare register 0 high byte SAB80517 specific
1736 sfr at 0xD5 CMH1 ; // compare register 1 high byte SAB80517 specific
1741 sfr at 0xD7 CMH2 ; // compare register 2 high byte SAB80517 specific
1746 sfr at 0xE3 CMH3 ; // compare register 3 high byte SAB80517 specific
1751 sfr at 0xE5 CMH4 ; // compare register 4 high byte SAB80517 specific
1756 sfr at 0xE7 CMH5 ; // compare register 5 high byte SAB80517 specific
1761 sfr at 0xF3 CMH6 ; // compare register 6 high byte SAB80517 specific
1766 sfr at 0xF5 CMH7 ; // compare register 7 high byte SAB80517 specific
1771 sfr at 0xC9 CMH0 ; // Compare high 0, P80C552 specific
1776 sfr at 0xCA CMH1 ; // Compare high 1, P80C552 specific
1781 sfr at 0xCB CMH2 ; // Compare high 2, P80C552 specific
1786 sfr at 0xD2 CML0 ; // compare register 0 low byte SAB80517 specific
1791 sfr at 0xD4 CML1 ; // compare register 1 low byte SAB80517 specific
1796 sfr at 0xD6 CML2 ; // compare register 2 low byte SAB80517 specific
1801 sfr at 0xE2 CML3 ; // compare register 3 low byte SAB80517 specific
1806 sfr at 0xE4 CML4 ; // compare register 4 low byte SAB80517 specific
1811 sfr at 0xE6 CML5 ; // compare register 5 low byte SAB80517 specific
1816 sfr at 0xF2 CML6 ; // compare register 6 low byte SAB80517 specific
1821 sfr at 0xF4 CML7 ; // compare register 7 low byte SAB80517 specific
1826 sfr at 0xA9 CML0 ; // Compare low 0, P80C552 specific
1831 sfr at 0xAA CML1 ; // Compare low 1, P80C552 specific
1836 sfr at 0xAB CML2 ; // Compare low 2, P80C552 specific
1841 sfr at 0xF7 CMSEL ; // compare input select SAB80517
1846 sfr at 0xCE COR ; // Dallas DS80C390 specific
1859 sfr at 0xC1 CRC ; // Dallas DS5001 specific
1870 sfr at 0xCB CRCH ; // compare/reload/capture register, high byte SAB80515 specific
1875 sfr at 0xC3 CRCHIGH ; // DS5001 specific
1880 sfr at 0xCA CRCL ; // compare/reload/capture register, low byte SAB80515 specific
1885 sfr at 0xC2 CRCLOW ; // DS5001 specific
1888 #ifdef CTCOM_AT_0XE1
1889 #undef CTCOM_AT_0XE1
1890 sfr at 0xE1 CTCON ; // com.timer control register SAB80517
1893 #ifdef CTCON__CTN3__CTP3__CTN2__CTP2__CTN1__CTP1__CTN0__CTP0
1894 #undef CTCON__CTN3__CTP3__CTN2__CTP2__CTN1__CTP1__CTN0__CTP0
1895 sfr at 0xEB CTCON ; // Capture control, P80C552 specific
1896 // Not directly accessible Bits.
1909 sfr at 0xCC CTH0 ; // Capture high 0, P80C552 specific
1914 sfr at 0xCD CTH1 ; // Capture high 1, P80C552 specific
1919 sfr at 0xCE CTH2 ; // Capture high 2, P80C552 specific
1924 sfr at 0xCF CTH3 ; // Capture high 3, P80C552 specific
1929 sfr at 0xAC CTL0 ; // Capture low 0, P80C552 specific
1934 sfr at 0xAD CTL1 ; // Capture low 1, P80C552 specific
1939 sfr at 0xAE CTL2 ; // Capture low 2, P80C552 specific
1944 sfr at 0xAF CTL3 ; // Capture low 3, P80C552 specific
1949 sfr at 0xDF CTRELH ; // com.timer rel register high byte SAB80517
1954 sfr at 0xDE CTRELL ; // com.timer rel register low byte SAB80517
1957 #ifdef DAPR__SAB80515
1958 #undef DAPR__SAB80515
1959 sfr at 0xD8 DAPR ; // D/A-converter program register SAB80515 specific
1962 #ifdef DAPR__SAB80517
1963 #undef DAPR__SAB80517
1964 sfr at 0xDA DAPR ; // D/A-converter program register SAB80517 specific
1970 sfr at 0x83 DP0H ; // Alternate name for AT89S53
1975 sfr at 0x85 DPH1 ; // DS80C320 specific
1976 sfr at 0x85 DP1H ; // Alternate name for AT89S53
1981 sfr at 0x82 DPL ; // Alternate name for AT89S53
1987 sfr at 0x84 DPL1 ; // DS80C320 specific
1988 sfr at 0x84 DP1L ; // Alternate name for AT89S53
1991 #ifdef DPS__x__x__x__x__x__x__x__SEL
1992 #undef DPS__x__x__x__x__x__x__x__SEL
1994 // Not directly accessible DPS Bit. DS80C320 & DPS8XC520 specific
1998 #ifdef DPS__ID1__ID0__TSL__x__x__x__x__SEL
1999 #undef DPS__ID1__ID0__TSL__x__x__x__x__SEL
2001 // Not directly accessible DPS Bit. DS89C390 specific
2008 #ifdef DPS__ID1__ID0__TSL__AID__x__x__x__SEL
2009 #undef DPS__ID1__ID0__TSL__AID__x__x__x__SEL
2011 // Not directly accessible DPS Bit. DS89C420 specific
2021 sfr at 0x92 DPSEL ; // data pointer select register SAB80517
2026 sfr at 0x93 DPX1 ; // DS80C390 specific
2031 sfr at 0x95 DPX1 ; // DS80C390 specific
2034 #ifdef EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
2035 #undef EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
2037 // Bit registers DS80C320 specific
2045 #ifdef EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2
2046 #undef EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2
2048 // Bit registers DS80C390 specific
2056 sbit at 0xEF CANBIE ;
2059 #ifdef EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
2060 #undef EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
2062 // Bit registers DS80C320 specific
2070 #ifdef EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
2071 #undef EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
2073 // Bit registers DS80C320 specific
2081 sbit at 0xFF CANBIP ;
2087 // Not directly accessible Bits DS80C390 specific
2092 #ifdef EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
2093 #undef EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
2095 // Not directly accessible EXIF Bits DS80C320 specific
2105 #ifdef EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
2106 #undef EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
2108 // Not directly accessible EXIF Bits DS87C520 specific
2119 #ifdef EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
2120 #undef EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
2122 // Not directly accessible EXIF Bits DS80C390 & DS89C420 specific
2133 #ifdef IE__EA__x__x__ES__ET1__EX1__ET0__EX0
2134 #undef IE__EA__x__x__ES__ET1__EX1__ET0__EX0
2145 #ifdef IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
2146 #undef IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
2154 sbit at 0xAD ET2 ; // Enable timer2 interrupt
2158 #ifdef IE__EA__EAD__ES1__ES0__ET1__EX1__ET0__EX0
2159 #undef IE__EA__EAD__ES1__ES0__ET1__EX1__ET0__EX0
2160 sfr at 0xA8 IE ; // same as IEN0 - Interrupt enable 0, P80C552 specific
2161 sfr at 0xA8 IEN0 ; // alternate name
2173 #ifdef IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
2174 #undef IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
2182 sbit at 0xAC ES0 ; // Alternate name
2183 sbit at 0xAD ET2 ; // Enable timer2 interrupt
2188 #ifdef IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
2189 #undef IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
2191 sfr at 0xA8 IEN0 ; // Alternate name
2192 // Bit registers for the SAB80515 and compatible IE
2199 sbit at 0xAD ET2 ; // Enable timer 2 overflow SAB80515 specific
2200 sbit at 0xAE WDT ; // watchdog timer reset - SAB80515 specific
2202 sbit at 0xAF EAL ; // EA as called by Infineon / Siemens
2205 #ifdef IEN1__ET2__ECM2__ECM1__ECM0__ECT3__ECT2__ECT1__ECT0
2206 #undef IEN1__ET2__ECM2__ECM1__ECM0__ECT3__ECT2__ECT1__ECT0
2207 sfr at 0xE8 IEN1 ; // Interrupt enable 1, P80C552 specific
2219 #ifdef IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
2220 #undef IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
2221 sfr at 0xB8 IEN1 ; // interrupt enable register - SAB80515 specific
2223 sbit at 0xB8 EADC ; // A/D converter interrupt enable
2229 sbit at 0xBE SWDT ; // watchdog timer start/reset
2230 sbit at 0xBF EXEN2 ; // timer2 external reload interrupt enable
2233 #ifdef IEN2__SAB80517
2234 #undef IEN2__SAB80517
2235 sfr at 0x9A IEN2 ; // interrupt enable register 2 SAB80517
2238 #ifdef IP__x__x__x__PS__PT1__PX1__PT0__PX0
2239 #undef IP__x__x__x__PS__PT1__PX1__PT0__PX0
2249 #ifdef IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
2250 #undef IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
2258 sbit at 0xBC PS0 ; // alternate name
2262 #ifdef IP__x__PAD__PS1__PS0__PT1__PX1__PT0__PX0
2263 #undef IP__x__PAD__PS1__PS0__PT1__PX1__PT0__PX0
2264 sfr at 0xB8 IP ; // Interrupt priority 0, P80C552 specific
2265 sfr at 0xB8 IP0 ; // alternate name
2276 #ifdef IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
2277 #undef IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
2289 #ifdef IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
2290 #undef IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
2301 #ifdef IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
2302 #undef IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
2303 sfr at 0xA9 IP0 ; // interrupt priority register SAB80515 specific
2304 // Not directly accessible IP0 bits
2314 #ifdef IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
2315 #undef IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
2316 sfr at 0xB8 IP0 ; // interrupt priority register DS89C420 specific
2317 // Not directly accessible IP0 bits
2327 #ifdef IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
2328 #undef IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
2329 sfr at 0xB9 IP1 ; // interrupt priority register SAB80515 specific
2330 // Not directly accessible IP1 bits
2339 #ifdef IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
2340 #undef IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
2341 sfr at 0xB1 IP1 ; // interrupt priority register DS89C420 specific
2342 // Not directly accessible IP0 bits
2352 #ifdef IP1__PT2__PCM2__PCM1__PCM0__PCT3__PCT2__PCT1__PCT0
2353 #undef IP1__PT2__PCM2__PCM1__PCM0__PCT3__PCT2__PCT1__PCT0
2354 sfr at 0xF8 IP1 ; // Interrupt priority 1, P80C552 specific
2368 sfr at 0xC0 IRCON ; // interrupt control register - SAB80515 specific
2370 sbit at 0xC0 IADC ; // A/D converter irq flag
2371 sbit at 0xC1 IEX2 ; // external interrupt edge detect flag
2376 sbit at 0xC6 TF2 ; // timer 2 owerflow flag
2377 sbit at 0xC7 EXF2 ; // timer2 reload flag
2382 sfr at 0xC0 IRCON0 ; // interrupt control register - SAB80515 specific
2384 sbit at 0xC0 IADC ; // A/D converter irq flag
2385 sbit at 0xC1 IEX2 ; // external interrupt edge detect flag
2390 sbit at 0xC6 TF2 ; // timer 2 owerflow flag
2391 sbit at 0xC7 EXF2 ; // timer2 reload flag
2396 sfr at 0xD1 IRCON1 ; // interrupt control register - SAB80515 specific
2401 sfr at 0xD3 MA ; // DS80C390
2406 sfr at 0xD4 MB ; // DS80C390
2411 sfr at 0xD5 MC ; // DS80C390
2416 sfr at 0xD1 MCNT0 ; // DS80C390
2429 sfr at 0xD2 MCNT1 ; // DS80C390
2435 #ifdef MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0
2436 #undef MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0
2437 sfr at 0xC6 MCON ; // DS80C390
2447 #ifdef MCON__PA3__PA2__PA1__PA0__RA32_8__ECE2__PAA__SL
2448 #undef MCON__PA3__PA2__PA1__PA0__RA32_8__ECE2__PAA__SL
2449 sfr at 0xC6 MCON ; // DS5000
2460 #ifdef MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL
2461 #undef MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL
2462 sfr at 0xC6 MCON ; // DS5001
2475 sfr at 0xE9 MD0 ; // MUL / DIV register 0 SAB80517
2480 sfr at 0xEA MD1 ; // MUL / DIV register 1 SAB80517
2485 sfr at 0xEB MD2 ; // MUL / DIV register 2 SAB80517
2490 sfr at 0xEC MD3 ; // MUL / DIV register 3 SAB80517
2495 sfr at 0xED MD4 ; // MUL / DIV register 4 SAB80517
2500 sfr at 0xEE MD5 ; // MUL / DIV register 5 SAB80517
2505 sfr at 0xEA MXAX ; // Dallas DS80C390
2536 #ifdef P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
2537 #undef P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
2538 // P1 alternate functions
2549 #ifdef P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
2550 sbit at 0x90 INT3_CC0 ; // P1 alternate functions - SAB80515 specific
2551 sbit at 0x91 INT4_CC1 ;
2552 sbit at 0x92 INT5_CC2 ;
2553 sbit at 0x93 INT6_CC3 ;
2556 sbit at 0x96 CLKOUT ;
2560 #ifdef P1_EXT__CT0I__CT1I__CT2I__CT3I__T2__RT2__SCL__SDA
2561 #undef P1_EXT__CT0I__CT1I__CT2I__CT3I__T2__RT2__SCL__SDA
2563 sbit at 0x90 CT0I ; // Port 1 alternate functions, P80C552 specific
2573 #ifdef P1_EXT__x__x__x__x__x__x__T2EX__T2
2574 #undef P1_EXT__x__x__x__x__x__x__T2EX__T2
2575 // P1 alternate functions
2604 #ifndef MCS51REG_EXTERNAL_RAM
2617 #ifndef MCS51REG_EXTERNAL_RAM
2625 sfr at 0x80 P4 ; // Port 4 - DS80C390
2639 sfr at 0xC0 P4 ; // Port 4, P80C552 specific
2641 sbit at 0xC0 CMSR0 ;
2642 sbit at 0xC1 CMSR1 ;
2643 sbit at 0xC2 CMSR2 ;
2644 sbit at 0xC3 CMSR3 ;
2645 sbit at 0xC4 CMSR4 ;
2646 sbit at 0xC5 CMSR5 ;
2653 sfr at 0xE8 P4 ; // Port 4 - SAB80515 & compatible microcontrollers
2667 sfr at 0x92 P4CNT ; // DS80C390
2668 // Not directly accessible bits
2669 #define P4CNT_0 0x01
2670 #define P4CNT_1 0x02
2671 #define P4CNT_2 0x04
2672 #define P4CNT_3 0x08
2673 #define P4CNT_4 0x10
2674 #define P4CNT_5 0x20
2680 sfr at 0xA1 P5 ; // Port 5 - DS80C390
2685 sfr at 0xA2 P5CNT ; // DS80C390
2686 // Not directly accessible bits
2687 #define P5CNT_0 0x01
2688 #define P5CNT_1 0x02
2689 #define P5CNT_2 0x04
2693 #define SBCAN0BA 0x40
2694 #define SBCAN1BA 0x80
2699 sfr at 0xC4 P5 ; // Port 5, P80C552 specific
2700 // Not directly accessible Bits.
2713 sfr at 0xF8 P5 ; // Port 5 - SAB80515 & compatible microcontrollers
2727 sfr at 0xDB P6 ; // Port 6 - SAB80515 & compatible microcontrollers
2732 sfr at 0xFA P6 ; // Port 6 - SAB80517 specific
2737 sfr at 0xDB P7 ; // Port 7 - SAB80517 specific
2742 sfr at 0xDD P8 ; // Port 6 - SAB80517 specific
2745 #ifdef PCON__SMOD__x__x__x__x__x__x__x
2746 #undef PCON__SMOD__x__x__x__x__x__x__x
2748 // Not directly accessible PCON bits
2752 #ifdef PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
2753 #undef PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
2755 // Not directly accessible PCON bits
2763 #ifdef PCON__SMOD__x__x__WLE__GF1__GF0__PD__IDL
2764 #undef PCON__SMOD__x__x__WLE__GF1__GF0__PD__IDL
2765 sfr at 0x87 PCON ; // PCON, P80C552 specific
2766 // Not directly accessible Bits.
2768 #define IDLE 0x01 ; same as IDL
2776 #ifdef PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
2777 #undef PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
2779 // Not directly accessible PCON bits
2781 #define IDLE 0x01 ; same as IDL
2783 #define PDE 0x02 ; same as PD
2788 #define PCON_IDLE 0x01
2789 #define PCON_PDE 0x02
2790 #define PCON_GF0 0x04
2791 #define PCON_GF1 0x08
2792 #define PCON_IDLS 0x20
2793 #define PCON_PDS 0x40
2794 #define PCON_SMOD 0x80
2797 #ifdef PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
2798 #undef PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
2800 // Not directly accessible PCON bits
2802 #define IDLE 0x01 ; same as IDL
2812 #ifdef PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
2813 #undef PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
2815 // Not directly accessible PCON bits
2817 #define IDLE 0x01 ; same as IDL
2825 #ifdef PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
2826 #undef PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
2828 // Not directly accessible PCON bits
2830 #define IDLE 0x01 ; same as IDL
2838 #define SMOD_0 0x80 ; same as SMOD
2841 #ifdef PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1_DME0
2842 #undef PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1_DME0
2843 sfr at 0xC4 PMR ; // DS87C520, DS83C520
2844 // Not directly accessible bits
2854 #ifdef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEOFF__x__x
2855 #undef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEOFF__x__x
2856 sfr at 0xC4 PMR ; // DS80C390
2857 // Not directly accessible bits
2882 sfr at 0xFC PWM0 ; // PWM register 0, P80C552 specific
2887 sfr at 0xFD PWM1 ; // PWM register 1, P80C552 specific
2892 sfr at 0xFE PWMP ; // PWM prescaler, P80C552 specific
2897 sfr at 0xCB RCAP2H ;
2902 sfr at 0xCA RCAP2L ;
2910 #ifdef ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0
2911 #undef ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0
2912 sfr at 0xC2 ROMSIZE ; // DS87C520, DS83C520
2913 // Not directly accessible bits
2919 #ifdef ROMSIZE__HBPF__BPF__TE__MOVCX__PRAME__RMS2__RMS1__RMS0
2920 #undef ROMSIZE__HBPF__BPF__TE__MOVCX__PRAME__RMS2__RMS1__RMS0
2921 sfr at 0xC2 ROMSIZE ; // DS87C520, DS83C520
2922 // Not directly accessible bits
2935 sfr at 0xD8 RPCTL ; // Dallas DS5001 specific
2937 sbit at 0xD9 RPCON ;
2942 sbit at 0xDF RNR_FLAG ;
2945 #ifdef RTE__TP47__TP46__RP45__RP44__RP43__RP42__RP41__RP40
2946 #undef RTE__TP47__TP46__RP45__RP44__RP43__RP42__RP41__RP40
2947 sfr at 0xEF RTE ; // Reset/toggle enable, P80C552 specific
2948 // Not directly accessible Bits.
2961 sfr at 0x99 S0BUF ; // serial channel 0 buffer register SAB80517 specific
2964 #ifdef S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI
2965 #undef S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI
2966 sfr at 0x98 S0CON ; // serial channel 0 control register P80C552 specific
2968 // Already defined in SCON
2969 //sbit at 0x98 RI0 ;
2970 //sbit at 0x99 TI0 ;
2971 //sbit at 0x9A RB8 ;
2972 //sbit at 0x9B TB8 ;
2973 //sbit at 0x9C REN ;
2974 //sbit at 0x9D SM2 ;
2975 //sbit at 0x9E SM1 ;
2976 //sbit at 0x9F SM0 ;
2981 sfr at 0xAA S0RELL ; // serial channel 0 reload register low byte SAB80517 specific
2986 sfr at 0xBA S0RELH ; // serial channel 0 reload register high byte SAB80517 specific
2989 #ifdef S1ADR__x__x__x__x__x__x__x__GC
2990 #undef S1ADR__x__x__x__x__x__x__x__GC
2991 sfr at 0xDB S1ADR ; // Serial 1 address, P80C552 specific
2992 // Not directly accessible Bits.
2998 sfr at 0x9C S1BUF ; // serial channel 1 buffer register SAB80517 specific
3001 #ifdef S1CON_AT_0X9B
3002 #undef S1CON_AT_0X9B
3003 sfr at 0x9B S1CON ; // serial channel 1 control register SAB80517 specific
3006 #ifdef S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0
3007 #undef S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0
3008 sfr at 0xD8 S1CON ; // Serial 1 control, P80C552 specific
3009 sfr at 0xD8 SICON ; // sometimes called SICON
3021 #ifdef S1DAT_AT_0XDA
3022 #undef S1DAT_AT_0XDA
3023 sfr at 0xDA S1DAT ; // Serial 1 data, P80C552 specific
3024 sfr at 0xDA SIDAT ; // sometimes called SIDAT
3029 sfr at 0x9D S1RELL ; // serial channel 1 reload register low byte SAB80517 specific
3034 sfr at 0xBB S1RELH ; // serial channel 1 reload register high byte SAB80517 specific
3037 #ifdef S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x
3038 #undef S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x
3039 sfr at 0xD9 S1STA ; // Serial 1 status, P80C552 specific
3040 // Not directly accessible Bits.
3050 // DS80C320 specific
3051 sfr at 0xA9 SADDR0 ;
3056 // DS80C320 specific
3057 sfr at 0xAA SADDR1 ;
3062 // DS80C320 & DS80C390 specific
3063 sfr at 0xB9 SADEN0 ;
3068 // DS80C320 & DS80C390 specific
3069 sfr at 0xBA SADEN1 ;
3080 // DS80C320 & DS80C390 specific
3104 sbit at 0x9A RB8_0 ;
3105 sbit at 0x9B TB8_0 ;
3106 sbit at 0x9C REN_0 ;
3107 sbit at 0x9D SM2_0 ;
3108 sbit at 0x9E SM1_0 ;
3109 sbit at 0x9F SM0_0 ;
3111 sbit at 0x9F SM0_FE_0 ;
3116 // DS80C320 - 80C390 specific
3121 sbit at 0xC2 RB8_1 ;
3122 sbit at 0xC3 TB8_1 ;
3123 sbit at 0xC4 REN_1 ;
3124 sbit at 0xC5 SM2_1 ;
3125 sbit at 0xC6 SM1_1 ;
3126 sbit at 0xC7 SM0_1 ;
3128 sbit at 0xC7 SM0_FE_1 ;
3138 sfr at 0xD5 SPCR ; // AT89S53 specific
3139 // Not directly accesible bits
3152 sfr at 0x86 SPDR ; // AT89S53 specific
3153 // Not directly accesible bits
3166 sfr at 0xAA SPSR ; // AT89S53 specific
3167 // Not directly accesible bits
3174 sfr at 0xBA SRELH ; // Baudrate generator reload high
3179 sfr at 0xAA SRELL ; // Baudrate generator reload low
3182 #ifdef STATUS__PIP__HIP__LIP__x__x__x__x__x
3183 #undef STATUS__PIP__HIP__LIP__x__x__x__x__x
3184 // DS80C320 specific
3185 sfr at 0xC5 STATUS ;
3186 // Not directly accessible Bits. DS80C320 specific
3192 #ifdef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
3193 #undef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
3194 sfr at 0xC5 STATUS ; // DS80C390 specific
3195 // Not directly accessible Bits.
3205 #ifdef STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
3206 #undef STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
3207 sfr at 0xC5 STATUS ; // DS87C520 & DS83520specific
3208 // Not directly accessible Bits.
3219 #ifdef STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF
3220 #undef STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF
3221 sfr at 0xDA STATUS ; // DS5001specific
3222 // Not directly accessible Bits.
3233 #ifdef STE__TG47__TG46__SP45__SP44__SP43__SP42__SP41__SP40
3234 #undef STE__TG47__TG46__SP45__SP44__SP43__SP42__SP41__SP40
3235 sfr at 0xEE STE ; // Set enable, P80C552 specific
3236 // Not directly accessible Bits.
3249 sfr at 0xB1 SYSCON ; // XRAM Controller Access Control
3251 #define SYSCON_XMAP0 0x01
3252 #define SYSCON_XMAP1 0x02
3253 #define SYSCON_RMAP 0x10
3254 #define SYSCON_EALE 0x20
3257 #ifdef T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
3258 #undef T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
3260 // Definitions for the 8052 compatible microcontrollers.
3262 sbit at 0xC8 CP_RL2 ;
3265 sbit at 0xCB EXEN2 ;
3271 sbit at 0xC8 T2CON_0 ;
3272 sbit at 0xC9 T2CON_1 ;
3273 sbit at 0xCA T2CON_2 ;
3274 sbit at 0xCB T2CON_3 ;
3275 sbit at 0xCC T2CON_4 ;
3276 sbit at 0xCD T2CON_5 ;
3277 sbit at 0xCE T2CON_6 ;
3278 sbit at 0xCF T2CON_7 ;
3281 #ifdef T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
3282 #undef T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
3284 // Definitions for the Infineon / Siemens SAB80515, SAB80515A, SAB80517
3295 sbit at 0xC8 T2CON_0 ;
3296 sbit at 0xC9 T2CON_1 ;
3297 sbit at 0xCA T2CON_2 ;
3298 sbit at 0xCB T2CON_3 ;
3299 sbit at 0xCC T2CON_4 ;
3300 sbit at 0xCD T2CON_5 ;
3301 sbit at 0xCE T2CON_6 ;
3302 sbit at 0xCF T2CON_7 ;
3305 #ifdef T2MOD__x__x__x__D13T1__D13T2__x__T2OE__DCEN
3306 #undef T2MOD__x__x__x__D13T1__D13T2__x__T2OE__DCEN
3307 // Definitions for the timer/counter 2 of the Atmel & Dallas microcontrollers
3309 // Not not directly accessible T2MOD bits
3316 #ifdef T2MOD__x__x__x__x__x__x__T2OE__DCEN
3317 #undef T2MOD__x__x__x__x__x__x__T2OE__DCEN
3318 // Definitions for the timer/counter 2 of the Atmel 89x52 microcontroller
3320 // Not not directly accessible T2MOD bits
3330 sfr at 0xFF T3 ; // Timer 3, P80C552 specific
3335 // DS500x, DS80C320 & DS80C390 specific
3386 // Not directly accessible TMOD bits
3390 #define T0_GATE 0x08
3394 #define T1_GATE 0x80
3396 #define T0_MASK 0x0F
3397 #define T1_MASK 0xF0
3400 #ifdef TM2CON__T2IS1__T2IS0__T2ER__T2B0__T2P1__T2P0__T2MS1__T2MS0
3401 #undef TM2CON__T2IS1__T2IS0__T2ER__T2B0__T2P1__T2P0__T2MS1__T2MS0
3402 sfr at 0xEA TM2CON ; // Timer 2 control, P80C552 specific
3403 // Not directly accessible Bits.
3414 #ifdef TM2IR__T20V__CMI2__CMI1__CMI0__CTI3__CTI2__CTI1__CTI0
3415 #undef TM2IR__T20V__CMI2__CMI1__CMI0__CTI3__CTI2__CTI1__CTI0
3416 sfr at 0xC8 TM2IR ; // Timer 2 int flag reg, P80C552 specific
3430 sfr at 0xED TMH2 ; // Timer high 2, P80C552 specific
3435 sfr at 0xEC TML2 ; // Timer low 2, P80C552 specific
3440 sfr at 0x96 WCON ; // AT89S53 specific
3441 // Not directly accesible bits
3452 // DS80C320 - 390 specific
3462 sbit at 0xDF SMOD_1 ;
3467 sfr at 0x86 WDTREL ; // Watchdof Timer reload register
3472 sfr at 0x91 XPAGE ; // Page Address Register for Extended On-Chip Ram - Infineon / Siemens SAB80515A specific
3476 /////////////////////////
3477 /// Interrupt vectors ///
3478 /////////////////////////
3480 // Interrupt numbers: address = (number * 8) + 3
3481 #define IE0_VECTOR 0 // 0x03 external interrupt 0
3482 #define TF0_VECTOR 1 // 0x0b timer 0
3483 #define IE1_VECTOR 2 // 0x13 external interrupt 1
3484 #define TF1_VECTOR 3 // 0x1b timer 1
3485 #define SI0_VECTOR 4 // 0x23 serial port 0
3487 #ifdef MICROCONTROLLER_AT89S53
3488 #define TF2_VECTOR 5 /* 0x2B timer 2 */
3489 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
3492 #ifdef MICROCONTROLLER_AT89X52
3493 #define TF2_VECTOR 5 /* 0x2B timer 2 */
3494 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
3497 #ifdef MICROCONTROLLER_AT89X55
3498 #define TF2_VECTOR 5 /* 0x2B timer 2 */
3499 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
3502 #ifdef MICROCONTROLLER_DS5000
3503 #define PFW_VECTOR 5 /* 0x2B */
3506 #ifdef MICROCONTROLLER_DS5001
3507 #define PFW_VECTOR 5 /* 0x2B */
3510 #ifdef MICROCONTROLLER_DS80C32X
3511 #define TF2_VECTOR 5 /* 0x2B */
3512 #define PFI_VECTOR 6 /* 0x33 */
3513 #define SIO1_VECTOR 7 /* 0x3B */
3514 #define IE2_VECTOR 8 /* 0x43 */
3515 #define IE3_VECTOR 9 /* 0x4B */
3516 #define IE4_VECTOR 10 /* 0x53 */
3517 #define IE5_VECTOR 11 /* 0x5B */
3518 #define WDI_VECTOR 12 /* 0x63 */
3521 #ifdef MICROCONTROLLER_DS8XC520
3522 #define TF2_VECTOR 5 /* 0x2B */
3523 #define PFI_VECTOR 6 /* 0x33 */
3524 #define SIO1_VECTOR 7 /* 0x3B */
3525 #define IE2_VECTOR 8 /* 0x43 */
3526 #define IE3_VECTOR 9 /* 0x4B */
3527 #define IE4_VECTOR 10 /* 0x53 */
3528 #define IE5_VECTOR 11 /* 0x5B */
3529 #define WDI_VECTOR 12 /* 0x63 */
3532 #ifdef MICROCONTROLLER_P80C552
3533 #define SIO1_VECTOR 5 // 0x2B SIO1 (I2C)
3534 #define CT0_VECTOR 6 // 0x33 T2 capture 0
3535 #define CT1_VECTOR 7 // 0x3B T2 capture 1
3536 #define CT2_VECTOR 8 // 0x43 T2 capture 2
3537 #define CT3_VECTOR 9 // 0x4B T2 capture 3
3538 #define ADC_VECTOR 10 // 0x53 ADC completion
3539 #define CM0_VECTOR 11 // 0x5B T2 compare 0
3540 #define CM1_VECTOR 12 // 0x63 T2 compare 1
3541 #define CM2_VECTOR 13 // 0x6B T2 compare 2
3542 #define TF2_VECTOR 14 // 0x73 T2 overflow
3545 #ifdef MICROCONTROLLER_SAB80515
3546 #define TF2_VECTOR 5 // 0x2B timer 2
3547 #define EX2_VECTOR 5 // 0x2B external interrupt 2
3548 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt
3549 #define IEX2_VECTOR 9 // 0x4B external interrupt 2
3550 #define IEX3_VECTOR 10 // 0x53 external interrupt 3
3551 #define IEX4_VECTOR 11 // 0x5B external interrupt 4
3552 #define IEX5_VECTOR 12 // 0x63 external interrupt 5
3553 #define IEX6_VECTOR 13 // 0x6B external interrupt 6
3556 #ifdef MICROCONTROLLER_SAB80515A
3557 #define TF2_VECTOR 5 // 0x2B timer 2
3558 #define EX2_VECTOR 5 // 0x2B external interrupt 2
3559 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt
3560 #define IEX2_VECTOR 9 // 0x4B external interrupt 2
3561 #define IEX3_VECTOR 10 // 0x53 external interrupt 3
3562 #define IEX4_VECTOR 11 // 0x5B external interrupt 4
3563 #define IEX5_VECTOR 12 // 0x63 external interrupt 5
3564 #define IEX6_VECTOR 13 // 0x6B external interrupt 6
3567 #ifdef MICROCONTROLLER_SAB80517
3568 #define TF2_VECTOR 5 // 0x2B timer 2
3569 #define EX2_VECTOR 5 // 0x2B external interrupt 2
3570 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt
3571 #define IEX2_VECTOR 9 // 0x4B external interrupt 2
3572 #define IEX3_VECTOR 10 // 0x53 external interrupt 3
3573 #define IEX4_VECTOR 11 // 0x5B external interrupt 4
3574 #define IEX5_VECTOR 12 // 0x63 external interrupt 5
3575 #define IEX6_VECTOR 13 // 0x6B external interrupt 6
3578 #define SI1_VECTOR 16 // 0x83 serial port 1
3581 #define COMPARE_VECTOR 19 // 0x9B compare
3584 #endif // End of the header -> #ifndef MCS51REG_H