1 /*-------------------------------------------------------------------------
2 Register Declarations for the mcs51 compatible microcontrollers
4 Written By - Bela Torok / bela.torok@kssg.ch (November 2000)
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the
8 Free Software Foundation; either version 2, or (at your option) any
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 In other words, you are welcome to use, share and improve this program.
21 You are forbidden to forbid anyone else to use, share and improve
22 what you give them. Help stamp out software-hoarding!
27 Version 1.0 Nov 2, 2000 - B. Torok / bela.torok@kssg.ch
28 Initial release, supported microcontrollers:
29 8051, 8052, Atmel AT89C1051, AT89C2051, AT89C4051,
30 Infineon / Siemens SAB80515, SAB80535, SAB80515A
32 Version 1.0.1 (Nov 3, 2000)
33 SAB80515A definitions revised by Michael Schmitt / michael.schmitt@t-online.de
35 Version 1.0.2 (Nov 6, 2000)
36 T2CON bug corrected 8052 and SABX microcontrollers have different T2CONs
37 Support for the Atmel AT89C52, AT80LV52, AT89C55, AT80LV55
38 Support for the Dallas DS80C320 and DS80C323
39 B. Torok / bela.torok@kssg.ch
41 Version 1.0.3 (Nov 7, 2000)
42 SAB80517 definitions added by Michael Schmitt / michael.schmitt@t-online.de
43 Dallas AT89S53 definitions added by B. Torok / bela.torok@kssg.ch
44 Dallas DS87C520 and DS83C520 definitions added by B. Torok / bela.torok@kssg.ch
46 Version 1.0.4 (Nov 9, 2000)
47 To simplify the identication of registers, a large number of definitios
48 were renamed. Long register names now (hopefully) clearly define the
49 function of the registers.
50 Dallas DS89C420 definitions added by B. Torok / bela.torok@kssg.ch
52 Version 1.0.5 (Dec 15, 2000)
53 Definitions added: #ifdef MCS51REG_EXTERNAL_ROM
54 #ifdef MCS51REG_EXTERNAL_RAM
55 #ifndef MCS51REG_DISABLE_WARNINGS
58 Version 1.0.6 (March 10, 2001)
59 Support for the Dallas DS5000 & DS2250
60 Support for the Dallas DS5001 & DS2251
61 Support for the Dallas DS80C390
62 microcontrollers - B. Torok / bela.torok@kssg.ch
64 Version 1.0.7 (June 7, 2001)
65 #ifndef MCS51REG_DISABLE_WARNINGS removed
66 #ifdef MCS51REG_DISABLE_WARNINGS added - B. Torok / bela.torok@kssg.ch
67 Support for the Philips P80C552 added - Bernhard Held / Bernhard.Held@otelo-online.de
70 Adding support for additional microcontrollers:
71 -----------------------------------------------
73 1. Don't modify this file!!!
75 2. Insert your code in a separate file e.g.: mcs51reg_update.h and include
76 this after the #define HEADER_MCS51REG statement in this file
78 3. The mcs51reg_update.h file should contain following definitions:
80 a. An entry with the inventory of the register set of the
81 microcontroller in the "Describe microcontrollers" section.
83 b. If necessary add entry(s) in for registers not defined in this file
85 c. Define interrupt vectors
87 4. Send me the file mcs51reg_update.h ( bela.torok@kssg.ch ).
88 I'm going to verify/merge new definitions to this file.
91 Microcontroller support:
93 Use one of the following options:
95 1. use #include <mcs51reg.h> in your program & define MICROCONTROLLER_XXXX in your makefile.
97 2. use following definitions prior the
98 #include <mcs51reg.h> line in your program:
100 #define MICROCONTROLLER_8052 -> 8052 type microcontroller
102 #define MICROCONTROLLER_AT89CX051 -> Atmel AT89C1051, AT89C2051 and AT89C4051 microcontrollers
105 Use only one of the following definitions!!!
107 Supported Microcontrollers:
110 MICROCONTROLLER_8051 8051
111 MICROCONTROLLER_8052 8052
112 MICROCONTROLLER_AT89CX051 Atmel AT89C1051, AT89C2051 and AT89C4051
113 MICROCONTROLLER_AT89S53 Atmel AT89S53 microcontroller
114 MICROCONTROLLER_AT89X52 Atmel AT89C52 and AT80LV52 microcontrollers
115 MICROCONTROLLER_AT89X55 Atmel AT89C55 and AT80LV55 microcontrollers
116 MICROCONTROLLER_DS5000 Dallas DS5000 & DS2250 microcontroller
117 MICROCONTROLLER_DS5001 Dallas DS5001 & DS2251 microcontroller
118 MICROCONTROLLER_DS80C32X Dallas DS80C320 and DS80C323 microcontrollers
119 MICROCONTROLLER_DS80C390 Dallas DS80C390 microcontroller
120 MICROCONTROLLER_DS89C420 Dallas DS89C420 microcontroller
121 MICROCONTROLLER_DS8XC520 Dallas DS87C520 and DS83C520 microcontrollers
122 MICROCONTROLLER_P80C552 Philips P80C552
123 MICROCONTROLLER_SAB80515 Infineon / Siemens SAB80515 & SAB80535
124 MICROCONTROLLER_SAB80515A Infineon / Siemens SAB80515A
125 MICROCONTROLLER_SAB80517 Infineon / Siemens SAB80517
127 Additional definitions (use them prior the #include mcs51reg.h statement):
129 Ports P0 & P2 are not available for the programmer if external ROM used.
130 Use statement "#define MCS51REG_EXTERNAL_RAM" to undefine P0 & P2.
132 Ports P0, P2, P3_6, WR, P3_7 & RD are not available for the programmer if
133 external RAM is used.
134 Use statement "#define MCS51REG_EXTERNAL_RAM" to undefine P0, P2,
137 #define MCS51REG_ENABLE_WARNINGS -> enable warnings
139 -----------------------------------------------------------------------*/
142 #ifndef HEADER_MCS51REG
143 #define HEADER_MCS51REG
145 ///////////////////////////////////////////////////////
146 /// Insert header here (for developers only) ///
147 /// remove "//" from the begining of the next line ///
148 /// #include "mcs51reg_update.h" ///
149 ///////////////////////////////////////////////////////
151 //////////////////////////////////
152 /// Describe microcontrollers ///
153 /// (inventory of registers) ///
154 //////////////////////////////////
156 // definitions for the 8051
157 #ifdef MICROCONTROLLER_8051
158 #ifdef MICROCONTROLLER_DEFINED
159 #define MCS51REG_ERROR
161 #ifndef MICROCONTROLLER_DEFINED
162 #define MICROCONTROLLER_DEFINED
164 #ifdef MCS51REG_ENABLE_WARNINGS
165 #warning Selected HW: 8051
171 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
182 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
184 #define IP__x__x__x__PS__PT1__PX1__PT0__PX0
189 // end of definitions for the 8051
192 // definitions for the 8052 microcontroller
193 #ifdef MICROCONTROLLER_8052
194 #ifdef MICROCONTROLLER_DEFINED
195 #define MCS51REG_ERROR
197 #ifndef MICROCONTROLLER_DEFINED
198 #define MICROCONTROLLER_DEFINED
200 #ifdef MCS51REG_ENABLE_WARNINGS
201 #warning Selected HW: 8052
208 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
219 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
221 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
225 // 8052 specific registers
226 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
232 // end of definitions for the 8052 microcontroller
235 // definitionsons for the Atmel
236 // AT89C1051, AT89C2051 and AT89C4051 microcontrollers
237 #ifdef MICROCONTROLLER_AT89CX051
238 #ifdef MICROCONTROLLER_DEFINED
239 #define MCS51REG_ERROR
241 #ifndef MICROCONTROLLER_DEFINED
242 #define MICROCONTROLLER_DEFINED
244 #ifdef MCS51REG_ENABLE_WARNINGS
245 #warning Selected HW: Atmel AT89Cx051
247 // 8051 register set without P0 & P2
251 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
261 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
263 #define IP__x__x__x__PS__PT1__PX1__PT0__PX0
268 // end of definitionsons for the Atmel
269 // AT89C1051, AT89C2051 and AT89C4051 microcontrollers
272 // definitions for the Atmel AT89S53
273 #ifdef MICROCONTROLLER_AT89S53
274 #ifdef MICROCONTROLLER_DEFINED
275 #define MCS51REG_ERROR
277 #ifndef MICROCONTROLLER_DEFINED
278 #define MICROCONTROLLER_DEFINED
280 #ifdef MCS51REG_ENABLE_WARNINGS
281 #warning Selected HW: AT89S53
288 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
299 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
301 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
305 // 8052 specific registers
306 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
311 // AT89S53 specific register
312 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
313 #define P1_EXT__x__x__x__x__x__x__T2EX__T2
321 // end of definitions for the Atmel AT89S53 microcontroller
324 // definitions for the Atmel AT89C52 and AT89LV52 microcontrollers
325 #ifdef MICROCONTROLLER_AT89X52
326 #ifdef MICROCONTROLLER_DEFINED
327 #define MCS51REG_ERROR
329 #ifndef MICROCONTROLLER_DEFINED
330 #define MICROCONTROLLER_DEFINED
332 #ifdef MCS51REG_ENABLE_WARNINGS
333 #warning Selected HW: AT89C52 or AT89LV52
340 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
351 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
353 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
357 // 8052 specific registers
358 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
363 // AT89X55 specific register
364 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
365 #define P1_EXT__x__x__x__x__x__x__T2EX__T2
367 // end of definitions for the Atmel AT89C52 and AT89LV52 microcontrollers
370 // definitions for the Atmel AT89C55 and AT89LV55 microcontrollers
371 #ifdef MICROCONTROLLER_AT89X55
372 #ifdef MICROCONTROLLER_DEFINED
373 #define MCS51REG_ERROR
375 #ifndef MICROCONTROLLER_DEFINED
376 #define MICROCONTROLLER_DEFINED
378 #ifdef MCS51REG_ENABLE_WARNINGS
379 #warning Selected HW: AT89C55 or AT89LV55
386 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
397 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
399 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
403 // 8052 specific registers
404 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
409 // AT89X55 specific register
410 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
411 #define P1_EXT__x__x__x__x__x__x__T2EX__T2
413 // end of definitions for the Atmel AT89C55 and AT89LV55 microcontrollers
416 // definitions for the Dallas DS5000
417 #ifdef MICROCONTROLLER_DS5000
418 #ifdef MICROCONTROLLER_DEFINED
419 #define MCS51REG_ERROR
421 #ifndef MICROCONTROLLER_DEFINED
422 #define MICROCONTROLLER_DEFINED
424 #ifdef MCS51REG_ENABLE_WARNINGS
425 #warning Selected HW: DS5000
431 #define PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
442 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
444 #define IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
445 #define MCON__SL__PAA__ECE2__RA32_8__PA0__PA1__PA2__PA3
451 // end of definitions for the Dallas DS5000
454 // definitions for the Dallas DS5001
455 #ifdef MICROCONTROLLER_DS5001
456 #ifdef MICROCONTROLLER_DEFINED
457 #define MCS51REG_ERROR
459 #ifndef MICROCONTROLLER_DEFINED
460 #define MICROCONTROLLER_DEFINED
462 #ifdef MCS51REG_ENABLE_WARNINGS
463 #warning Selected HW: DS5001
469 #define PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
480 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
482 #define IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
486 #define MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL
491 #define STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF
495 // end of definitions for the Dallas DS5001
498 // definitions for the Dallas DS80C320 and DS80C323 microcontrollers
499 #ifdef MICROCONTROLLER_DS80C32X
500 #ifdef MICROCONTROLLER_DEFINED
501 #define MCS51REG_ERROR
503 #ifndef MICROCONTROLLER_DEFINED
504 #define MICROCONTROLLER_DEFINED
506 #ifdef MCS51REG_ENABLE_WARNINGS
507 #warning Selected HW: Dallas DS80C320 or DS80C323
514 #define PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
526 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
528 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
532 // 8052 specific registers
533 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
538 // DS80C320 specific register
541 #define DPS__x__x__x__x__x__x__x__SEL
543 #define EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
550 #define STATUS__PIP__HIP__LIP__x__x__x__x__x
552 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
553 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
555 #define EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
556 #define EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
558 // end of definitions for the Dallas DS80C320 and DS80C323 microcontrollers
561 // definitions for the Dallas DS80C390
562 #ifdef MICROCONTROLLER_DS80C390
563 #ifdef MICROCONTROLLER_DEFINED
564 #define MCS51REG_ERROR
566 #ifndef MICROCONTROLLER_DEFINED
567 #define MICROCONTROLLER_DEFINED
569 #ifdef MCS51REG_ENABLE_WARNINGS
570 #warning Selected HW: Dallas DS80C390
577 #define PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
589 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
591 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
595 // 8052 specific registers
596 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
601 // DS80C390 specific register
605 #define DPS__ID1__ID0__TSL__x__x__x__x__SEL
607 #define EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
615 #define ACON__x__x__x__x__x__SA__AM1__AM0
646 #define PMR__CD1__CD0__SWB__CTM__4X_2X__ALEOFF__x__x
647 #define STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
648 #define MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0
650 #define T2MOD__x__x__x__D13T1__D13T2__x__T2OE__DCEN
667 #define EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2
678 #define EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
685 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
687 // end of definitions for the Dallas DS80C390
690 // definitions for the Dallas DS89C420 microcontroller
691 #ifdef MICROCONTROLLER_DS89C420
692 #ifdef MICROCONTROLLER_DEFINED
693 #define MCS51REG_ERROR
695 #ifndef MICROCONTROLLER_DEFINED
696 #define MICROCONTROLLER_DEFINED
698 #ifdef MCS51REG_ENABLE_WARNINGS
699 #warning Selected HW: Dallas DS89C420
706 #define PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
718 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
720 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
724 // 8052 specific registers
725 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
730 // DS8XC420 specific registers
731 #define ACON__PAGEE__PAGES__PAGE0__x__x__x__x__x
734 #define DPS__ID1__ID0__TSL__AID__x__x__x__SEL
737 #define IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
738 #define IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
739 #define EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
740 #define PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1_DME0
747 #define STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
750 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
751 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
753 #define ROMSIZE__HBPF__BPF__TE__MOVCX__PRAME__RMS2__RMS1__RMS0
755 #define EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
756 #define EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
758 // end of definitions for the Dallas DS89C420 microcontroller
761 // definitions for the Dallas DS87C520 and DS83C520 microcontrollers
762 #ifdef MICROCONTROLLER_DS8XC520
763 #ifdef MICROCONTROLLER_DEFINED
764 #define MCS51REG_ERROR
766 #ifndef MICROCONTROLLER_DEFINED
767 #define MICROCONTROLLER_DEFINED
769 #ifdef MCS51REG_ENABLE_WARNINGS
770 #warning Selected HW: Dallas DS87C520 or DS85C520
777 #define PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
789 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
791 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
795 // 8052 specific registers
796 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
801 // DS8XC520 specific registers
804 #define DPS__x__x__x__x__x__x__x__SEL
806 #define EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
807 #define PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1_DME0
814 #define STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
816 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
817 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
819 #define ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0
822 #define EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
823 #define EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
825 // end of definitions for the Dallas DS87C520 and DS83C520 microcontrollers
828 // definitions for the Philips P80C552 microcontroller
829 #ifdef MICROCONTROLLER_P80C552
830 #ifdef MICROCONTROLLER_DEFINED
831 #define MCS51REG_ERROR
833 #ifndef MICROCONTROLLER_DEFINED
834 #define MICROCONTROLLER_DEFINED
836 #ifdef MCS51REG_ENABLE_WARNINGS
837 #warning Selected HW: Philips P80C552
844 #define PCON__SMOD__x__x__WLE__GF1__GF0__PD__IDL
855 #define IE__EA__EAD__ES1__ES0__ET1__EX1__ET0__EX0
857 #define IP__x__PAD__PS1__PS0__PT1__PX1__PT0__PX0
861 // P80C552 specific register-names
862 #define S0BUF // same as SBUF, set in mcs51reg.h
863 #define S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI
864 // P80C552 specific registers
866 #define ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0
867 #define CTCON__CTN3__CTP3__CTN2__CTP2__CTN1__CTP1__CTN0__CTP0
882 #define IEN1__ET2__ECM2__ECM1__ECM0__ECT3__ECT2__ECT1__ECT0
883 #define IP1__PT2__PCM2__PCM1__PCM0__PCT3__PCT2__PCT1__PCT0
887 #define P1_EXT__SDA__SCL__RT2__T2__CT3I__CT2I__CT1I__CT0I
890 #define RTE__TP47__TP46__RP45__RP44__RP43__RP42__RP41__RP40
891 #define S1ADR__x__x__x__x__x__x__x__GC
892 #define S1DAT_AT_0XDA
893 #define S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x
894 #define S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0
895 #define STE__TG47__TG46__SP45__SP44__SP43__SP42__SP41__SP40
898 #define TM2CON__T2IS1__T2IS0__T2ER__T2B0__T2P1__T2P0__T2MS1__T2MS0
899 #define TM2IR__T20V__CMI2__CMI1__CMI0__CTI3__CTI2__CTI1__CTI0
902 // end of definitions for the Philips P80C552 microcontroller
905 // definitions for the Infineon / Siemens SAB80515 & SAB80535
906 #ifdef MICROCONTROLLER_SAB80515
907 #ifdef MICROCONTROLLER_DEFINED
908 #define MCS51REG_ERROR
910 #ifndef MICROCONTROLLER_DEFINED
911 #define MICROCONTROLLER_DEFINED
913 #ifdef MCS51REG_ENABLE_WARNINGS
914 #warning Selected HW: Infineon / Siemens SAB80515 & SAB80535
916 // 8051 register set without IP
921 #define PCON__SMOD__x__x__x__x__x__x__x
932 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
937 // SAB80515 specific registers
938 #define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
939 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
940 #define IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
949 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
956 #define DAPR__SAB80515
960 // end of definitions for the Infineon / Siemens SAB80515
963 // definitions for the Infineon / Siemens SAB80515A
964 #ifdef MICROCONTROLLER_SAB80515A
965 #ifdef MICROCONTROLLER_DEFINED
966 #define MCS51REG_ERROR
968 #ifndef MICROCONTROLLER_DEFINED
969 #define MICROCONTROLLER_DEFINED
971 #ifdef MCS51REG_ENABLE_WARNINGS
972 #warning Selected HW: Infineon / Siemens SAB80515A
974 // 8051 register set without IP
979 #define PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
990 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
995 // SAB80515A specific registers
996 #define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
997 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
998 #define IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
999 #define IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
1008 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
1025 // end of definitions for the Infineon / Siemens SAB80515A
1028 // definitions for the Infineon / Siemens SAB80517
1029 #ifdef MICROCONTROLLER_SAB80517
1030 #ifdef MICROCONTROLLER_DEFINED
1031 #define MCS51REG_ERROR
1033 #ifndef MICROCONTROLLER_DEFINED
1034 #define MICROCONTROLLER_DEFINED
1036 #ifdef MCS51REG_ENABLE_WARNINGS
1037 #warning Selected HW: Infineon / Siemens SAB80517
1039 // 8051 register set without IP, SCON & SBUF
1044 #define PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
1055 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
1060 // SAB80517 specific registers
1061 #define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
1062 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
1063 #define IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
1064 #define IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
1065 #define IEN2__SAB80517
1095 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
1098 #define CTCOM_AT_0XE1
1106 #define DAPR__SAB80517
1121 #define S0CON__SM0__SM1__SM20__REN0__TB80__RB80__TI0__RI0
1125 #define S1CON_AT_0X9B
1132 // end of definitions for the Infineon / Siemens SAB80517
1135 /////////////////////////////////////////////////////////
1136 /// don't specify microcontrollers below this line! ///
1137 /////////////////////////////////////////////////////////
1140 // default microcontroller -> 8051
1141 // use default if no microcontroller specified
1142 #ifndef MICROCONTROLLER_DEFINED
1143 #define MICROCONTROLLER_DEFINED
1144 #ifdef MCS51REG_ENABLE_WARNINGS
1145 #warning No microcontroller defined!
1146 #warning Code generated for the 8051
1148 // 8051 register set
1153 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
1164 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
1166 #define IP__x__x__x__PS__PT1__PX1__PT0__PX0
1171 // end of definitions for the default microcontroller
1174 #ifdef MCS51REG_ERROR
1175 #error Two or more microcontrollers defined!
1178 #ifdef MCS51REG_EXTERNAL_ROM
1179 #ifndef MCS51REG_UNDEFINE_P0
1180 #define MCS51REG_UNDEFINE_P0
1182 #ifndef MCS51REG_UNDEFINE_P2
1183 #define MCS51REG_UNDEFINE_P2
1187 #ifdef MCS51REG_EXTERNAL_RAM
1188 #ifndef MCS51REG_UNDEFINE_P0
1189 #define MCS51REG_UNDEFINE_P0
1191 #ifndef MCS51REG_UNDEFINE_P2
1192 #define MCS51REG_UNDEFINE_P2
1196 #ifdef MCS51REG_UNDEFINE_P0
1200 #ifdef MCS51REG_UNDEFINE_P2
1204 ////////////////////////////////
1205 /// Register definitions ///
1206 /// (In alphabetical order) ///
1207 ////////////////////////////////
1214 #ifdef ACON__PAGEE__PAGES__PAGE0__x__x__x__x__x
1215 #undef ACON__PAGEE__PAGES__PAGE0__x__x__x__x__x
1216 sfr at 0x9D ACON ; // DS89C420 specific
1217 // Not directly accessible bits
1223 #ifdef ACON__x__x__x__x__x__SA__AM1__AM0
1224 #undef ACON__x__x__x__x__x__SA__AM1__AM0
1225 sfr at 0x9D ACON ; // DS89C390 specific
1226 // Not directly accessible bits
1234 sfr at 0xC6 ADCH ; // A/D converter high
1239 sfr at 0xD8 ADCON ; // A/D-converter control register SAB80515 specific
1250 // ADCON0 ... Infineon / Siemens also called this register ADCON in the User Manual
1253 sfr at 0xD8 ADCON0 ; // A/D-converter control register 0 SAB80515A &
1254 // Bit registers // SAB80517 specific
1263 // Not directly accessible ADCON0
1264 #define ADCON0_MX0 0x01
1265 #define ADCON0_MX1 0x02
1266 #define ADCON0_MX2 0x04
1267 #define ADCON0_ADM 0x08
1268 #define ADCON0_BSY 0x10
1269 #define ADCON0_ADEX 0x20
1270 #define ADCON0_CLK 0x40
1271 #define ADCON0_BD 0x80
1276 sfr at 0xDC ADCON1 ; // A/D-converter control register 1 SAB80515A & SAB80517 specific
1277 // Not directly accessible ADCON1
1278 #define ADCON1_MX0 0x01
1279 #define ADCON1_MX1 0x02
1280 #define ADCON1_MX2 0x04
1281 #define ADCON1_ADCL 0x80
1284 #ifdef ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0
1285 #undef ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0
1286 sfr at 0xC5 ADCON ; // A/D control, P80C552 specific
1287 // Not directly accessible Bits.
1294 #define ADC_0 0x40 // different name as ADC0 in P5
1295 #define ADC_1 0x80 // different name as ADC1 in P5
1300 sfr at 0xD9 ADDAT ; // A/D-converter data register SAB80515 specific
1305 sfr at 0xD9 ADDATH ; // A/D data high byte SAB80515A specific
1310 sfr at 0xDA ADDATL ; // A/D data low byte SAB80515A specific
1315 sfr at 0xEF ARCON ; // arithmetic control register SAB80517
1320 sfr at 0x9C AP ; // DS80C390
1327 sbit at 0xF0 BREG_F0 ;
1328 sbit at 0xF1 BREG_F1 ;
1329 sbit at 0xF2 BREG_F2 ;
1330 sbit at 0xF3 BREG_F3 ;
1331 sbit at 0xF4 BREG_F4 ;
1332 sbit at 0xF5 BREG_F5 ;
1333 sbit at 0xF6 BREG_F6 ;
1334 sbit at 0xF7 BREG_F7 ;
1340 // Not directly accessible bits
1351 sfr at 0xA3 C0C ; // DS80C390 specific
1352 // Not directly accessible bits
1365 sfr at 0xA5 C0IR ; // DS80C390 specific
1366 // Not directly accessible bits
1379 sfr at 0xAB C0M1C ; // DS80C390 specific
1380 // Not directly accessible bits
1382 #define ROW_TIH 0x02
1393 sfr at 0xAC C0M2C ; // DS80C390 specific
1398 sfr at 0xAD C0M3C ; // DS80C390 specific
1403 sfr at 0xAE C0M4C ; // DS80C390 specific
1408 sfr at 0xAF C0M5C ; // DS80C390 specific
1413 sfr at 0xB3 C0M6C ; // DS80C390 specific
1418 sfr at 0xB4 C0M7C ; // DS80C390 specific
1423 sfr at 0xB5 C0M8C ; // DS80C390 specific
1428 sfr at 0xB6 C0M9C ; // DS80C390 specific
1433 sfr at 0xB7 C0M10C ; // DS80C390 specific
1438 sfr at 0xBB C0M11C ; // DS80C390 specific
1443 sfr at 0xBC C0M12C ; // DS80C390 specific
1448 sfr at 0xBD C0M13C ; // DS80C390 specific
1453 sfr at 0xBE C0M14C ; // DS80C390 specific
1458 sfr at 0xBF C0M15C ; // DS80C390 specific
1463 sfr at 0xA7 C0RE ; // DS80C390 specific
1468 sfr at 0x96 C0RMS0 ; // DS80C390 specific
1473 sfr at 0x97 C0RMS1 ; // DS80C390 specific
1478 sfr at 0xA4 C0S ; // DS80C390 specific
1479 // Not directly accessible bits
1486 #define EC96_128 0x40
1492 sfr at 0xA6 C0TE ; // DS80C390 specific
1497 sfr at 0x9E C0TMA0 ; // DS80C390 specific
1502 sfr at 0x9F C0TMA1 ; // DS80C390 specific
1507 sfr at 0xE3 C1C ; // DS80C390 specific
1508 // Not directly accessible bits
1521 sfr at 0xE5 C1IR ; // DS80C390 specific
1522 // Not directly accessible bits
1535 sfr at 0xE7 C1RE ; // DS80C390 specific
1540 sfr at 0xEB C1M1C ; // DS80C390 specific
1545 sfr at 0xEC C1M2C ; // DS80C390 specific
1550 sfr at 0xED C1M3C ; // DS80C390 specific
1555 sfr at 0xEE C1M4C ; // DS80C390 specific
1560 sfr at 0xEF C1M5C ; // DS80C390 specific
1565 sfr at 0xF3 C1M6C ; // DS80C390 specific
1570 sfr at 0xF4 C1M7C ; // DS80C390 specific
1575 sfr at 0xF5 C1M8C ; // DS80C390 specific
1580 sfr at 0xF6 C1M9C ; // DS80C390 specific
1585 sfr at 0xF7 C1M10C ; // DS80C390 specific
1590 sfr at 0xFB C1M11C ; // DS80C390 specific
1595 sfr at 0xFC C1M12C ; // DS80C390 specific
1600 sfr at 0xFD C1M13C ; // DS80C390 specific
1605 sfr at 0xFE C1M14C ; // DS80C390 specific
1610 sfr at 0xFF C1M15C ; // DS80C390 specific
1615 sfr at 0xE4 C1S ; // DS80C390 specific
1616 // Not directly accessible bits
1629 sfr at 0xE6 C1TE ; // DS80C390 specific
1634 sfr at 0xD6 C1RSM0 ; // DS80C390 specific
1639 sfr at 0xD7 C1RSM1 ; // DS80C390 specific
1644 sfr at 0xDE C1TMA0 ; // DS80C390 specific
1649 sfr at 0xDF C1TMA1 ; // DS80C390 specific
1654 sfr at 0xC9 CC4EN ; // compare/capture 4 enable register SAB80517 specific
1659 sfr at 0xC1 CCEN ; // compare/capture enable register SAB80515 specific
1664 sfr at 0xC3 CCH1 ; // compare/capture register 1, high byte SAB80515 specific
1669 sfr at 0xC5 CCH2 ; // compare/capture register 2, high byte SAB80515 specific
1674 sfr at 0xC7 CCH3 ; // compare/capture register 3, high byte SAB80515 specific
1679 sfr at 0xCF CCH4 ; // compare/capture register 4, high byte SAB80515 specific
1684 sfr at 0xC2 CCL1 ; // compare/capture register 1, low byte SAB80515 specific
1689 sfr at 0xC4 CCL2 ; // compare/capture register 2, low byte SAB80515 specific
1694 sfr at 0xC6 CCL3 ; // compare/capture register 3, low byte SAB80515 specific
1699 sfr at 0xCE CCL4 ; // compare/capture register 4, low byte SAB80515 specific
1704 sfr at 0x8E CKCON ; // DS80C320 & DS80C390 specific
1705 // Not directly accessible Bits.
1718 sfr at 0x96 CKMOD ; // DS89C420 specific
1719 // Not directly accessible Bits.
1727 sfr at 0xF6 CMEN ; // compare enable register SAB80517 specific
1732 sfr at 0xD3 CMH0 ; // compare register 0 high byte SAB80517 specific
1737 sfr at 0xD5 CMH1 ; // compare register 1 high byte SAB80517 specific
1742 sfr at 0xD7 CMH2 ; // compare register 2 high byte SAB80517 specific
1747 sfr at 0xE3 CMH3 ; // compare register 3 high byte SAB80517 specific
1752 sfr at 0xE5 CMH4 ; // compare register 4 high byte SAB80517 specific
1757 sfr at 0xE7 CMH5 ; // compare register 5 high byte SAB80517 specific
1762 sfr at 0xF3 CMH6 ; // compare register 6 high byte SAB80517 specific
1767 sfr at 0xF5 CMH7 ; // compare register 7 high byte SAB80517 specific
1772 sfr at 0xC9 CMH0 ; // Compare high 0, P80C552 specific
1777 sfr at 0xCA CMH1 ; // Compare high 1, P80C552 specific
1782 sfr at 0xCB CMH2 ; // Compare high 2, P80C552 specific
1787 sfr at 0xD2 CML0 ; // compare register 0 low byte SAB80517 specific
1792 sfr at 0xD4 CML1 ; // compare register 1 low byte SAB80517 specific
1797 sfr at 0xD6 CML2 ; // compare register 2 low byte SAB80517 specific
1802 sfr at 0xE2 CML3 ; // compare register 3 low byte SAB80517 specific
1807 sfr at 0xE4 CML4 ; // compare register 4 low byte SAB80517 specific
1812 sfr at 0xE6 CML5 ; // compare register 5 low byte SAB80517 specific
1817 sfr at 0xF2 CML6 ; // compare register 6 low byte SAB80517 specific
1822 sfr at 0xF4 CML7 ; // compare register 7 low byte SAB80517 specific
1827 sfr at 0xA9 CML0 ; // Compare low 0, P80C552 specific
1832 sfr at 0xAA CML1 ; // Compare low 1, P80C552 specific
1837 sfr at 0xAB CML2 ; // Compare low 2, P80C552 specific
1842 sfr at 0xF7 CMSEL ; // compare input select SAB80517
1847 sfr at 0xCE COR ; // Dallas DS80C390 specific
1860 sfr at 0xC1 CRC ; // Dallas DS5001 specific
1871 sfr at 0xCB CRCH ; // compare/reload/capture register, high byte SAB80515 specific
1876 sfr at 0xC3 CRCHIGH ; // DS5001 specific
1881 sfr at 0xCA CRCL ; // compare/reload/capture register, low byte SAB80515 specific
1886 sfr at 0xC2 CRCLOW ; // DS5001 specific
1889 #ifdef CTCOM_AT_0XE1
1890 #undef CTCOM_AT_0XE1
1891 sfr at 0xE1 CTCON ; // com.timer control register SAB80517
1894 #ifdef CTCON__CTN3__CTP3__CTN2__CTP2__CTN1__CTP1__CTN0__CTP0
1895 #undef CTCON__CTN3__CTP3__CTN2__CTP2__CTN1__CTP1__CTN0__CTP0
1896 sfr at 0xEB CTCON ; // Capture control, P80C552 specific
1897 // Not directly accessible Bits.
1910 sfr at 0xCC CTH0 ; // Capture high 0, P80C552 specific
1915 sfr at 0xCD CTH1 ; // Capture high 1, P80C552 specific
1920 sfr at 0xCE CTH2 ; // Capture high 2, P80C552 specific
1925 sfr at 0xCF CTH3 ; // Capture high 3, P80C552 specific
1930 sfr at 0xAC CTL0 ; // Capture low 0, P80C552 specific
1935 sfr at 0xAD CTL1 ; // Capture low 1, P80C552 specific
1940 sfr at 0xAE CTL2 ; // Capture low 2, P80C552 specific
1945 sfr at 0xAF CTL3 ; // Capture low 3, P80C552 specific
1950 sfr at 0xDF CTRELH ; // com.timer rel register high byte SAB80517
1955 sfr at 0xDE CTRELL ; // com.timer rel register low byte SAB80517
1958 #ifdef DAPR__SAB80515
1959 #undef DAPR__SAB80515
1960 sfr at 0xD8 DAPR ; // D/A-converter program register SAB80515 specific
1963 #ifdef DAPR__SAB80517
1964 #undef DAPR__SAB80517
1965 sfr at 0xDA DAPR ; // D/A-converter program register SAB80517 specific
1971 sfr at 0x83 DP0H ; // Alternate name for AT89S53
1976 sfr at 0x85 DPH1 ; // DS80C320 specific
1977 sfr at 0x85 DP1H ; // Alternate name for AT89S53
1982 sfr at 0x82 DPL ; // Alternate name for AT89S53
1988 sfr at 0x84 DPL1 ; // DS80C320 specific
1989 sfr at 0x84 DP1L ; // Alternate name for AT89S53
1992 #ifdef DPS__x__x__x__x__x__x__x__SEL
1993 #undef DPS__x__x__x__x__x__x__x__SEL
1995 // Not directly accessible DPS Bit. DS80C320 & DPS8XC520 specific
1999 #ifdef DPS__ID1__ID0__TSL__x__x__x__x__SEL
2000 #undef DPS__ID1__ID0__TSL__x__x__x__x__SEL
2002 // Not directly accessible DPS Bit. DS89C390 specific
2009 #ifdef DPS__ID1__ID0__TSL__AID__x__x__x__SEL
2010 #undef DPS__ID1__ID0__TSL__AID__x__x__x__SEL
2012 // Not directly accessible DPS Bit. DS89C420 specific
2022 sfr at 0x92 DPSEL ; // data pointer select register SAB80517
2027 sfr at 0x93 DPX1 ; // DS80C390 specific
2032 sfr at 0x95 DPX1 ; // DS80C390 specific
2035 #ifdef EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
2036 #undef EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
2038 // Bit registers DS80C320 specific
2046 #ifdef EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2
2047 #undef EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2
2049 // Bit registers DS80C390 specific
2057 sbit at 0xEF CANBIE ;
2060 #ifdef EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
2061 #undef EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
2063 // Bit registers DS80C320 specific
2071 #ifdef EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
2072 #undef EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
2074 // Bit registers DS80C320 specific
2082 sbit at 0xFF CANBIP ;
2088 // Not directly accessible Bits DS80C390 specific
2093 #ifdef EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
2094 #undef EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
2096 // Not directly accessible EXIF Bits DS80C320 specific
2106 #ifdef EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
2107 #undef EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
2109 // Not directly accessible EXIF Bits DS87C520 specific
2120 #ifdef EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
2121 #undef EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
2123 // Not directly accessible EXIF Bits DS80C390 & DS89C420 specific
2134 #ifdef IE__EA__x__x__ES__ET1__EX1__ET0__EX0
2135 #undef IE__EA__x__x__ES__ET1__EX1__ET0__EX0
2146 #ifdef IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
2147 #undef IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
2155 sbit at 0xAD ET2 ; // Enable timer2 interrupt
2159 #ifdef IE__EA__EAD__ES1__ES0__ET1__EX1__ET0__EX0
2160 #undef IE__EA__EAD__ES1__ES0__ET1__EX1__ET0__EX0
2161 sfr at 0xA8 IE ; // same as IEN0 - Interrupt enable 0, P80C552 specific
2162 sfr at 0xA8 IEN0 ; // alternate name
2174 #ifdef IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
2175 #undef IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
2183 sbit at 0xAC ES0 ; // Alternate name
2184 sbit at 0xAD ET2 ; // Enable timer2 interrupt
2189 #ifdef IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
2190 #undef IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
2192 sfr at 0xA8 IEN0 ; // Alternate name
2193 // Bit registers for the SAB80515 and compatible IE
2200 sbit at 0xAD ET2 ; // Enable timer 2 overflow SAB80515 specific
2201 sbit at 0xAE WDT ; // watchdog timer reset - SAB80515 specific
2203 sbit at 0xAF EAL ; // EA as called by Infineon / Siemens
2206 #ifdef IEN1__ET2__ECM2__ECM1__ECM0__ECT3__ECT2__ECT1__ECT0
2207 #undef IEN1__ET2__ECM2__ECM1__ECM0__ECT3__ECT2__ECT1__ECT0
2208 sfr at 0xE8 IEN1 ; // Interrupt enable 1, P80C552 specific
2220 #ifdef IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
2221 #undef IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
2222 sfr at 0xB8 IEN1 ; // interrupt enable register - SAB80515 specific
2224 sbit at 0xB8 EADC ; // A/D converter interrupt enable
2230 sbit at 0xBE SWDT ; // watchdog timer start/reset
2231 sbit at 0xBF EXEN2 ; // timer2 external reload interrupt enable
2234 #ifdef IEN2__SAB80517
2235 #undef IEN2__SAB80517
2236 sfr at 0x9A IEN2 ; // interrupt enable register 2 SAB80517
2239 #ifdef IP__x__x__x__PS__PT1__PX1__PT0__PX0
2240 #undef IP__x__x__x__PS__PT1__PX1__PT0__PX0
2250 #ifdef IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
2251 #undef IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
2259 sbit at 0xBC PS0 ; // alternate name
2263 #ifdef IP__x__PAD__PS1__PS0__PT1__PX1__PT0__PX0
2264 #undef IP__x__PAD__PS1__PS0__PT1__PX1__PT0__PX0
2265 sfr at 0xB8 IP ; // Interrupt priority 0, P80C552 specific
2266 sfr at 0xB8 IP0 ; // alternate name
2277 #ifdef IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
2278 #undef IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
2290 #ifdef IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
2291 #undef IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
2302 #ifdef IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
2303 #undef IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
2304 sfr at 0xA9 IP0 ; // interrupt priority register SAB80515 specific
2305 // Not directly accessible IP0 bits
2315 #ifdef IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
2316 #undef IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
2317 sfr at 0xB8 IP0 ; // interrupt priority register DS89C420 specific
2318 // Not directly accessible IP0 bits
2328 #ifdef IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
2329 #undef IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
2330 sfr at 0xB9 IP1 ; // interrupt priority register SAB80515 specific
2331 // Not directly accessible IP1 bits
2340 #ifdef IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
2341 #undef IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
2342 sfr at 0xB1 IP1 ; // interrupt priority register DS89C420 specific
2343 // Not directly accessible IP0 bits
2353 #ifdef IP1__PT2__PCM2__PCM1__PCM0__PCT3__PCT2__PCT1__PCT0
2354 #undef IP1__PT2__PCM2__PCM1__PCM0__PCT3__PCT2__PCT1__PCT0
2355 sfr at 0xF8 IP1 ; // Interrupt priority 1, P80C552 specific
2369 sfr at 0xC0 IRCON ; // interrupt control register - SAB80515 specific
2371 sbit at 0xC0 IADC ; // A/D converter irq flag
2372 sbit at 0xC1 IEX2 ; // external interrupt edge detect flag
2377 sbit at 0xC6 TF2 ; // timer 2 owerflow flag
2378 sbit at 0xC7 EXF2 ; // timer2 reload flag
2383 sfr at 0xC0 IRCON0 ; // interrupt control register - SAB80515 specific
2385 sbit at 0xC0 IADC ; // A/D converter irq flag
2386 sbit at 0xC1 IEX2 ; // external interrupt edge detect flag
2391 sbit at 0xC6 TF2 ; // timer 2 owerflow flag
2392 sbit at 0xC7 EXF2 ; // timer2 reload flag
2397 sfr at 0xD1 IRCON1 ; // interrupt control register - SAB80515 specific
2402 sfr at 0xD3 MA ; // DS80C390
2407 sfr at 0xD4 MB ; // DS80C390
2412 sfr at 0xD5 MC ; // DS80C390
2417 sfr at 0xD1 MCNT0 ; // DS80C390
2430 sfr at 0xD2 MCNT1 ; // DS80C390
2436 #ifdef MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0
2437 #undef MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0
2438 sfr at 0xC6 MCON ; // DS80C390
2448 #ifdef MCON__PA3__PA2__PA1__PA0__RA32_8__ECE2__PAA__SL
2449 #undef MCON__PA3__PA2__PA1__PA0__RA32_8__ECE2__PAA__SL
2450 sfr at 0xC6 MCON ; // DS5000
2461 #ifdef MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL
2462 #undef MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL
2463 sfr at 0xC6 MCON ; // DS5001
2476 sfr at 0xE9 MD0 ; // MUL / DIV register 0 SAB80517
2481 sfr at 0xEA MD1 ; // MUL / DIV register 1 SAB80517
2486 sfr at 0xEB MD2 ; // MUL / DIV register 2 SAB80517
2491 sfr at 0xEC MD3 ; // MUL / DIV register 3 SAB80517
2496 sfr at 0xED MD4 ; // MUL / DIV register 4 SAB80517
2501 sfr at 0xEE MD5 ; // MUL / DIV register 5 SAB80517
2506 sfr at 0xEA MXAX ; // Dallas DS80C390
2537 #ifdef P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
2538 #undef P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
2539 // P1 alternate functions
2550 #ifdef P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
2551 sbit at 0x90 INT3_CC0 ; // P1 alternate functions - SAB80515 specific
2552 sbit at 0x91 INT4_CC1 ;
2553 sbit at 0x92 INT5_CC2 ;
2554 sbit at 0x93 INT6_CC3 ;
2557 sbit at 0x96 CLKOUT ;
2561 #ifdef P1_EXT__CT0I__CT1I__CT2I__CT3I__T2__RT2__SCL__SDA
2562 #undef P1_EXT__CT0I__CT1I__CT2I__CT3I__T2__RT2__SCL__SDA
2564 sbit at 0x90 CT0I ; // Port 1 alternate functions, P80C552 specific
2574 #ifdef P1_EXT__x__x__x__x__x__x__T2EX__T2
2575 #undef P1_EXT__x__x__x__x__x__x__T2EX__T2
2576 // P1 alternate functions
2605 #ifndef MCS51REG_EXTERNAL_RAM
2618 #ifndef MCS51REG_EXTERNAL_RAM
2626 sfr at 0x80 P4 ; // Port 4 - DS80C390
2640 sfr at 0xC0 P4 ; // Port 4, P80C552 specific
2642 sbit at 0xC0 CMSR0 ;
2643 sbit at 0xC1 CMSR1 ;
2644 sbit at 0xC2 CMSR2 ;
2645 sbit at 0xC3 CMSR3 ;
2646 sbit at 0xC4 CMSR4 ;
2647 sbit at 0xC5 CMSR5 ;
2654 sfr at 0xE8 P4 ; // Port 4 - SAB80515 & compatible microcontrollers
2668 sfr at 0x92 P4CNT ; // DS80C390
2669 // Not directly accessible bits
2670 #define P4CNT_0 0x01
2671 #define P4CNT_1 0x02
2672 #define P4CNT_2 0x04
2673 #define P4CNT_3 0x08
2674 #define P4CNT_4 0x10
2675 #define P4CNT_5 0x20
2681 sfr at 0xA1 P5 ; // Port 5 - DS80C390
2686 sfr at 0xA2 P5CNT ; // DS80C390
2687 // Not directly accessible bits
2688 #define P5CNT_0 0x01
2689 #define P5CNT_1 0x02
2690 #define P5CNT_2 0x04
2694 #define SBCAN0BA 0x40
2695 #define SBCAN1BA 0x80
2700 sfr at 0xC4 P5 ; // Port 5, P80C552 specific
2701 // Not directly accessible Bits.
2714 sfr at 0xF8 P5 ; // Port 5 - SAB80515 & compatible microcontrollers
2728 sfr at 0xDB P6 ; // Port 6 - SAB80515 & compatible microcontrollers
2733 sfr at 0xFA P6 ; // Port 6 - SAB80517 specific
2738 sfr at 0xDB P7 ; // Port 7 - SAB80517 specific
2743 sfr at 0xDD P8 ; // Port 6 - SAB80517 specific
2746 #ifdef PCON__SMOD__x__x__x__x__x__x__x
2747 #undef PCON__SMOD__x__x__x__x__x__x__x
2749 // Not directly accessible PCON bits
2753 #ifdef PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
2754 #undef PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
2756 // Not directly accessible PCON bits
2764 #ifdef PCON__SMOD__x__x__WLE__GF1__GF0__PD__IDL
2765 #undef PCON__SMOD__x__x__WLE__GF1__GF0__PD__IDL
2766 sfr at 0x87 PCON ; // PCON, P80C552 specific
2767 // Not directly accessible Bits.
2769 #define IDLE 0x01 ; same as IDL
2777 #ifdef PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
2778 #undef PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
2780 // Not directly accessible PCON bits
2782 #define IDLE 0x01 ; same as IDL
2784 #define PDE 0x02 ; same as PD
2789 #define PCON_IDLE 0x01
2790 #define PCON_PDE 0x02
2791 #define PCON_GF0 0x04
2792 #define PCON_GF1 0x08
2793 #define PCON_IDLS 0x20
2794 #define PCON_PDS 0x40
2795 #define PCON_SMOD 0x80
2798 #ifdef PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
2799 #undef PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
2801 // Not directly accessible PCON bits
2803 #define IDLE 0x01 ; same as IDL
2813 #ifdef PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
2814 #undef PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
2816 // Not directly accessible PCON bits
2818 #define IDLE 0x01 ; same as IDL
2826 #ifdef PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
2827 #undef PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
2829 // Not directly accessible PCON bits
2831 #define IDLE 0x01 ; same as IDL
2839 #define SMOD_0 0x80 ; same as SMOD
2842 #ifdef PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1_DME0
2843 #undef PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1_DME0
2844 sfr at 0xC4 PMR ; // DS87C520, DS83C520
2845 // Not directly accessible bits
2855 #ifdef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEOFF__x__x
2856 #undef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEOFF__x__x
2857 sfr at 0xC4 PMR ; // DS80C390
2858 // Not directly accessible bits
2883 sfr at 0xFC PWM0 ; // PWM register 0, P80C552 specific
2888 sfr at 0xFD PWM1 ; // PWM register 1, P80C552 specific
2893 sfr at 0xFE PWMP ; // PWM prescaler, P80C552 specific
2898 sfr at 0xCB RCAP2H ;
2903 sfr at 0xCA RCAP2L ;
2911 #ifdef ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0
2912 #undef ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0
2913 sfr at 0xC2 ROMSIZE ; // DS87C520, DS83C520
2914 // Not directly accessible bits
2920 #ifdef ROMSIZE__HBPF__BPF__TE__MOVCX__PRAME__RMS2__RMS1__RMS0
2921 #undef ROMSIZE__HBPF__BPF__TE__MOVCX__PRAME__RMS2__RMS1__RMS0
2922 sfr at 0xC2 ROMSIZE ; // DS87C520, DS83C520
2923 // Not directly accessible bits
2936 sfr at 0xD8 RPCTL ; // Dallas DS5001 specific
2938 sbit at 0xD9 RPCON ;
2943 sbit at 0xDF RNR_FLAG ;
2946 #ifdef RTE__TP47__TP46__RP45__RP44__RP43__RP42__RP41__RP40
2947 #undef RTE__TP47__TP46__RP45__RP44__RP43__RP42__RP41__RP40
2948 sfr at 0xEF RTE ; // Reset/toggle enable, P80C552 specific
2949 // Not directly accessible Bits.
2962 sfr at 0x99 S0BUF ; // serial channel 0 buffer register SAB80517 specific
2965 #ifdef S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI
2966 #undef S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI
2967 sfr at 0x98 S0CON ; // serial channel 0 control register P80C552 specific
2969 // Already defined in SCON
2970 //sbit at 0x98 RI0 ;
2971 //sbit at 0x99 TI0 ;
2972 //sbit at 0x9A RB8 ;
2973 //sbit at 0x9B TB8 ;
2974 //sbit at 0x9C REN ;
2975 //sbit at 0x9D SM2 ;
2976 //sbit at 0x9E SM1 ;
2977 //sbit at 0x9F SM0 ;
2980 #ifdef S0CON__SM0__SM1__SM20__REN0__TB80__RB80__TI0__RI0
2981 #undef S0CON__SM0__SM1__SM20__REN0__TB80__RB80__TI0__RI0
2982 // serial channel 0 buffer register SAB80517 specific(same as stock SCON)
2998 sfr at 0xAA S0RELL ; // serial channel 0 reload register low byte SAB80517 specific
3003 sfr at 0xBA S0RELH ; // serial channel 0 reload register high byte SAB80517 specific
3006 #ifdef S1ADR__x__x__x__x__x__x__x__GC
3007 #undef S1ADR__x__x__x__x__x__x__x__GC
3008 sfr at 0xDB S1ADR ; // Serial 1 address, P80C552 specific
3009 // Not directly accessible Bits.
3015 sfr at 0x9C S1BUF ; // serial channel 1 buffer register SAB80517 specific
3018 #ifdef S1CON_AT_0X9B
3019 #undef S1CON_AT_0X9B
3020 sfr at 0x9B S1CON ; // serial channel 1 control register SAB80517 specific
3023 #ifdef S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0
3024 #undef S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0
3025 sfr at 0xD8 S1CON ; // Serial 1 control, P80C552 specific
3026 sfr at 0xD8 SICON ; // sometimes called SICON
3038 #ifdef S1DAT_AT_0XDA
3039 #undef S1DAT_AT_0XDA
3040 sfr at 0xDA S1DAT ; // Serial 1 data, P80C552 specific
3041 sfr at 0xDA SIDAT ; // sometimes called SIDAT
3046 sfr at 0x9D S1RELL ; // serial channel 1 reload register low byte SAB80517 specific
3051 sfr at 0xBB S1RELH ; // serial channel 1 reload register high byte SAB80517 specific
3054 #ifdef S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x
3055 #undef S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x
3056 sfr at 0xD9 S1STA ; // Serial 1 status, P80C552 specific
3057 // Not directly accessible Bits.
3067 // DS80C320 specific
3068 sfr at 0xA9 SADDR0 ;
3073 // DS80C320 specific
3074 sfr at 0xAA SADDR1 ;
3079 // DS80C320 & DS80C390 specific
3080 sfr at 0xB9 SADEN0 ;
3085 // DS80C320 & DS80C390 specific
3086 sfr at 0xBA SADEN1 ;
3097 // DS80C320 & DS80C390 specific
3121 sbit at 0x9A RB8_0 ;
3122 sbit at 0x9B TB8_0 ;
3123 sbit at 0x9C REN_0 ;
3124 sbit at 0x9D SM2_0 ;
3125 sbit at 0x9E SM1_0 ;
3126 sbit at 0x9F SM0_0 ;
3128 sbit at 0x9F SM0_FE_0 ;
3133 // DS80C320 - 80C390 specific
3138 sbit at 0xC2 RB8_1 ;
3139 sbit at 0xC3 TB8_1 ;
3140 sbit at 0xC4 REN_1 ;
3141 sbit at 0xC5 SM2_1 ;
3142 sbit at 0xC6 SM1_1 ;
3143 sbit at 0xC7 SM0_1 ;
3145 sbit at 0xC7 SM0_FE_1 ;
3155 sfr at 0xD5 SPCR ; // AT89S53 specific
3156 // Not directly accesible bits
3169 sfr at 0x86 SPDR ; // AT89S53 specific
3170 // Not directly accesible bits
3183 sfr at 0xAA SPSR ; // AT89S53 specific
3184 // Not directly accesible bits
3191 sfr at 0xBA SRELH ; // Baudrate generator reload high
3196 sfr at 0xAA SRELL ; // Baudrate generator reload low
3199 #ifdef STATUS__PIP__HIP__LIP__x__x__x__x__x
3200 #undef STATUS__PIP__HIP__LIP__x__x__x__x__x
3201 // DS80C320 specific
3202 sfr at 0xC5 STATUS ;
3203 // Not directly accessible Bits. DS80C320 specific
3209 #ifdef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
3210 #undef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
3211 sfr at 0xC5 STATUS ; // DS80C390 specific
3212 // Not directly accessible Bits.
3222 #ifdef STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
3223 #undef STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
3224 sfr at 0xC5 STATUS ; // DS87C520 & DS83520specific
3225 // Not directly accessible Bits.
3236 #ifdef STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF
3237 #undef STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF
3238 sfr at 0xDA STATUS ; // DS5001specific
3239 // Not directly accessible Bits.
3250 #ifdef STE__TG47__TG46__SP45__SP44__SP43__SP42__SP41__SP40
3251 #undef STE__TG47__TG46__SP45__SP44__SP43__SP42__SP41__SP40
3252 sfr at 0xEE STE ; // Set enable, P80C552 specific
3253 // Not directly accessible Bits.
3266 sfr at 0xB1 SYSCON ; // XRAM Controller Access Control
3268 #define SYSCON_XMAP0 0x01
3269 #define SYSCON_XMAP1 0x02
3270 #define SYSCON_RMAP 0x10
3271 #define SYSCON_EALE 0x20
3274 #ifdef T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
3275 #undef T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
3277 // Definitions for the 8052 compatible microcontrollers.
3279 sbit at 0xC8 CP_RL2 ;
3282 sbit at 0xCB EXEN2 ;
3288 sbit at 0xC8 T2CON_0 ;
3289 sbit at 0xC9 T2CON_1 ;
3290 sbit at 0xCA T2CON_2 ;
3291 sbit at 0xCB T2CON_3 ;
3292 sbit at 0xCC T2CON_4 ;
3293 sbit at 0xCD T2CON_5 ;
3294 sbit at 0xCE T2CON_6 ;
3295 sbit at 0xCF T2CON_7 ;
3298 #ifdef T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
3299 #undef T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
3301 // Definitions for the Infineon / Siemens SAB80515, SAB80515A, SAB80517
3312 sbit at 0xC8 T2CON_0 ;
3313 sbit at 0xC9 T2CON_1 ;
3314 sbit at 0xCA T2CON_2 ;
3315 sbit at 0xCB T2CON_3 ;
3316 sbit at 0xCC T2CON_4 ;
3317 sbit at 0xCD T2CON_5 ;
3318 sbit at 0xCE T2CON_6 ;
3319 sbit at 0xCF T2CON_7 ;
3322 #ifdef T2MOD__x__x__x__D13T1__D13T2__x__T2OE__DCEN
3323 #undef T2MOD__x__x__x__D13T1__D13T2__x__T2OE__DCEN
3324 // Definitions for the timer/counter 2 of the Atmel & Dallas microcontrollers
3326 // Not not directly accessible T2MOD bits
3333 #ifdef T2MOD__x__x__x__x__x__x__T2OE__DCEN
3334 #undef T2MOD__x__x__x__x__x__x__T2OE__DCEN
3335 // Definitions for the timer/counter 2 of the Atmel 89x52 microcontroller
3337 // Not not directly accessible T2MOD bits
3347 sfr at 0xFF T3 ; // Timer 3, P80C552 specific
3352 // DS500x, DS80C320 & DS80C390 specific
3403 // Not directly accessible TMOD bits
3407 #define T0_GATE 0x08
3411 #define T1_GATE 0x80
3413 #define T0_MASK 0x0F
3414 #define T1_MASK 0xF0
3417 #ifdef TM2CON__T2IS1__T2IS0__T2ER__T2B0__T2P1__T2P0__T2MS1__T2MS0
3418 #undef TM2CON__T2IS1__T2IS0__T2ER__T2B0__T2P1__T2P0__T2MS1__T2MS0
3419 sfr at 0xEA TM2CON ; // Timer 2 control, P80C552 specific
3420 // Not directly accessible Bits.
3431 #ifdef TM2IR__T20V__CMI2__CMI1__CMI0__CTI3__CTI2__CTI1__CTI0
3432 #undef TM2IR__T20V__CMI2__CMI1__CMI0__CTI3__CTI2__CTI1__CTI0
3433 sfr at 0xC8 TM2IR ; // Timer 2 int flag reg, P80C552 specific
3447 sfr at 0xED TMH2 ; // Timer high 2, P80C552 specific
3452 sfr at 0xEC TML2 ; // Timer low 2, P80C552 specific
3457 sfr at 0x96 WCON ; // AT89S53 specific
3458 // Not directly accesible bits
3469 // DS80C320 - 390 specific
3479 sbit at 0xDF SMOD_1 ;
3484 sfr at 0x86 WDTREL ; // Watchdof Timer reload register
3489 sfr at 0x91 XPAGE ; // Page Address Register for Extended On-Chip Ram - Infineon / Siemens SAB80515A specific
3493 /////////////////////////
3494 /// Interrupt vectors ///
3495 /////////////////////////
3497 // Interrupt numbers: address = (number * 8) + 3
3498 #define IE0_VECTOR 0 // 0x03 external interrupt 0
3499 #define TF0_VECTOR 1 // 0x0b timer 0
3500 #define IE1_VECTOR 2 // 0x13 external interrupt 1
3501 #define TF1_VECTOR 3 // 0x1b timer 1
3502 #define SI0_VECTOR 4 // 0x23 serial port 0
3504 #ifdef MICROCONTROLLER_AT89S53
3505 #define TF2_VECTOR 5 /* 0x2B timer 2 */
3506 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
3509 #ifdef MICROCONTROLLER_AT89X52
3510 #define TF2_VECTOR 5 /* 0x2B timer 2 */
3511 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
3514 #ifdef MICROCONTROLLER_AT89X55
3515 #define TF2_VECTOR 5 /* 0x2B timer 2 */
3516 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
3519 #ifdef MICROCONTROLLER_DS5000
3520 #define PFW_VECTOR 5 /* 0x2B */
3523 #ifdef MICROCONTROLLER_DS5001
3524 #define PFW_VECTOR 5 /* 0x2B */
3527 #ifdef MICROCONTROLLER_DS80C32X
3528 #define TF2_VECTOR 5 /* 0x2B */
3529 #define PFI_VECTOR 6 /* 0x33 */
3530 #define SIO1_VECTOR 7 /* 0x3B */
3531 #define IE2_VECTOR 8 /* 0x43 */
3532 #define IE3_VECTOR 9 /* 0x4B */
3533 #define IE4_VECTOR 10 /* 0x53 */
3534 #define IE5_VECTOR 11 /* 0x5B */
3535 #define WDI_VECTOR 12 /* 0x63 */
3538 #ifdef MICROCONTROLLER_DS8XC520
3539 #define TF2_VECTOR 5 /* 0x2B */
3540 #define PFI_VECTOR 6 /* 0x33 */
3541 #define SIO1_VECTOR 7 /* 0x3B */
3542 #define IE2_VECTOR 8 /* 0x43 */
3543 #define IE3_VECTOR 9 /* 0x4B */
3544 #define IE4_VECTOR 10 /* 0x53 */
3545 #define IE5_VECTOR 11 /* 0x5B */
3546 #define WDI_VECTOR 12 /* 0x63 */
3549 #ifdef MICROCONTROLLER_P80C552
3550 #define SIO1_VECTOR 5 // 0x2B SIO1 (I2C)
3551 #define CT0_VECTOR 6 // 0x33 T2 capture 0
3552 #define CT1_VECTOR 7 // 0x3B T2 capture 1
3553 #define CT2_VECTOR 8 // 0x43 T2 capture 2
3554 #define CT3_VECTOR 9 // 0x4B T2 capture 3
3555 #define ADC_VECTOR 10 // 0x53 ADC completion
3556 #define CM0_VECTOR 11 // 0x5B T2 compare 0
3557 #define CM1_VECTOR 12 // 0x63 T2 compare 1
3558 #define CM2_VECTOR 13 // 0x6B T2 compare 2
3559 #define TF2_VECTOR 14 // 0x73 T2 overflow
3562 #ifdef MICROCONTROLLER_SAB80515
3563 #define TF2_VECTOR 5 // 0x2B timer 2
3564 #define EX2_VECTOR 5 // 0x2B external interrupt 2
3565 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt
3566 #define IEX2_VECTOR 9 // 0x4B external interrupt 2
3567 #define IEX3_VECTOR 10 // 0x53 external interrupt 3
3568 #define IEX4_VECTOR 11 // 0x5B external interrupt 4
3569 #define IEX5_VECTOR 12 // 0x63 external interrupt 5
3570 #define IEX6_VECTOR 13 // 0x6B external interrupt 6
3573 #ifdef MICROCONTROLLER_SAB80515A
3574 #define TF2_VECTOR 5 // 0x2B timer 2
3575 #define EX2_VECTOR 5 // 0x2B external interrupt 2
3576 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt
3577 #define IEX2_VECTOR 9 // 0x4B external interrupt 2
3578 #define IEX3_VECTOR 10 // 0x53 external interrupt 3
3579 #define IEX4_VECTOR 11 // 0x5B external interrupt 4
3580 #define IEX5_VECTOR 12 // 0x63 external interrupt 5
3581 #define IEX6_VECTOR 13 // 0x6B external interrupt 6
3584 #ifdef MICROCONTROLLER_SAB80517
3585 #define TF2_VECTOR 5 // 0x2B timer 2
3586 #define EX2_VECTOR 5 // 0x2B external interrupt 2
3587 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt
3588 #define IEX2_VECTOR 9 // 0x4B external interrupt 2
3589 #define IEX3_VECTOR 10 // 0x53 external interrupt 3
3590 #define IEX4_VECTOR 11 // 0x5B external interrupt 4
3591 #define IEX5_VECTOR 12 // 0x63 external interrupt 5
3592 #define IEX6_VECTOR 13 // 0x6B external interrupt 6
3595 #define SI1_VECTOR 16 // 0x83 serial port 1
3598 #define COMPARE_VECTOR 19 // 0x9B compare
3601 #endif // End of the header -> #ifndef MCS51REG_H