1 /*****************************************************************************
5 |* This file contains definitions for the builtin CAN-Bus Controller of
6 |* the Siemens c515c controller
8 ****************************************************************************/
13 /* define CPU_CLK_10MHZ or CPU_CLK_8MHZ to select the right values for */
14 /* the bit timing registers */
18 /* address of can controller in xmem */
19 #define CAN_CTRL 0xf700
21 /* size of message buffer including 1 dummy byte at end */
22 #define CAN_MSG_SZ 0x10
24 /* register offset definitions */
37 #define MSG15MSK_0 0xc
38 #define MSG15MSK_1 0xd
39 #define MSG15MSK_2 0xe
40 #define MSG15MSK_3 0xf
42 /* register offsets in message buffer */
50 /* beginning of message data */
53 /* bits in cntr_x registers */
64 /* macros for setting and resetting above bits, see Siemens documentation */
65 #define MCR_BIT_SET(p,x) ((p) = (0xff & ~((x) >> 1)))
66 #define MCR_BIT_RES(p,x) ((p) = (0xff & ~(x)))
68 /* direction = transmit in mcfg */
69 #define DIR_TRANSMIT 0x8
71 /* constants for bit timing registers */
75 #define BT_1_125K 0x1c
77 #define BT_1_250K 0x1c
79 #define BT_1_500K 0x1c
86 #define BT_1_125K 0x1c
88 #define BT_1_250K 0x1c
90 #define BT_1_500K 0x2f
95 /* Control register bits */
104 /* status register bits */
115 typedef struct can_msg
124 unsigned char data_bytes[8];
128 __xdata __at CAN_CTRL struct
142 unsigned char msg15msk_0;
143 unsigned char msg15msk_1;
144 unsigned char msg15msk_2;
145 unsigned char msg15msk_3;
146 struct can_msg msgbufs[15];
149 /* Byte registers in numerical order */
155 __sfr __at 0x86 WDTREL;
156 __sfr __at 0x87 PCON;
157 __sfr __at 0x88 TCON;
158 __sfr __at 0x88 PCON1;
159 __sfr __at 0x89 TMOD;
165 __sfr __at 0x91 XPAGE;
166 __sfr __at 0x92 DPSEL;
167 __sfr __at 0x93 SSCCON;
170 __sfr __at 0x96 SSCMOD;
171 __sfr __at 0x98 SCON;
172 __sfr __at 0x99 SBUF;
173 __sfr __at 0x9A IEN2;
175 __sfr __at 0xA8 IEN0;
177 __sfr __at 0xAA SRELL;
179 __sfr __at 0xAC SCIEN;
181 __sfr __at 0xB1 SYSCON;
182 __sfr __at 0xB8 IEN1;
184 __sfr __at 0xBA SRELH;
185 __sfr __at 0xC0 IRCON;
186 __sfr __at 0xC1 CCEN;
187 __sfr __at 0xC2 CCL1;
188 __sfr __at 0xC3 CCH1;
189 __sfr __at 0xC4 CCL2;
190 __sfr __at 0xC5 CCH2;
191 __sfr __at 0xC6 CCL3;
192 __sfr __at 0xC7 CCH3;
193 __sfr __at 0xC8 T2CON;
194 __sfr __at 0xCA CRCL;
195 __sfr __at 0xCB CRCH;
199 __sfr __at 0xD8 ADCON0;
200 __sfr __at 0xD9 ADDATH;
201 __sfr __at 0xDA ADDATL;
203 __sfr __at 0xDC ADCON1;
208 __sfr __at 0xF8 DIR5;
212 /* defining bits in SFR P0 */
213 __sbit __at 0x80 P0_0;
214 __sbit __at 0x81 P0_1;
215 __sbit __at 0x82 P0_2;
216 __sbit __at 0x83 P0_3;
217 __sbit __at 0x84 P0_4;
218 __sbit __at 0x85 P0_5;
219 __sbit __at 0x86 P0_6;
220 __sbit __at 0x87 P0_7;
224 /* defining bits in SFR PCON1 */
225 __sbit __at 0x88 IT0;
226 __sbit __at 0x89 IE0;
227 __sbit __at 0x8a IT1;
228 __sbit __at 0x8b IE1;
229 __sbit __at 0x8c TR0;
230 __sbit __at 0x8d TF0;
231 __sbit __at 0x8e TR1;
232 __sbit __at 0x8f TF1;
233 __sbit __at 0x8f EWPD;
237 /* defining bits in SFR P1 */
238 __sbit __at 0x90 P1_0;
239 __sbit __at 0x90 INT3;
240 __sbit __at 0x91 P1_1;
241 __sbit __at 0x91 INT4;
242 __sbit __at 0x92 P1_2;
243 __sbit __at 0x92 INT5;
244 __sbit __at 0x93 P1_3;
245 __sbit __at 0x93 INT6;
246 __sbit __at 0x94 P1_4;
247 __sbit __at 0x94 INT2;
248 __sbit __at 0x95 P1_5;
249 __sbit __at 0x95 T2EX;
250 __sbit __at 0x96 P1_6;
251 __sbit __at 0x96 CLKOUT;
252 __sbit __at 0x97 P1_7;
257 /* defining bits in SFR SCON */
260 __sbit __at 0x9a RB8;
261 __sbit __at 0x9b TB8;
262 __sbit __at 0x9c REN;
263 __sbit __at 0x9d SM2;
264 __sbit __at 0x9e SM1;
265 __sbit __at 0x9f SM0;
269 /* defining bits in SFR P2 */
270 __sbit __at 0xa0 P2_0;
271 __sbit __at 0xa1 P2_1;
272 __sbit __at 0xa2 P2_2;
273 __sbit __at 0xa3 P2_3;
274 __sbit __at 0xa4 P2_4;
275 __sbit __at 0xa5 P2_5;
276 __sbit __at 0xa6 P2_6;
277 __sbit __at 0xa7 P2_7;
281 /* defining bits in SFR IEN0 */
282 __sbit __at 0xa8 EX0;
283 __sbit __at 0xa9 ET0;
284 __sbit __at 0xaa EX1;
285 __sbit __at 0xab ET1;
287 __sbit __at 0xad ET2;
288 __sbit __at 0xae WDT;
293 /* defining bits in SFR P3 */
294 __sbit __at 0xb0 P3_0;
295 __sbit __at 0xb0 RXD;
296 __sbit __at 0xb1 P3_1;
297 __sbit __at 0xb1 TXD;
298 __sbit __at 0xb2 P3_2;
299 __sbit __at 0xb2 INT0;
300 __sbit __at 0xb3 P3_3;
301 __sbit __at 0xb3 INT1;
302 __sbit __at 0xb4 P3_4;
304 __sbit __at 0xb5 P3_5;
306 __sbit __at 0xb6 P3_6;
308 __sbit __at 0xb7 P3_7;
313 /* defining bits in SFR IEN1 */
314 __sbit __at 0xb8 EADC;
315 __sbit __at 0xb9 EX2;
316 __sbit __at 0xba EX3;
317 __sbit __at 0xbb EX4;
318 __sbit __at 0xbc EX5;
319 __sbit __at 0xbd EX6;
320 __sbit __at 0xbe SWDT;
321 __sbit __at 0xbf EXEN2;
325 /* defining bits in SFR IRCON */
326 __sbit __at 0xc0 IADC;
327 __sbit __at 0xc1 IEX2;
328 __sbit __at 0xc2 IEX3;
329 __sbit __at 0xc3 IEX4;
330 __sbit __at 0xc4 IEX5;
331 __sbit __at 0xc5 IEX6;
332 __sbit __at 0xc6 TF2;
333 __sbit __at 0xc7 EXF2;
337 /* defining bits in SFR T2CON */
338 __sbit __at 0xc8 T2I0;
339 __sbit __at 0xc9 T2I1;
340 __sbit __at 0xca T2CM;
341 __sbit __at 0xcb T2R0;
342 __sbit __at 0xcc T2R1;
343 __sbit __at 0xcd I2FR;
344 __sbit __at 0xce I3FR;
345 __sbit __at 0xcf T2PS;
349 /* defining bits in SFR PSW */
353 __sbit __at 0xd3 RS0;
354 __sbit __at 0xd4 RS1;
361 /* defining bits in SFR ADCON0 */
362 __sbit __at 0xd8 MX0;
363 __sbit __at 0xd9 MX1;
364 __sbit __at 0xda MX2;
365 __sbit __at 0xdb ADM;
366 __sbit __at 0xdc BSY;
367 __sbit __at 0xdd ADEX;
368 __sbit __at 0xde CLK;
373 /* defining bits in SFR ACC */
374 __sbit __at 0xe0 ACC_0;
375 __sbit __at 0xe1 ACC_1;
376 __sbit __at 0xe2 ACC_2;
377 __sbit __at 0xe3 ACC_3;
378 __sbit __at 0xe4 ACC_4;
379 __sbit __at 0xe5 ACC_5;
380 __sbit __at 0xe6 ACC_6;
381 __sbit __at 0xe7 ACC_7;
385 /* defining bits in SFR P4 */
386 __sbit __at 0xe8 P4_0;
387 __sbit __at 0xe8 ADST;
388 __sbit __at 0xe9 P4_1;
389 __sbit __at 0xe9 SCLK;
390 __sbit __at 0xea P4_2;
391 __sbit __at 0xea SRI;
392 __sbit __at 0xeb P4_3;
393 __sbit __at 0xeb STO;
394 __sbit __at 0xec P4_4;
395 __sbit __at 0xec SLS;
396 __sbit __at 0xed P4_5;
397 __sbit __at 0xed INT8;
398 __sbit __at 0xee P4_6;
399 __sbit __at 0xee TXDC;
400 __sbit __at 0xef P4_7;
401 __sbit __at 0xef RXDC;
405 /* defining bits in SFR B */
406 __sbit __at 0xf0 B_0;
407 __sbit __at 0xf1 B_1;
408 __sbit __at 0xf2 B_2;
409 __sbit __at 0xf3 B_3;
410 __sbit __at 0xf4 B_4;
411 __sbit __at 0xf5 B_5;
412 __sbit __at 0xf6 B_6;
413 __sbit __at 0xf7 B_7;
417 /* defining bits in SFR DIR5 */
418 __sbit __at 0xf8 P5_0;
419 __sbit __at 0xf9 P5_1;
420 __sbit __at 0xfa P5_2;
421 __sbit __at 0xfb P5_3;
422 __sbit __at 0xfc P5_4;
423 __sbit __at 0xfd P5_5;
424 __sbit __at 0xfe P5_6;
425 __sbit __at 0xff P5_7;
426 __sbit __at 0xf8 DIR5_0;
427 __sbit __at 0xf9 DIR5_1;
428 __sbit __at 0xfa DIR5_2;
429 __sbit __at 0xfb DIR5_3;
430 __sbit __at 0xfc DIR5_4;
431 __sbit __at 0xfd DIR5_5;
432 __sbit __at 0xfe DIR5_6;
433 __sbit __at 0xff DIR5_7;
435 #endif /* _REGC515C_H */