1 /*---------------------------------------------------------------------------
4 This file contains definitions for the builtin CAN-Bus Controller of
5 the Siemens c515c controller
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2.1 of the License, or (at your option) any later version.
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 ---------------------------------------------------------------------------*/
25 /* define CPU_CLK_10MHZ or CPU_CLK_8MHZ to select the right values for */
26 /* the bit timing registers */
30 /* address of can controller in xmem */
31 #define CAN_CTRL 0xf700
33 /* size of message buffer including 1 dummy byte at end */
34 #define CAN_MSG_SZ 0x10
36 /* register offset definitions */
49 #define MSG15MSK_0 0xc
50 #define MSG15MSK_1 0xd
51 #define MSG15MSK_2 0xe
52 #define MSG15MSK_3 0xf
54 /* register offsets in message buffer */
62 /* beginning of message data */
65 /* bits in cntr_x registers */
76 /* macros for setting and resetting above bits, see Siemens documentation */
77 #define MCR_BIT_SET(p,x) ((p) = (0xff & ~((x) >> 1)))
78 #define MCR_BIT_RES(p,x) ((p) = (0xff & ~(x)))
80 /* direction = transmit in mcfg */
81 #define DIR_TRANSMIT 0x8
83 /* constants for bit timing registers */
87 #define BT_1_125K 0x1c
89 #define BT_1_250K 0x1c
91 #define BT_1_500K 0x1c
98 #define BT_1_125K 0x1c
100 #define BT_1_250K 0x1c
101 #define BT_0_500K 0x0
102 #define BT_1_500K 0x2f
107 /* Control register bits */
116 /* status register bits */
127 typedef struct can_msg
136 unsigned char data_bytes[8];
140 __xdata __at CAN_CTRL struct
154 unsigned char msg15msk_0;
155 unsigned char msg15msk_1;
156 unsigned char msg15msk_2;
157 unsigned char msg15msk_3;
158 struct can_msg msgbufs[15];
161 /* Byte registers in numerical order */
167 __sfr __at 0x86 WDTREL;
168 __sfr __at 0x87 PCON;
169 __sfr __at 0x88 TCON;
170 __sfr __at 0x88 PCON1;
171 __sfr __at 0x89 TMOD;
177 __sfr __at 0x91 XPAGE;
178 __sfr __at 0x92 DPSEL;
179 __sfr __at 0x93 SSCCON;
182 __sfr __at 0x96 SSCMOD;
183 __sfr __at 0x98 SCON;
184 __sfr __at 0x99 SBUF;
185 __sfr __at 0x9A IEN2;
187 __sfr __at 0xA8 IEN0;
189 __sfr __at 0xAA SRELL;
191 __sfr __at 0xAC SCIEN;
193 __sfr __at 0xB1 SYSCON;
194 __sfr __at 0xB8 IEN1;
196 __sfr __at 0xBA SRELH;
197 __sfr __at 0xC0 IRCON;
198 __sfr __at 0xC1 CCEN;
199 __sfr __at 0xC2 CCL1;
200 __sfr __at 0xC3 CCH1;
201 __sfr __at 0xC4 CCL2;
202 __sfr __at 0xC5 CCH2;
203 __sfr __at 0xC6 CCL3;
204 __sfr __at 0xC7 CCH3;
205 __sfr __at 0xC8 T2CON;
206 __sfr __at 0xCA CRCL;
207 __sfr __at 0xCB CRCH;
211 __sfr __at 0xD8 ADCON0;
212 __sfr __at 0xD9 ADDATH;
213 __sfr __at 0xDA ADDATL;
215 __sfr __at 0xDC ADCON1;
220 __sfr __at 0xF8 DIR5;
224 /* defining bits in SFR P0 */
225 __sbit __at 0x80 P0_0;
226 __sbit __at 0x81 P0_1;
227 __sbit __at 0x82 P0_2;
228 __sbit __at 0x83 P0_3;
229 __sbit __at 0x84 P0_4;
230 __sbit __at 0x85 P0_5;
231 __sbit __at 0x86 P0_6;
232 __sbit __at 0x87 P0_7;
236 /* defining bits in SFR PCON1 */
237 __sbit __at 0x88 IT0;
238 __sbit __at 0x89 IE0;
239 __sbit __at 0x8a IT1;
240 __sbit __at 0x8b IE1;
241 __sbit __at 0x8c TR0;
242 __sbit __at 0x8d TF0;
243 __sbit __at 0x8e TR1;
244 __sbit __at 0x8f TF1;
245 __sbit __at 0x8f EWPD;
249 /* defining bits in SFR P1 */
250 __sbit __at 0x90 P1_0;
251 __sbit __at 0x90 INT3;
252 __sbit __at 0x91 P1_1;
253 __sbit __at 0x91 INT4;
254 __sbit __at 0x92 P1_2;
255 __sbit __at 0x92 INT5;
256 __sbit __at 0x93 P1_3;
257 __sbit __at 0x93 INT6;
258 __sbit __at 0x94 P1_4;
259 __sbit __at 0x94 INT2;
260 __sbit __at 0x95 P1_5;
261 __sbit __at 0x95 T2EX;
262 __sbit __at 0x96 P1_6;
263 __sbit __at 0x96 CLKOUT;
264 __sbit __at 0x97 P1_7;
269 /* defining bits in SFR SCON */
272 __sbit __at 0x9a RB8;
273 __sbit __at 0x9b TB8;
274 __sbit __at 0x9c REN;
275 __sbit __at 0x9d SM2;
276 __sbit __at 0x9e SM1;
277 __sbit __at 0x9f SM0;
281 /* defining bits in SFR P2 */
282 __sbit __at 0xa0 P2_0;
283 __sbit __at 0xa1 P2_1;
284 __sbit __at 0xa2 P2_2;
285 __sbit __at 0xa3 P2_3;
286 __sbit __at 0xa4 P2_4;
287 __sbit __at 0xa5 P2_5;
288 __sbit __at 0xa6 P2_6;
289 __sbit __at 0xa7 P2_7;
293 /* defining bits in SFR IEN0 */
294 __sbit __at 0xa8 EX0;
295 __sbit __at 0xa9 ET0;
296 __sbit __at 0xaa EX1;
297 __sbit __at 0xab ET1;
299 __sbit __at 0xad ET2;
300 __sbit __at 0xae WDT;
305 /* defining bits in SFR P3 */
306 __sbit __at 0xb0 P3_0;
307 __sbit __at 0xb0 RXD;
308 __sbit __at 0xb1 P3_1;
309 __sbit __at 0xb1 TXD;
310 __sbit __at 0xb2 P3_2;
311 __sbit __at 0xb2 INT0;
312 __sbit __at 0xb3 P3_3;
313 __sbit __at 0xb3 INT1;
314 __sbit __at 0xb4 P3_4;
316 __sbit __at 0xb5 P3_5;
318 __sbit __at 0xb6 P3_6;
320 __sbit __at 0xb7 P3_7;
325 /* defining bits in SFR IEN1 */
326 __sbit __at 0xb8 EADC;
327 __sbit __at 0xb9 EX2;
328 __sbit __at 0xba EX3;
329 __sbit __at 0xbb EX4;
330 __sbit __at 0xbc EX5;
331 __sbit __at 0xbd EX6;
332 __sbit __at 0xbe SWDT;
333 __sbit __at 0xbf EXEN2;
337 /* defining bits in SFR IRCON */
338 __sbit __at 0xc0 IADC;
339 __sbit __at 0xc1 IEX2;
340 __sbit __at 0xc2 IEX3;
341 __sbit __at 0xc3 IEX4;
342 __sbit __at 0xc4 IEX5;
343 __sbit __at 0xc5 IEX6;
344 __sbit __at 0xc6 TF2;
345 __sbit __at 0xc7 EXF2;
349 /* defining bits in SFR T2CON */
350 __sbit __at 0xc8 T2I0;
351 __sbit __at 0xc9 T2I1;
352 __sbit __at 0xca T2CM;
353 __sbit __at 0xcb T2R0;
354 __sbit __at 0xcc T2R1;
355 __sbit __at 0xcd I2FR;
356 __sbit __at 0xce I3FR;
357 __sbit __at 0xcf T2PS;
361 /* defining bits in SFR PSW */
365 __sbit __at 0xd3 RS0;
366 __sbit __at 0xd4 RS1;
373 /* defining bits in SFR ADCON0 */
374 __sbit __at 0xd8 MX0;
375 __sbit __at 0xd9 MX1;
376 __sbit __at 0xda MX2;
377 __sbit __at 0xdb ADM;
378 __sbit __at 0xdc BSY;
379 __sbit __at 0xdd ADEX;
380 __sbit __at 0xde CLK;
385 /* defining bits in SFR ACC */
386 __sbit __at 0xe0 ACC_0;
387 __sbit __at 0xe1 ACC_1;
388 __sbit __at 0xe2 ACC_2;
389 __sbit __at 0xe3 ACC_3;
390 __sbit __at 0xe4 ACC_4;
391 __sbit __at 0xe5 ACC_5;
392 __sbit __at 0xe6 ACC_6;
393 __sbit __at 0xe7 ACC_7;
397 /* defining bits in SFR P4 */
398 __sbit __at 0xe8 P4_0;
399 __sbit __at 0xe8 ADST;
400 __sbit __at 0xe9 P4_1;
401 __sbit __at 0xe9 SCLK;
402 __sbit __at 0xea P4_2;
403 __sbit __at 0xea SRI;
404 __sbit __at 0xeb P4_3;
405 __sbit __at 0xeb STO;
406 __sbit __at 0xec P4_4;
407 __sbit __at 0xec SLS;
408 __sbit __at 0xed P4_5;
409 __sbit __at 0xed INT8;
410 __sbit __at 0xee P4_6;
411 __sbit __at 0xee TXDC;
412 __sbit __at 0xef P4_7;
413 __sbit __at 0xef RXDC;
417 /* defining bits in SFR B */
418 __sbit __at 0xf0 B_0;
419 __sbit __at 0xf1 B_1;
420 __sbit __at 0xf2 B_2;
421 __sbit __at 0xf3 B_3;
422 __sbit __at 0xf4 B_4;
423 __sbit __at 0xf5 B_5;
424 __sbit __at 0xf6 B_6;
425 __sbit __at 0xf7 B_7;
429 /* defining bits in SFR DIR5 */
430 __sbit __at 0xf8 P5_0;
431 __sbit __at 0xf9 P5_1;
432 __sbit __at 0xfa P5_2;
433 __sbit __at 0xfb P5_3;
434 __sbit __at 0xfc P5_4;
435 __sbit __at 0xfd P5_5;
436 __sbit __at 0xfe P5_6;
437 __sbit __at 0xff P5_7;
438 __sbit __at 0xf8 DIR5_0;
439 __sbit __at 0xf9 DIR5_1;
440 __sbit __at 0xfa DIR5_2;
441 __sbit __at 0xfb DIR5_3;
442 __sbit __at 0xfc DIR5_4;
443 __sbit __at 0xfd DIR5_5;
444 __sbit __at 0xfe DIR5_6;
445 __sbit __at 0xff DIR5_7;
447 #endif /* _REGC515C_H */