1 /*--------------------------------------------------------------------------
4 This header allows to use the microcontroler NXP (formerly Philips) p89v66x
5 where x stands for 0,2,4.
7 Copyright (c) 2008 Gudjon I. Gudjonsson <gudjon AT gudjon.org>
9 This library is free software; you can redistribute it and/or
10 modify it under the terms of the GNU Lesser General Public
11 License as published by the Free Software Foundation; either
12 version 2.1 of the License, or (at your option) any later version.
14 This library is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the GNU
17 Lesser General Public License for more details.
19 You should have received a copy of the GNU Lesser General Public
20 License along with this library; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA02111-1307 USA
23 The registered are ordered in the same way as in the NXP data sheet:
24 http://www.standardics.nxp.com/products/80c51/datasheet/p89v660.p89v662.p89v664.pdf
26 --------------------------------------------------------------------------*/
32 SFR(ACC, 0xE0); // Accumulator
41 SFR(AUXR, 0x8E); // Auxiliary
44 SFR(AUXR1, 0xA2); // Auxiliary 1
49 SFR(B, 0xF0); // B register
58 SFR(CCAP0H, 0xFA); // Module 0 Capture High
59 SFR(CCAP1H, 0xFB); // Module 1 Capture High
60 SFR(CCAP2H, 0xFC); // Module 2 Capture High
61 SFR(CCAP3H, 0xFD); // Module 3 Capture High
62 SFR(CCAP4H, 0xFE); // Module 4 Capture High
63 SFR(CCAP0L, 0xEA); // Module 0 Capture Low
64 SFR(CCAP1L, 0xEB); // Module 1 Capture Low
65 SFR(CCAP2L, 0xEC); // Module 2 Capture Low
66 SFR(CCAP3L, 0xED); // Module 3 Capture Low
67 SFR(CCAP4L, 0xEE); // Module 4 Capture Low
68 SFR(CCAPM0, 0xC2); // Module 0 Mode
76 SFR(CCAPM1, 0xC3); // Module 1 Mode
84 SFR(CCAPM2, 0xC4); // Module 2 Mode
92 SFR(CCAPM3, 0xC5); // Module 3 Mode
100 SFR(CCAPM4, 0xC6); // Module 4 Mode
115 SFR(CCON, 0xC0); // PCA Counter Control
123 SFR(CH, 0xF9); // PCA Counter High
124 SFR(CL, 0xE9); // PCA Counter Low
125 SFR(CMOD, 0xC1); // PCA Counter Mode
131 SFR(DPH, 0x83); // Data Pointer High
132 SFR(DPL, 0x82); // Data Pointer Low
133 SFR(IEN0, 0xA8); // Interrupt Enable 0
142 SFR(IEN1, 0xE8); // Interrupt Enable 1
146 SFR(IP0, 0xB8); // Interrupt Priority 0
155 SFR(IP0H, 0xB7); // Interrupt Priority 0 High
164 SFR(IP1, 0x91); // Interrupt Priority 1
167 SFR(IP1H, 0x92); // Interrupt Priority 1 High
170 SFR(P0, 0x80); // Port 0
187 SFR(P1, 0x90); // Port 1
188 SBIT(T1_CEX4, 0x90, 7);
190 SBIT(T0_CEX3, 0x90, 6);
204 SFR(P2, 0xA0); // Port 2
221 SFR(P3, 0xB0); // Port 3
238 SFR(P4, 0xA1); // Port 3
249 SFR(PCON, 0x87); // Power Control
257 SFR(PSW, 0xD0); // Program Status Word
266 SFR(RCAP2H, 0xCB); // Timer 2 Capture High
267 SFR(RCAP2L, 0xCA); // Timer 2 Capture Low
268 SFR(S0CON, 0x98); // Serial Control
269 SBIT(SM0_FE,0x98, 7);
277 SFR(S0BUF, 0x99); // Serial Data Buffer
278 SFR(SADDR, 0xA9); // I2C Slave Address
279 SFR(SADEN, 0xB9); // I2C Slave Address Mask
280 SFR(SPCR, 0xD5); // SPI Control Register
289 /* SBIT(SPIE, 0x80, 7); // SPCR is not bit addressable, not yet at least, according to the manual.
296 SBIT(SPR0, 0x80, 0);*/
297 SFR(SPSR, 0xAA); // SPI Configuration Register
300 SFR(SPDAT, 0x86); // SPI Data
301 SFR(SP, 0x81); // Stack Pointer
302 SFR(S1DAT, 0xDA); // I2C Serial 1 Data
303 SFR(S1ADR, 0xDB); // I2C Serial 1 Address
312 SFR(S1STA, 0xD9); // I2C Serial 1 Status
317 #define SC0 0x08 // Only write 0 to the lowest three bits
318 SFR(S1CON, 0xD8); // I2C Serial 1 Control
327 SFR(S2DAT, 0xE2); // I2C Serial 1 Data
328 SFR(S2ADR, 0xE3); // I2C Serial 1 Address
337 SFR(S2STA, 0xE1); // I2C Serial 1 Status
342 #define SC20 0x08 // Only write 0 to the lowest three bits
343 SFR(S2CON, 0xF8); // I2C Serial 1 Control
345 SBIT(ENS21, 0xF8, 6);
352 SFR(TCON, 0x88); // Timer Control
361 SFR(T2CON, 0xC8); // Timer 2 Control
366 SBIT(EXEN2, 0xC8, 3);
369 SBIT(CP_RL2, 0xC8, 0);
370 SFR(T2MOD, 0xC9); // Timer 2 Mode Control
374 SFR(TH0, 0x8C); // Timer High 0
375 SFR(TH1, 0x8D); // Timer High 1
376 SFR(TH2, 0xCD); // Timer High 2
377 SFR(TL0, 0x8A); // Timer Low 0
378 SFR(TL1, 0x8B); // Timer Low 1
379 SFR(TL2, 0xCC); // Timer Low 2
380 SFR(TMOD, 0x89); // Timer Mode
389 SFR(WDTRST, 0xA6); // Watchdog Timer Reset
391 #endif //__P89V66X_H__