1 /*-------------------------------------------------------------------------
2 Register Declarations for the Philips P89V51RD2 Processor
4 Written By - Jesus Calvino-Fraga / jesusc at ece.ubc.ca (June 2005)
6 This library is free software; you can redistribute it and/or
7 modify it under the terms of the GNU Lesser General Public
8 License as published by the Free Software Foundation; either
9 version 2.1 of the License, or (at your option) any later version.
11 This library is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 Lesser General Public License for more details.
16 You should have received a copy of the GNU Lesser General Public
17 License along with this library; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 In other words, you are welcome to use, share and improve this program.
21 You are forbidden to forbid anyone else to use, share and improve
22 what you give them. Help stamp out software-hoarding!
23 -------------------------------------------------------------------------*/
25 #ifndef REG_P89V51RD2_H
26 #define REG_P89V51RD2_H
28 #include <8052.h> // Load definitions for the 8052
34 // Define P89V51RD2 specific registers only
36 __sfr __at (0x8E) AUXR; //Auxiliary function register (Reset value 0x00).
37 #define EXTRAM 0x02 //'0'=uses internal XRAM.
38 #define AO 0x01 //'1'=Disables ALE generation.
40 __sfr __at (0xA2) AUXR1; //Auxiliary function register 1 (Reset value 0x00).
41 #define GF2 0x08 //General purpose user-defined flag.
42 #define DPS 0x01 //Data pointer select.
44 __sfr __at (0xFA) CCAP0H; //Module 0 Capture HIGH.
45 __sfr __at (0xFB) CCAP1H; //Module 1 Capture HIGH.
46 __sfr __at (0xFC) CCAP2H; //Module 2 Capture HIGH.
47 __sfr __at (0xFD) CCAP3H; //Module 3 Capture HIGH.
48 __sfr __at (0xFE) CCAP4H; //Module 4 Capture HIGH.
49 __sfr __at (0xEA) CCAP0L; //Module 0 Capture LOW.
50 __sfr __at (0xEB) CCAP1L; //Module 1 Capture LOW.
51 __sfr __at (0xEC) CCAP2L; //Module 2 Capture LOW.
52 __sfr __at (0xED) CCAP3L; //Module 3 Capture LOW.
53 __sfr __at (0xEE) CCAP4L; //Module 4 Capture LOW.
55 __sfr __at (0xDA) CCAPM0; //Module 0 Mode.
56 __sfr __at (0xDB) CCAPM1; //Module 1 Mode.
57 __sfr __at (0xDC) CCAPM2; //Module 2 Mode.
58 __sfr __at (0xDD) CCAPM3; //Module 3 Mode.
59 __sfr __at (0xDE) CCAPM4; //Module 4 Mode.
60 //The preceding five registers have the following bits:
61 #define ECOM 0x40 //Enable Comparator.
62 #define CAPP 0x20 //1=enables positive edge capture.
63 #define CAPN 0x10 //1=enables negative edge capture.
64 #define MAT 0x08 //When counter matches sets CCF_n bit causing and interrupt.
65 #define TOG 0x04 //Toggle output on match.
66 #define PWM 0x02 //Pulse width modulation mode.
67 #define ECCF 0x01 //Enable CCF interrupt.
69 __sfr __at (0xD8) CCON; //PCA Counter Control (Reset value 0x00)
70 __sbit __at (0xDF) CF; //PCA Counter overflow flag.
71 __sbit __at (0xDE) CR ; //PCA Counter Run Control Bit. 1=counter on. 0=counter off.
72 __sbit __at (0xDC) CCF4;//PCA Module 4 Interrupt Flag.
73 __sbit __at (0xDB) CCF3;//PCA Module 3 Interrupt Flag.
74 __sbit __at (0xDA) CCF2;//PCA Module 2 Interrupt Flag.
75 __sbit __at (0xD9) CCF1;//PCA Module 1 Interrupt Flag.
76 __sbit __at (0xD8) CCF0;//PCA Module 0 Interrupt Flag.
78 __sfr __at (0xF9) CH; //PCA Counter HIGH.
79 __sfr __at (0xE9) CL; //PCA Counter LOW.
81 __sfr __at (0xD9) CMOD; //PCA Counter Mode.
82 #define CIDL 0x80 //CIDL=0 program the PCA counter to work during idle mode.
83 #define WDTE 0x40 //Watchdog Timer Enable.
84 #define CPS1 0x04 //PCA Count Pulse Select bit 1.
85 #define CPS0 0x02 //PCA Count Pulse Select bit 0.
86 //00=Internal clock, Fosc/6
87 //01=Internal clock, Fosc/6
89 //11=External clock at ECI/P1.2 pin (max rate=Fosc/4)
90 #define ECF 0x01 //PCA Enable Counter Overflow Interrupt.
92 __sfr __at (0xB6) FST; //Flash Status Register.
96 __sfr __at (0xB1) FCF; //Flash program memory bank selection.
100 //Attention IEN0 is the same as register IE found in <8051.h> only bit EC added here.
101 __sfr __at (0xA8) IEN0; //Interrupt Enable 1.
102 __sbit __at (0xAE) EC; //PCA Interrupt Enable bit.
104 __sfr __at (0xE8) IEN1; //Interrupt Enable 1
105 __sbit __at (0xEB) EBO; //Brown-out Interrupt Enable. (Vector is 0x00b4).
107 //Attention IP0 is the same as register IP found in <8051.h> only bit PPC added here.
108 __sfr __at (0xB8) IP0; //Interrupt Priority 0 HIGH.
109 __sbit __at (0xBE) PPC; //PCA Interrupt Priority low bit.
111 __sfr __at (0xB7) IP0H; //Interrupt Priority 0 HIGH
112 #define PPCH 0x40 //PCA Interrupt Priority High Bit.
113 #define PT2H 0x20 //Timer 2 Interrupt Interrupt Priority High Bit.
114 #define PSH 0x10 //Serial Port Interrupt Priority High Bit.
115 #define PT1H 0x08 //Timer 1 Interrupt Priority High Bit.
116 #define PX1H 0x04 //External Interrupt 1 Priority High Bit.
117 #define PT0H 0x02 //Timer 0 Interrupt Priority High Bit.
118 #define PX0H 0x01 //External Interrupt 0 Priority High Bit.
120 __sfr __at (0xF8) IP1; //Interrupt Priority 1.
121 __sbit __at (0xFB) PBO; //Brown-out Interrupt Priority Bit.
123 __sfr __at (0xF7) IP1H; //Interrupt Priority 1 HIGH.
124 #define PBOH 0x08 //Brown-out Interrupt Priority High Bit.
126 __sfr __at (0xA9) SADDR; //Serial Port Address Register.
127 __sfr __at (0xB9) SADEN; //Serial Port Address Enable.
129 __sfr __at (0xD5) SPCR; //SPI Control Register (Reset value 00000000B).
130 __sfr __at (0xD5) SPCTL; //SPI Control Register (This name appears also in the datasheet).
131 #define SPIE 0x80 //If both SPIE and ES are set to one, SPI interrupts are enabled.
132 #define SPEN 0x40 //SPI enable bit. When set enables SPI.
133 #define SPE 0x40 //Same as above. This name appears also in the manual :-(
134 #define DORD 0x20 //Data trans. order. 0=MSB first; 1=LSB first.
135 #define MSTR 0x10 //1=master mode. 0=slave mode.
136 #define CPOL 0x08 //1=SCK is high when idle (active low), 0=SCK is low when idle (active high).
137 #define CPHA 0x04 //1=shift triggered on the trailing edge of SCK. 0=shift trig. on leading edge.
138 #define SPR1 0x02 //SPI Clork Rate select bit 1.
139 #define SPR0 0x01 //SPI Clork Rate select bit 0.
145 __sfr __at (0xAA) SPSR; //SPI Configuration Register (Reset value 00000000B).
146 __sfr __at (0xAA) SPCFG; //SPI Configuration Register (This name appears also in the datasheet).
147 #define SPIF 0x80 //SPI interrupt flag.
148 #define SPWCOL 0x40 //Write collision Flag.
150 __sfr __at (0x86) SPDR; //SPI Data
151 __sfr __at (0x86) SPDAT; //SPI Data (This name appears also in the datasheet).
153 __sfr __at (0xC0) WDTC; //Watchdog Timer Control (Reset value 0x00).
154 #define WDOUT 0x10 //Watchdog output enable.
155 #define WDRE 0x08 //Watchdog timer reset enable.
156 #define WDTS 0x04 //Watchdog timer reset flag.
157 #define WDT 0x02 //Watchdog timer refresh.
158 #define SWDT 0x01 //Start watchdog timer.
160 __sfr __at (0x85) WDTD; //Watchdog Timer Data/Reload.
162 __sfr __at (0xC9) T2MOD; //Timer 2 mode control
163 #define DCEN 0x01 //Down count enable bit
164 #define T2OE 0x02 //Timer 2 Output Enable bit.
165 #define ENT2 0x20 //No description???
167 #endif /*REG_P89V51RD2_H*/