2 * This header defines register addresses for the Philips P89LPC938
3 * microcontroller for use with the SDCC compiler.
5 * Copyright © 2007 Kyle Guinn <elyk03@gmail.com>
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 3 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this program. If not, see
19 * <http://www.gnu.org/licenses/>. */
24 /* SFR byte addresses */
25 __sfr __at (0x80) P0; /* Port 0 */
26 __sfr __at (0x81) SP; /* Stack pointer */
27 __sfr __at (0x82) DPL; /* Data pointer low */
28 __sfr __at (0x83) DPH; /* Data pointer high */
29 __sfr __at (0x84) P0M1; /* Port 0 output mode 1 */
30 __sfr __at (0x85) P0M2; /* Port 0 output mode 2 */
31 __sfr __at (0x86) KBMASK; /* Keypad interrupt mask register */
32 __sfr __at (0x87) PCON; /* Power control register */
33 __sfr __at (0x88) TCON; /* Timer 0 and 1 control */
34 __sfr __at (0x89) TMOD; /* Timer 0 and 1 mode */
35 __sfr __at (0x8A) TL0; /* Timer 0 low */
36 __sfr __at (0x8B) TL1; /* Timer 1 low */
37 __sfr __at (0x8C) TH0; /* Timer 0 high */
38 __sfr __at (0x8D) TH1; /* Timer 1 high */
39 __sfr __at (0x8F) TAMOD; /* Timer 0 and 1 auxiliary mode */
40 __sfr __at (0x90) P1; /* Port 1 */
41 __sfr __at (0x91) P1M1; /* Port 1 output mode 1 */
42 __sfr __at (0x92) P1M2; /* Port 1 output mode 2 */
43 __sfr __at (0x93) KBPATN; /* Keypad pattern register */
44 __sfr __at (0x94) KBCON; /* Keypad control register */
45 __sfr __at (0x95) DIVM; /* CPU clock divide-by-M control */
46 __sfr __at (0x96) TRIM; /* Internal oscillator trim register */
47 __sfr __at (0x97) AD0CON; /* ADC0 control register */
48 __sfr __at (0x98) SCON; /* Serial port control */
49 __sfr __at (0x99) SBUF; /* Serial port data buffer register */
50 __sfr __at (0xA0) P2; /* Port 2 */
51 __sfr __at (0xA1) AD0MODB; /* ADC0 mode register B */
52 __sfr __at (0xA2) AUXR1; /* Auxiliary function register */
53 __sfr __at (0xA3) AD0INS; /* ADC0 input select */
54 __sfr __at (0xA4) P2M1; /* Port 2 output mode 1 */
55 __sfr __at (0xA5) P2M2; /* Port 2 output mode 2 */
56 __sfr __at (0xA7) WDCON; /* Watchdog control register */
57 __sfr __at (0xA8) IEN0; /* Interrupt enable 0 */
58 __sfr __at (0xA9) SADDR; /* Serial port address register */
59 __sfr __at (0xAA) ICRAL; /* Input capture A register low */
60 __sfr __at (0xAB) ICRAH; /* Input capture A register high */
61 __sfr __at (0xAC) CMP1; /* Comparator 1 control register */
62 __sfr __at (0xAD) CMP2; /* Comparator 2 control register */
63 __sfr __at (0xAE) ICRBL; /* Input capture B register low */
64 __sfr __at (0xAF) ICRBH; /* Input capture B register high */
65 __sfr __at (0xB0) P3; /* Port 3 */
66 __sfr __at (0xB1) P3M1; /* Port 3 output mode 1 */
67 __sfr __at (0xB2) P3M2; /* Port 3 output mode 2 */
68 __sfr __at (0xB5) PCONA; /* Power control register A */
69 __sfr __at (0xB7) IP0H; /* Interrupt priority 0 high */
70 __sfr __at (0xB8) IP0; /* Interrupt priority 0 */
71 __sfr __at (0xB9) SADEN; /* Serial port address enable */
72 __sfr __at (0xBA) SSTAT; /* Serial port extended status register */
73 __sfr __at (0xBD) BRGCON; /* Baud rate generator control */
74 __sfr __at (0xBE) BRGR0; /* Baud rate generator rate low */
75 __sfr __at (0xBF) BRGR1; /* Baud rate generator rate high */
76 __sfr __at (0xC0) AD0MODA; /* ADC0 mode register A */
77 __sfr __at (0xC1) WDL; /* Watchdog load */
78 __sfr __at (0xC2) WFEED1; /* Watchdog feed 1 */
79 __sfr __at (0xC3) WFEED2; /* Watchdog feed 2 */
80 __sfr __at (0xC8) TCR20; /* CCU control register 0 */
81 __sfr __at (0xC9) TICR2; /* CCU interrupt control register */
82 __sfr __at (0xCA) TPCR2L; /* Prescaler control register low */
83 __sfr __at (0xCB) TPCR2H; /* Prescaler control register high */
84 __sfr __at (0xCC) TL2; /* CCU timer low */
85 __sfr __at (0xCD) TH2; /* CCU timer high */
86 __sfr __at (0xCE) TOR2L; /* CCU reload register low */
87 __sfr __at (0xCF) TOR2H; /* CCU reload register high */
88 __sfr __at (0xD0) PSW; /* Program status word */
89 __sfr __at (0xD1) RTCCON; /* RTC control */
90 __sfr __at (0xD2) RTCH; /* RTC register high */
91 __sfr __at (0xD3) RTCL; /* RTC register low */
92 __sfr __at (0xD5) IEN2; /* Interrupt enable 2 */
93 __sfr __at (0xD6) IP2; /* Interrupt priority 2 */
94 __sfr __at (0xD7) IP2H; /* Interrupt priority 2 high */
95 __sfr __at (0xD8) I2CON; /* I²C control register */
96 __sfr __at (0xD9) I2STAT; /* I²C status register */
97 __sfr __at (0xDA) I2DAT; /* I²C data register */
98 __sfr __at (0xDB) I2ADR; /* I²C slave address register */
99 __sfr __at (0xDC) I2SCLL; /* Serial clock generator low/
100 * SCL duty cycle register low */
101 __sfr __at (0xDD) I2SCLH; /* Serial clock generator high/
102 * SCL duty cycle register high */
103 __sfr __at (0xDE) TISE2; /* CCU interrupt status encode register */
104 __sfr __at (0xDF) RSTSRC; /* Reset source register */
105 __sfr __at (0xE0) ACC; /* Accumulator */
106 __sfr __at (0xE1) SPSTAT; /* SPI status register */
107 __sfr __at (0xE2) SPCTL; /* SPI control register */
108 __sfr __at (0xE3) SPDAT; /* SPI data register */
109 __sfr __at (0xE4) FMCON; /* Program Flash control (Read)/
110 * Program Flash control (Write) */
111 __sfr __at (0xE5) FMDATA; /* Program Flash data */
112 __sfr __at (0xE6) FMADRL; /* Program Flash address low */
113 __sfr __at (0xE7) FMADRH; /* Program Flash address high */
114 __sfr __at (0xE8) IEN1; /* Interrupt enable 1 */
115 __sfr __at (0xE9) TIFR2; /* CCU interrupt flag register */
116 __sfr __at (0xEA) CCCRA; /* Capture compare A control register */
117 __sfr __at (0xEB) CCCRB; /* Capture compare B control register */
118 __sfr __at (0xEC) CCCRC; /* Capture compare C control register */
119 __sfr __at (0xED) CCCRD; /* Capture compare D control register */
120 __sfr __at (0xEE) OCRAL; /* Output compare A register low */
121 __sfr __at (0xEF) OCRAH; /* Output compare A register high */
122 __sfr __at (0xF0) B; /* B register */
123 __sfr __at (0xF1) DEECON; /* Data EEPROM control register */
124 __sfr __at (0xF2) DEEDAT; /* Data EEPROM data register */
125 __sfr __at (0xF3) DEEADR; /* Data EEPROM address register */
126 __sfr __at (0xF6) PT0AD; /* Port 0 digital input disable */
127 __sfr __at (0xF7) IP1H; /* Interrupt priority 1 high */
128 __sfr __at (0xF8) IP1; /* Interrupt priority 1 */
129 __sfr __at (0xF9) TCR21; /* CCU control register 1 */
130 __sfr __at (0xFA) OCRBL; /* Output compare B register low */
131 __sfr __at (0xFB) OCRBH; /* Output compare B register high */
132 __sfr __at (0xFC) OCRCL; /* Output compare C register low */
133 __sfr __at (0xFD) OCRCH; /* Output compare C register high */
134 __sfr __at (0xFE) OCRDL; /* Output compare D register low */
135 __sfr __at (0xFF) OCRDH; /* Output compare D register high */
137 /* 16-bit SFRs (duplicates of above) */
138 __sfr16 __at (0x8382) DPTR; /* Data pointer */
139 __sfr16 __at (0x8C8A) TMR0; /* Timer 0 count */
140 __sfr16 __at (0x8D8B) TMR1; /* Timer 1 count */
141 __sfr16 __at (0xABAA) ICRA; /* Input capture A register */
142 __sfr16 __at (0xAFAE) ICRB; /* Input capture B register */
143 __sfr16 __at (0xBFBE) BRGR; /* Baud rate generator */
144 __sfr16 __at (0xCBCA) TPCR2; /* Prescaler control register */
145 __sfr16 __at (0xCDCC) TMR2; /* Timer 2 count */
146 __sfr16 __at (0xCFCE) TOR2; /* CCU reload register */
147 __sfr16 __at (0xD2D3) RTC; /* RTC register */
148 __sfr16 __at (0xDDDC) I2SCL; /* Serial clock generator/
149 * SCL duty cycle register */
150 __sfr16 __at (0xE7E6) FMADR; /* Program Flash address */
151 __sfr16 __at (0xEFEE) OCRA; /* Output compare A register */
152 __sfr16 __at (0xFBFA) OCRB; /* Output compare B register */
153 __sfr16 __at (0xFDFC) OCRC; /* Output compare C register */
154 __sfr16 __at (0xFFFE) OCRD; /* Output compare D register */
156 /* "Extended SFRs" (logically in __xdata memory space) */
157 #define BNDSTA0 (*(__xdata volatile unsigned char*)0xFFED) /* ADC0 boundary status register */
158 #define ADC0LBND (*(__xdata volatile unsigned char*)0xFFEE) /* ADC0 low_boundary register (MSB) */
159 #define ADC0HBND (*(__xdata volatile unsigned char*)0xFFEF) /* ADC0 high_boundary register, left (MSB) */
160 #define AD0DAT7R (*(__xdata volatile unsigned char*)0xFFF0) /* ADC0 data register 7, right (LSB) */
161 #define AD0DAT7L (*(__xdata volatile unsigned char*)0xFFF1) /* ADC0 data register 7, left (MSB) */
162 #define AD0DAT6R (*(__xdata volatile unsigned char*)0xFFF2) /* ADC0 data register 6, right (LSB) */
163 #define AD0DAT6L (*(__xdata volatile unsigned char*)0xFFF3) /* ADC0 data register 6, left (MSB) */
164 #define AD0DAT5R (*(__xdata volatile unsigned char*)0xFFF4) /* ADC0 data register 5, right (LSB) */
165 #define AD0DAT5L (*(__xdata volatile unsigned char*)0xFFF5) /* ADC0 data register 5, left (MSB) */
166 #define AD0DAT4R (*(__xdata volatile unsigned char*)0xFFF6) /* ADC0 data register 4, right (LSB) */
167 #define AD0DAT4L (*(__xdata volatile unsigned char*)0xFFF7) /* ADC0 data register 4, left (MSB) */
168 #define AD0DAT3R (*(__xdata volatile unsigned char*)0xFFF8) /* ADC0 data register 3, right (LSB) */
169 #define AD0DAT3L (*(__xdata volatile unsigned char*)0xFFF9) /* ADC0 data register 3, left (MSB) */
170 #define AD0DAT2R (*(__xdata volatile unsigned char*)0xFFFA) /* ADC0 data register 2, right (LSB) */
171 #define AD0DAT2L (*(__xdata volatile unsigned char*)0xFFFB) /* ADC0 data register 2, left (MSB) */
172 #define AD0DAT1R (*(__xdata volatile unsigned char*)0xFFFC) /* ADC0 data register 1, right (LSB) */
173 #define AD0DAT1L (*(__xdata volatile unsigned char*)0xFFFD) /* ADC0 data register 1, left (MSB) */
174 #define AD0DAT0R (*(__xdata volatile unsigned char*)0xFFFE) /* ADC0 data register 0, right (LSB) */
175 #define AD0DAT0L (*(__xdata volatile unsigned char*)0xFFFF) /* ADC0 data register 0, left (MSB) */
177 /* Special Function Bits */
179 __sbit __at (0x80) P0_0;
180 __sbit __at (0x81) P0_1;
181 __sbit __at (0x82) P0_2;
182 __sbit __at (0x83) P0_3;
183 __sbit __at (0x84) P0_4;
184 __sbit __at (0x85) P0_5;
185 __sbit __at (0x86) P0_6;
186 __sbit __at (0x87) P0_7;
187 /*#define CMP2 P0_0*/ /* Removed: Name conflicts with SFR 0xAD */
199 /*#define CMP1 P0_6*/ /* Removed: Name conflicts with SFR 0xAC */
205 __sbit __at (0x88) TCON_0;
206 __sbit __at (0x89) TCON_1;
207 __sbit __at (0x8A) TCON_2;
208 __sbit __at (0x8B) TCON_3;
209 __sbit __at (0x8C) TCON_4;
210 __sbit __at (0x8D) TCON_5;
211 __sbit __at (0x8E) TCON_6;
212 __sbit __at (0x8F) TCON_7;
223 __sbit __at (0x90) P1_0;
224 __sbit __at (0x91) P1_1;
225 __sbit __at (0x92) P1_2;
226 __sbit __at (0x93) P1_3;
227 __sbit __at (0x94) P1_4;
228 __sbit __at (0x95) P1_5;
229 __sbit __at (0x96) P1_6;
230 __sbit __at (0x97) P1_7;
243 __sbit __at (0x98) SCON_0;
244 __sbit __at (0x99) SCON_1;
245 __sbit __at (0x9A) SCON_2;
246 __sbit __at (0x9B) SCON_3;
247 __sbit __at (0x9C) SCON_4;
248 __sbit __at (0x9D) SCON_5;
249 __sbit __at (0x9E) SCON_6;
250 __sbit __at (0x9F) SCON_7;
262 __sbit __at (0xA0) P2_0;
263 __sbit __at (0xA1) P2_1;
264 __sbit __at (0xA2) P2_2;
265 __sbit __at (0xA3) P2_3;
266 __sbit __at (0xA4) P2_4;
267 __sbit __at (0xA5) P2_5;
268 __sbit __at (0xA6) P2_6;
269 __sbit __at (0xA7) P2_7;
280 __sbit __at (0xA8) IEN0_0;
281 __sbit __at (0xA9) IEN0_1;
282 __sbit __at (0xAA) IEN0_2;
283 __sbit __at (0xAB) IEN0_3;
284 __sbit __at (0xAC) IEN0_4;
285 __sbit __at (0xAD) IEN0_5;
286 __sbit __at (0xAE) IEN0_6;
287 __sbit __at (0xAF) IEN0_7;
299 __sbit __at (0xB0) P3_0;
300 __sbit __at (0xB1) P3_1;
301 __sbit __at (0xB2) P3_2;
302 __sbit __at (0xB3) P3_3;
303 __sbit __at (0xB4) P3_4;
304 __sbit __at (0xB5) P3_5;
305 __sbit __at (0xB6) P3_6;
306 __sbit __at (0xB7) P3_7;
311 __sbit __at (0xB8) IP0_0;
312 __sbit __at (0xB9) IP0_1;
313 __sbit __at (0xBA) IP0_2;
314 __sbit __at (0xBB) IP0_3;
315 __sbit __at (0xBC) IP0_4;
316 __sbit __at (0xBD) IP0_5;
317 __sbit __at (0xBE) IP0_6;
318 __sbit __at (0xBF) IP0_7;
329 __sbit __at (0xC0) AD0MODA_0;
330 __sbit __at (0xC1) AD0MODA_1;
331 __sbit __at (0xC2) AD0MODA_2;
332 __sbit __at (0xC3) AD0MODA_3;
333 __sbit __at (0xC4) AD0MODA_4;
334 __sbit __at (0xC5) AD0MODA_5;
335 __sbit __at (0xC6) AD0MODA_6;
336 __sbit __at (0xC7) AD0MODA_7;
337 #define SCAN0 AD0MODA_4
338 #define SCC0 AD0MODA_5
339 #define BURST0 AD0MODA_6
340 #define BNDI0 AD0MODA_7
343 __sbit __at (0xC8) TCR20_0;
344 __sbit __at (0xC9) TCR20_1;
345 __sbit __at (0xCA) TCR20_2;
346 __sbit __at (0xCB) TCR20_3;
347 __sbit __at (0xCC) TCR20_4;
348 __sbit __at (0xCD) TCR20_5;
349 __sbit __at (0xCE) TCR20_6;
350 __sbit __at (0xCF) TCR20_7;
351 #define TMOD20 TCR20_0
352 #define TMOD21 TCR20_1
353 #define TDIR2 TCR20_2
354 #define ALTAB TCR20_3
355 #define ALTCD TCR20_4
356 #define HLTEN TCR20_5
357 #define HLTRN TCR20_6
358 #define PLEEN TCR20_7
361 __sbit __at (0xD0) PSW_0;
362 __sbit __at (0xD1) PSW_1;
363 __sbit __at (0xD2) PSW_2;
364 __sbit __at (0xD3) PSW_3;
365 __sbit __at (0xD4) PSW_4;
366 __sbit __at (0xD5) PSW_5;
367 __sbit __at (0xD6) PSW_6;
368 __sbit __at (0xD7) PSW_7;
379 __sbit __at (0xD8) I2CON_0;
380 __sbit __at (0xD9) I2CON_1;
381 __sbit __at (0xDA) I2CON_2;
382 __sbit __at (0xDB) I2CON_3;
383 __sbit __at (0xDC) I2CON_4;
384 __sbit __at (0xDD) I2CON_5;
385 __sbit __at (0xDE) I2CON_6;
386 __sbit __at (0xDF) I2CON_7;
387 #define CRSEL I2CON_0
395 __sbit __at (0xE0) ACC_0;
396 __sbit __at (0xE1) ACC_1;
397 __sbit __at (0xE2) ACC_2;
398 __sbit __at (0xE3) ACC_3;
399 __sbit __at (0xE4) ACC_4;
400 __sbit __at (0xE5) ACC_5;
401 __sbit __at (0xE6) ACC_6;
402 __sbit __at (0xE7) ACC_7;
405 __sbit __at (0xE8) IEN1_0;
406 __sbit __at (0xE9) IEN1_1;
407 __sbit __at (0xEA) IEN1_2;
408 __sbit __at (0xEB) IEN1_3;
409 __sbit __at (0xEC) IEN1_4;
410 __sbit __at (0xED) IEN1_5;
411 __sbit __at (0xEE) IEN1_6;
412 __sbit __at (0xEF) IEN1_7;
422 __sbit __at (0xF0) B_0;
423 __sbit __at (0xF1) B_1;
424 __sbit __at (0xF2) B_2;
425 __sbit __at (0xF3) B_3;
426 __sbit __at (0xF4) B_4;
427 __sbit __at (0xF5) B_5;
428 __sbit __at (0xF6) B_6;
429 __sbit __at (0xF7) B_7;
432 __sbit __at (0xF8) IP1_0;
433 __sbit __at (0xF9) IP1_1;
434 __sbit __at (0xFA) IP1_2;
435 __sbit __at (0xFB) IP1_3;
436 __sbit __at (0xFC) IP1_4;
437 __sbit __at (0xFD) IP1_5;
438 __sbit __at (0xFE) IP1_6;
439 __sbit __at (0xFF) IP1_7;
448 #endif /* P89LPC938_H */