1 /*--------------------------------------------------------------------------
4 This header allows to use the microcontrolers NXP (formerly Philips)
7 Copyright (c) 2008 Gudjon I. Gudjonsson <gudjon AT gudjon.org>
9 This library is free software; you can redistribute it and/or
10 modify it under the terms of the GNU Lesser General Public
11 License as published by the Free Software Foundation; either
12 version 2.1 of the License, or (at your option) any later version.
14 This library is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the GNU
17 Lesser General Public License for more details.
19 You should have received a copy of the GNU Lesser General Public
20 License along with this library; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA02111-1307 USA
23 The registered are ordered in the same way as in the NXP data sheet:
24 http://www.standardics.nxp.com/products/lpc900/datasheet/p89lpc933.p89lpc934.p89lpc935.p89lpc936.pdf
27 --------------------------------------------------------------------------*/
28 #ifndef __P89LPC935_6_H__
29 #define __P89LPC935_6_H__
33 SFR(ACC, 0xE0); // Accumulator
42 SFR(ADCON0, 0x8E); // A/D control register 0
51 SFR(ADCON1, 0x97); // A/D control register 1
60 SFR(ADINS, 0xA3); // A/D input select
69 SFR(ADMODA, 0xC0); // A/D mode register A
71 SBIT(BURST1, 0xC0, 6);
75 SBIT(BURST0, 0xC0, 2);
78 SFR(ADMODB, 0xA1); // A/D mode register B
86 SFR(AD0BH, 0xBB); // A/D_0 boundary high register
87 SFR(AD0BL, 0xA6); // A/D_0 boundary low register
88 SFR(AD0DAT0, 0xC5); // A/D_0 data register 0
89 SFR(AD0DAT1, 0xC6); // A/D_0 data register 1
90 SFR(AD0DAT2, 0xC7); // A/D_0 data register 2
91 SFR(AD0DAT3, 0xF4); // A/D_0 data register 3
92 SFR(AD1BH, 0xC4); // A/D_1 boundary high register
93 SFR(AD1BL, 0xBC); // A/D_1 boundary low register
94 SFR(AD1DAT0, 0xD5); // A/D_1 data register 0
95 SFR(AD1DAT1, 0xD6); // A/D_1 data register 1
96 SFR(AD1DAT2, 0xD7); // A/D_1 data register 2
97 SFR(AD1DAT3, 0xF5); // A/D_1 data register 3
98 SFR(AUXR1, 0xA2); // Auxilary function register
104 #define DPS 0x01 // Bit 2 is always 0
105 SFR(B, 0xF0); // B register
114 SFR(BRGR0, 0xBE); // Baud rate generator rate low
115 SFR(BRGR1, 0xBF); // Baud rate generator rate high
116 SFR(BRGCON, 0xBD); // Baud rate generator control
119 SFR(CCCRA, 0xEA); // Capture compare A control register
128 SFR(CCCRB, 0xEB); // Capture compare B control register
137 SFR(CCCRC, 0xEC); // Capture compare C control register
141 SFR(CCCRD, 0xED); // Capture compare D control register
145 SFR(CMP1, 0xAC); // Comparator 1 control register
152 SFR(CMP2, 0xAD); // Comparator 2 control register
159 SFR(DEECON, 0xF1); // Data EEPROM control register
165 SFR(DEEDAT, 0xF2); // Data EEPROM data register
166 SFR(DEEADR, 0xF3); // Data EEPROM address register
167 SFR(DIVM, 0x95); // CPU clock divide-by-M control
168 SFR(DPH, 0x83); // Data Pointer High
169 SFR(DPL, 0x82); // Data Pointer Low
170 SFR(FMADRH, 0xE7); // Program flash address high
171 SFR(FMADRL, 0xE6); // Program flash address low
173 // Program flash control (Read)
179 // Program flash control (Write)
188 SFR(FMDATA, 0xE5); // Program flash data
189 SFR(I2ADR, 0xDB); // I2C slave address register
198 SFR(I2CON, 0xD8); // I2C control register
204 SBIT(CRSEL, 0xD8, 0);
205 SFR(I2DAT, 0xDA); // I2C data register
206 SFR(I2SCLH, 0xDD); // I2C serial clock generator/SCL duty cycle register high
207 SFR(I2SCLL, 0xDC); // I2C serial clock generator/SCL duty cycle register low
208 SFR(I2STAT, 0xD9); // I2C status register
213 #define STA_0 0x08 // Only write 0 to the lowest three bits
214 SFR(ICRAH, 0xAB); // Input capture A register high
215 SFR(ICRAL, 0xAA); // Input capture A register low
216 SFR(ICRBH, 0xAF); // Input capture B register high
217 SFR(ICRBL, 0xAE); // Input capture B register low
218 SFR(IEN0, 0xA8); // Interrupt Enable 0
220 SBIT(EWDRT, 0xA8, 6);
222 SBIT(ES_ESR, 0xA8, 4);
227 SFR(IEN1, 0xE8); // Interrupt Enable 1
228 SBIT(EADEE, 0xE8, 7);
235 SFR(IP0, 0xB8); // Interrupt Priority 0
236 SBIT(PWDRT, 0xB8, 6);
238 SBIT(PS_PSR, 0xB8, 4);
243 SFR(IP0H, 0xB7); // Interrupt Priority 0 high
246 #define PSH_PSRH 0x10
251 SFR(IP1, 0xF8); // Interrupt Priority 1
252 SBIT(PADEE, 0xF8, 7);
259 SFR(IP1H, 0xF7); // Interrupt Priority 1 High
267 SFR(KBCON, 0x94); // Keypad control register
268 #define PATN_SEL 0x02
270 SFR(KBMASK, 0x86); // Keypad interrupt mask register
271 SFR(KBPATN, 0x93); // Keypad pattern register
272 SFR(OCRAH, 0xEF); // Output compare A register high
273 SFR(OCRAL, 0xEE); // Output compare A register low
274 SFR(OCRBH, 0xFB); // Output compare B register high
275 SFR(OCRBL, 0xFA); // Output compare B register low
276 SFR(OCRCH, 0xFD); // Output compare C register high
277 SFR(OCRCL, 0xFC); // Output compare C register low
278 SFR(OCRDH, 0xFF); // Output compare D register high
279 SFR(OCRDL, 0xFE); // Output compare D register low
280 SFR(P0, 0x80); // Port 0
285 SBIT(CMP_1, 0x80, 6); // Renamed, not to conflict with the CMP1 register
288 SBIT(CMPREF, 0x80, 5);
291 SBIT(CIN1A, 0x80, 4);
294 SBIT(CIN1B, 0x80, 3);
297 SBIT(CIN2A, 0x80, 2);
300 SBIT(CIN2B, 0x80, 1);
303 SBIT(CMP_2, 0x80, 0); // Renamed, not to conflict with the CMP2 register
305 SFR(P1, 0x90); // Port 1
324 SFR(P2, 0xA0); // Port 2
330 SBIT(SPICLK, 0xA0, 5);
341 SFR(P3, 0xB0); // Port 3
352 SFR(P0M1, 0x84); // Port 0 output mode 1
361 SFR(P0M2, 0x85); // Port 0 output mode 2
370 SFR(P1M1, 0x91); // Port 1 output mode 1
378 SFR(P1M2, 0x92); // Port 1 output mode 2
386 SFR(P2M1, 0xA4); // Port 2 output mode 1
395 SFR(P2M2, 0xA5); // Port 2 output mode 2
404 SFR(P3M1, 0xB1); // Port 3 output mode 1
407 SFR(P3M2, 0xB2); // Port 3 output mode 2
410 SFR(PCON, 0x87); // Power control register
419 SFR(PCONA, 0xB5); // Power control register A
428 SFR(PSW, 0xD0); // Program Status Word
437 SFR(PT0AD, 0xF6); // Port 0 digital input disable
443 SFR(RSTSRC, 0xDF); // Reset source register
450 SFR(RTCCON, 0xD1); // Real-time clock control
456 SFR(RTCH, 0xD2); // Real-time clock register high
457 SFR(RTCL, 0xD3); // Real-time clock register low
458 SFR(SADDR, 0xA9); // Serial port address register
459 SFR(SADEN, 0xB9); // Serial port address enable
460 SFR(SBUF, 0x99); // Serial port data buffer register
461 SFR(SCON, 0x98); // Serial port control
462 SBIT(SM0_FE, 0x98, 7);
470 SFR(SSTAT, 0xBA); // Serial port extended status register
479 SFR(SP, 0x81); // Stack Pointer
480 SFR(SPCTL, 0xE2); // SPI control register
489 SFR(SPSTAT, 0xE1); // SPI status register
492 SFR(SPDAT, 0xE3); // SPI data register
493 SFR(TAMOD, 0x8F); // Timer 0 and 1 auxiliary mode
496 SFR(TCON, 0x88); // Timer 0 and 1 control
505 SFR(TCR20, 0xC8); // CCU control register 0
506 SBIT(PLEEN, 0xC8, 7);
507 SBIT(HLTRN, 0xC8, 6);
508 SBIT(HLTEN, 0xC8, 5);
509 SBIT(ALTCD, 0xC8, 4);
510 SBIT(ALTAB, 0xC8, 3);
511 SBIT(TDIR2, 0xC8, 2);
512 SBIT(TMOD21, 0xC8, 1);
513 SBIT(TMOD20, 0xC8, 0);
514 SFR(TCR21, 0xF9); // CCU control register 1
520 SFR(TH0, 0x8C); // Timer 0 high
521 SFR(TH1, 0x8D); // Timer 1 high
522 SFR(TH2, 0xCD); // CCU timer high
523 SFR(TICR2,0xC9); // CCU interrupt control register
531 SFR(TIFR2,0xE9); // CCU interrupt flag register
539 SFR(TISE2,0xDE); // CCU interrupt status encode register
543 SFR(TL0, 0x8A); // Timer 0 low
544 SFR(TL1, 0x8B); // Timer 1 low
545 SFR(TL2, 0xCC); // CCU timer low
546 SFR(TMOD, 0x89); // Timer 0 and 1 mode
555 SFR(TOR2H, 0xCF); // CCU reload register high
556 SFR(TOR2L, 0xCE); // CCU reload register low
557 SFR(TPCR2H,0xCB); // Prescaler control register high
558 #define TPCR2H_1 0x02
559 #define TPCR2H_0 0x01
560 SFR(TPCR2L,0xCA); // Prescaler control register low
561 #define TPCR2L_7 0x80
562 #define TPCR2L_6 0x40
563 #define TPCR2L_5 0x20
564 #define TPCR2L_4 0x10
565 #define TPCR2L_3 0x08
566 #define TPCR2L_2 0x04
567 #define TPCR2L_1 0x02
568 #define TPCR2L_0 0x01
569 SFR(TRIM, 0x96); // Internal oscillator trim register
578 SFR(WDCON, 0xA7); // Watchdog control register
585 SFR(WDL, 0xC1); // Watchdog load
586 SFR(WFEED1, 0xC2); // Watchdog feed 1
587 SFR(WFEED2, 0xC3); // Watchdog feed 2
588 #endif // __P89LPC935_6_H__