1 /*--------------------------------------------------------------------------
\r
2 * Register Declarations for Texas Intruments MSC12xx MCU family
\r
4 * Written By - Philippe Latu / philippe.latu(at)linux-france.org
\r
5 * $Id: msc1210.h 893 2006-05-10 21:32:22Z latu $
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7 * Copyright (C) 2006 Philippe Latu
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9 * This library is free software; you can redistribute it and/or
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10 * modify it under the terms of the GNU Lesser General Public
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11 * License as published by the Free Software Foundation; either
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12 * version 2.1 of the License, or (at your option) any later version.
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14 * This library is distributed in the hope that it will be useful,
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15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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17 * Lesser General Public License for more details.
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19 * You should have received a copy of the GNU Lesser General Public
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20 * License along with this library; if not, write to the Free Software
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21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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23 *---------------------------------------------------------------------------*/
\r
25 #ifndef __MSC1210_H__
\r
26 #define __MSC1210_H__
\r
28 /* BYTE Registers with bit definitions */
\r
30 __sfr __at (0x80) P0; /* Port 0 */
\r
31 __sfr __at (0x81) SP; /* Stack Pointer */
\r
32 __sfr __at (0x82) DPL; /* Data Pointer 0: low byte */
\r
33 __sfr __at (0x82) DPL0; /* Data Pointer 0: low byte */
\r
34 __sfr __at (0x83) DPH; /* Data Pointer 0: high byte */
\r
35 __sfr __at (0x83) DPH0; /* Data Pointer 0: high byte */
\r
36 __sfr __at (0x84) DPL1; /* Data Pointer 1: low byte */
\r
37 __sfr __at (0x85) DPH1; /* Data Pointer 1: high byte */
\r
38 __sfr __at (0x86) DPS; /* Data Pointer Select */
\r
39 __sfr __at (0x87) PCON; /* Power Control */
\r
40 __sfr __at (0x88) TCON; /* Timer Control */
\r
41 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
\r
42 /* |TF1|TR1|TF0|TR0|IE1|IT1|IE0|IT0| */
\r
43 __sbit __at (0x88) IT0; /* External Interrupt 0 Type */
\r
44 __sbit __at (0x89) IE0; /* External Interrupt 0 Edge Flag */
\r
45 __sbit __at (0x8a) IT1; /* External Interrupt 1 Type */
\r
46 __sbit __at (0x8b) IE1; /* External Interrupt 1 Edge Flag */
\r
47 __sbit __at (0x8c) TR0; /* Timer 0 On/Off Control */
\r
48 __sbit __at (0x8d) TF0; /* Timer 0 Overflow Flag */
\r
49 __sbit __at (0x8e) TR1; /* Timer 1 On/Off Control */
\r
50 __sbit __at (0x8f) TF1; /* Timer 1 Overflow Flag */
\r
51 __sfr __at (0x89) TMOD; /* Timer Mode */
\r
52 __sfr __at (0x8a) TL0; /* Timer 0: low byte */
\r
53 __sfr __at (0x8b) TL1; /* Timer 1: low byte */
\r
54 __sfr __at (0x8c) TH0; /* Timer 0: high byte */
\r
55 __sfr __at (0x8d) TH1; /* Timer 1: high byte */
\r
56 __sfr __at (0x8e) CKCON; /* Clock Control */
\r
57 __sfr __at (0x8f) MWS; /* Memory Write Select */
\r
58 __sfr __at (0x90) P1; /* Port 1 */
\r
59 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
\r
60 /* | | | | | | |T2EX|T2 | */
\r
61 __sbit __at (0x90) T2; /* Timer 2 External Input */
\r
62 __sbit __at (0x91) T2EX; /* Timer 2 Capture/Reload */
\r
63 __sfr __at (0x91) EXIF; /* External Interrupt Flag */
\r
64 __sfr __at (0x92) MPAGE; /* Memory Page */
\r
65 __sfr __at (0x92) _XPAGE; /* XDATA/PDATA PAGE */
\r
66 __sfr __at (0x93) CADDR; /* Configuration Address Register */
\r
67 __sfr __at (0x94) CDATA; /* Configuration Data Register */
\r
68 __sfr __at (0x95) MCON; /* Memory Configuration */
\r
69 __sfr __at (0x98) SCON; /* Serial Control 0 */
\r
70 __sfr __at (0x98) SCON0; /* Serial Control 0 */
\r
71 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
\r
72 /* |SM0|SM1|SM2|REN|TB8|RB8|TI |RI | */
\r
73 __sbit __at (0x98) RI; /* Receive Interrupt Flag */
\r
74 __sbit __at (0x98) RI0; /* Receive Interrupt Flag */
\r
75 __sbit __at (0x98) RI_0; /* Receive Interrupt Flag */
\r
76 __sbit __at (0x99) TI; /* Transmit Interrupt Flag */
\r
77 __sbit __at (0x99) TI0; /* Transmit Interrupt Flag */
\r
78 __sbit __at (0x99) TI_0; /* Transmit Interrupt Flag */
\r
79 __sbit __at (0x9a) RB8; /* Receive Bit 8 */
\r
80 __sbit __at (0x9a) RB8_0; /* Receive Bit 8 */
\r
81 __sbit __at (0x9b) TB8; /* Transmit Bit 8 */
\r
82 __sbit __at (0x9b) TB8_0; /* Transmit Bit 8 */
\r
83 __sbit __at (0x9c) REN; /* Receive Enable */
\r
84 __sbit __at (0x9c) REN_0; /* Receive Enable */
\r
85 __sbit __at (0x9d) SM2; /* Multiprocessor Communication Enable*/
\r
86 __sbit __at (0x9d) SM2_0; /* Multiprocessor Communication Enable*/
\r
87 __sbit __at (0x9e) SM1; /* Serial Port Select Mode 1 */
\r
88 __sbit __at (0x9e) SM1_0; /* Serial Port Select Mode 1 */
\r
89 __sbit __at (0x9f) SM0; /* Serial Port Select Mode 0 */
\r
90 __sbit __at (0x9f) SM0_0; /* Serial Port Select Mode 0 */
\r
91 __sfr __at (0x99) SBUF; /* Serial Buffer 0 */
\r
92 __sfr __at (0x99) SBUF0; /* Serial Buffer 0 */
\r
93 __sfr __at (0x9a) SPICON; /* SPI Control */
\r
94 __sfr __at (0x9a) I2CCON; /* I2C Control */
\r
95 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
\r
96 /* |SCLK2|SCLK1|SCLK0|FIFO|ORDER|MSTR|CPHA|CPOL| */
\r
97 __sbit __at (0x9a) CPOL; /* Serial Clock Polarity */
\r
98 __sbit __at (0x9b) CPHA; /* Serial Clock Phase Control */
\r
99 __sbit __at (0x9c) MSTR; /* Set Master Mode */
\r
100 __sbit __at (0x9d) ORDER; /* Set Bit Order Transmit/Receive */
\r
101 __sbit __at (0x9e) FIFO; /* Enable Fifo Buffer */
\r
102 __sbit __at (0x9f) SCLK0; /* Clock Divider Select 0 */
\r
103 __sbit __at (0xa0) SCLK1; /* Clock Divider Select 1 */
\r
104 __sbit __at (0xa1) SCLK2; /* Clock Divider Select 2 */
\r
105 __sfr __at (0x9b) SPIDATA; /* SPI Data */
\r
106 __sfr __at (0x9b) I2CDATA; /* I2C Data */
\r
107 __sfr __at (0x9c) SPIRCON; /* SPI Receive Control */
\r
108 __sfr __at (0x9c) I2CGM; /* I2C GM Register */
\r
109 __sfr __at (0x9d) SPITCON; /* SPI Transmit Control */
\r
110 __sfr __at (0x9d) I2CSTAT; /* I2C Status */
\r
111 __sfr __at (0x9e) SPISTART; /* SPI Buffer Start Address */
\r
112 __sfr __at (0x9e) I2CSTART; /* I2C Start */
\r
113 __sfr __at (0x9f) SPIEND; /* SPI Buffer End Address */
\r
114 __sfr __at (0xa0) P2; /* Port 2 */
\r
115 __sfr __at (0xa1) PWMCON; /* PWM Control */
\r
116 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
\r
117 /* | | |PPOL|PWMSEL|SPDSEL|TPCNTL2|TPCNTL1|TPCNTL0| */
\r
118 __sbit __at (0xa1) TPCNTL0; /* Generator Control */
\r
119 __sbit __at (0xa2) TPCNTL1; /* Generator Control */
\r
120 __sbit __at (0xa3) TPCNTL2; /* Generator Control */
\r
121 __sbit __at (0xa4) SPDSEL; /* Speed Selection */
\r
122 __sbit __at (0xa5) PWMSEL; /* PWM Register Select */
\r
123 __sbit __at (0xa6) PPOL; /* Period Polarity */
\r
124 __sfr __at (0xa2) PWMLOW; /* PWM low byte */
\r
125 __sfr __at (0xa2) TONELOW; /* Tone low byte */
\r
126 __sfr __at (0xa3) PWMHI; /* PWM high byte */
\r
127 __sfr __at (0xa3) TONEHI; /* Tone high byte */
\r
128 __sfr __at (0xa4) AIPOL; /* Auxiliary Interrupt Poll */
\r
129 __sfr __at (0xa5) PAI; /* Pending Auxiliary Interrupt */
\r
130 __sfr __at (0xa6) AIE; /* Auxiliary Interrupt Enable */
\r
131 __sfr __at (0xa7) AISTAT; /* Auxiliary Interrupt Status */
\r
132 __sfr __at (0xa8) IE; /* Interrupt Enable */
\r
133 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
\r
134 /* |EA |ES1|ET2|ES0|ET1|EX1|ET0|EX0| */
\r
135 __sbit __at (0xa8) EX0; /* Enable External Interrupt 0 */
\r
136 __sbit __at (0xa9) ET0; /* Enable Timer 0 Interrupt */
\r
137 __sbit __at (0xaa) EX1; /* Enable External Interrupt 1 */
\r
138 __sbit __at (0xab) ET1; /* Enable Timer 1 Interrupt */
\r
139 __sbit __at (0xac) ES0; /* Enable Serial Port 0 Interrupt */
\r
140 __sbit __at (0xad) ET2; /* Enable Timer 2 Interrupt */
\r
141 __sbit __at (0xae) ES1; /* Enable Serial Port 1 Interrupt */
\r
142 __sbit __at (0xaf) EA; /* Global Interrupt Enable */
\r
143 __sfr __at (0xa9) BPCON; /* Breakpoint Control */
\r
144 __sfr __at (0xaa) BPL; /* Breakpoint Address Low */
\r
145 __sfr __at (0xab) BPH; /* Breakpoint Address High */
\r
146 __sfr __at (0xac) P0DDRL; /* Port 0 Data Direction Low */
\r
147 __sfr __at (0xad) P0DDRH; /* Port 0 Data Direction High */
\r
148 __sfr __at (0xae) P1DDRL; /* Port 1 Data Direction Low */
\r
149 __sfr __at (0xaf) P1DDRH; /* Port 1 Data Direction High */
\r
150 __sfr __at (0xb0) P3; /* Port 3 */
\r
151 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
\r
152 /* |RD |WR |T1 |T0 |INT1|INT0|TXD|RXD| */
\r
153 __sbit __at (0xb0) RXD; /* Serial Port 0 Receive */
\r
154 __sbit __at (0xb0) RXD0; /* Serial Port 0 Receive */
\r
155 __sbit __at (0xb1) TXD; /* Serial Port 0 Transmit */
\r
156 __sbit __at (0xb1) TXD0; /* Serial Port 0 Transmit */
\r
157 __sbit __at (0xb2) INT0; /* External Interrupt 0 */
\r
158 __sbit __at (0xb3) INT1; /* External Interrupt 1 */
\r
159 __sbit __at (0xb4) T0; /* Timer 0 External Input */
\r
160 __sbit __at (0xb5) T1; /* Timer 1 External Input */
\r
161 __sbit __at (0xb6) WR; /* External Memory Write Strobe */
\r
162 __sbit __at (0xb7) RD; /* External Memory Read Strobe */
\r
163 __sfr __at (0xb1) P2DDRL; /* Port 2 Data Direction Low */
\r
164 __sfr __at (0xb2) P2DDRH; /* Port 2 Data Direction High */
\r
165 __sfr __at (0xb3) P3DDRL; /* Port 3 Data Direction Low */
\r
166 __sfr __at (0xb4) P3DDRH; /* Port 3 Data Direction High */
\r
167 __sfr __at (0xb5) DACL; /* Digital-to-Analog Converter Low */
\r
168 __sfr __at (0xb6) DACH; /* Digital-to-Analog Converter High */
\r
169 __sfr __at (0xb7) DACSEL; /* Digital-to-Analog Converter Select */
\r
170 __sfr __at (0xb8) IP; /* Interrupt Priority */
\r
171 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
\r
172 /* | | |PT2|PS |PT1|PX1|PT0|PX0| */
\r
173 __sbit __at (0xb8) PX0; /* External Interrupt 0 */
\r
174 __sbit __at (0xb9) PT0; /* Timer 0 */
\r
175 __sbit __at (0xba) PX1; /* External Interrupt 1 */
\r
176 __sbit __at (0xbb) PT1; /* Timer 1 */
\r
177 __sbit __at (0xbc) PS; /* Serial Port */
\r
178 __sbit __at (0xbd) PT2; /* Timer 2 */
\r
179 __sfr __at (0xc0) SCON1; /* Serial Control 1 */
\r
180 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
\r
181 /* |SM0|SM1|SM2|REN|TB8|RB8|TI |RI | */
\r
182 __sbit __at (0xc0) RI1; /* Receive Interrupt Flag */
\r
183 __sbit __at (0xc0) RI_1; /* Receive Interrupt Flag */
\r
184 __sbit __at (0xc1) TI1; /* Transmit Interrupt Flag */
\r
185 __sbit __at (0xc1) TI_1; /* Transmit Interrupt Flag */
\r
186 __sbit __at (0xc2) RB8_1; /* Receive Bit 8 */
\r
187 __sbit __at (0xc3) TB8_1; /* Transmit Bit 8 */
\r
188 __sbit __at (0xc4) REN_1; /* Receive Enable */
\r
189 __sbit __at (0xc5) SM2_1; /* Multiprocessor Communication Enable*/
\r
190 __sbit __at (0xc6) SM1_1; /* Serial Port Select Mode 1 */
\r
191 __sbit __at (0xc7) SM0_1; /* Serial Port Select Mode 0 */
\r
192 __sfr __at (0xc1) SBUF1; /* Serial Buffer 1 */
\r
193 __sfr __at (0xc6) EWU; /* Enable Wake Up */
\r
194 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
\r
195 /* | | | | | |EWUEX1|EWUEX0|EWUWDT| */
\r
196 __sbit __at (0xc6) EWUWDT; /* Enable Watchdog Interrupt */
\r
197 __sbit __at (0xc7) EWUEX0; /* Enable External Interrupt 0 */
\r
198 __sbit __at (0xc8) EWUEX1; /* Enable External Interrupt 1 */
\r
199 __sfr __at (0xc7) SYSCLK; /* System Clock Divider */
\r
200 __sfr __at (0xc8) T2CON; /* Timer 2 Control */
\r
201 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
\r
202 /* |TF2|EXF2|RCLK|TCLK|EXEN2|TR2|C_T2|CP_RL2 | */
\r
203 __sbit __at (0xc8) CP_RL2; /* Capture/Reload Flag */
\r
204 __sbit __at (0xc9) C_T2; /* Overflow Flag */
\r
205 __sbit __at (0xca) TR2; /* Timer Run */
\r
206 __sbit __at (0xcb) EXEN2; /* Timer External Enable */
\r
207 __sbit __at (0xcc) TCLK; /* Transmit Clock Flag */
\r
208 __sbit __at (0xcd) RCLK; /* Receive Clock Flag */
\r
209 __sbit __at (0xce) EXF2; /* External Flag */
\r
210 __sbit __at (0xcf) TF2; /* Overflow Flag */
\r
211 __sfr __at (0xca) RCAP2L; /* Timer 2 Capture Low */
\r
212 __sfr __at (0xcb) RCAP2H; /* Timer 2 Capture High */
\r
213 __sfr __at (0xcc) TL2; /* Timer 2 Low byte */
\r
214 __sfr __at (0xcd) TH2; /* Timer 2 High byte */
\r
215 __sfr __at (0xd0) PSW; /* Program Status Word */
\r
216 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
\r
217 /* |CY |AC |F0 |RS1|RS0|OV |F1 |P | */
\r
218 __sbit __at (0xd0) P; /* Parity Flag */
\r
219 __sbit __at (0xd1) F1; /* General Purpose User Flag 1 */
\r
220 __sbit __at (0xd2) OV; /* Overflow Flag */
\r
221 __sbit __at (0xd3) RS0; /* Register Bank Select 0 Flag */
\r
222 __sbit __at (0xd4) RS1; /* Register Bank Select 1 Flag */
\r
223 __sbit __at (0xd5) F0; /* General Purpose User Flag 0 */
\r
224 __sbit __at (0xd6) AC; /* Auxiliary Carry Flag */
\r
225 __sbit __at (0xd7) CY; /* Carry Flag */
\r
226 __sfr __at (0xd1) OCL; /* (ADC) Offset Calibration Low byte */
\r
227 __sfr __at (0xd2) OCM; /* (ADC) Offset Calibration Middle byte */
\r
228 __sfr __at (0xd3) OCH; /* (ADC) Offset Calibration High byte */
\r
229 __sfr __at (0xd4) GCL; /* (ADC) Gain Low byte */
\r
230 __sfr __at (0xd5) GCM; /* (ADC) Gain Middle byte */
\r
231 __sfr __at (0xd6) GCH; /* (ADC) Gain High byte */
\r
232 __sfr __at (0xd7) ADMUX; /* ADC Multiplexer Register */
\r
233 __sfr __at (0xd8) EICON; /* Enable Interrupt Control */
\r
234 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
\r
235 /* |SMOD1| |EAI|AI |WDTI| | | | */
\r
236 __sbit __at (0xdb) WDTI; /* Watchdog Timer Interrupt Flag */
\r
237 __sbit __at (0xdc) AI; /* Auxiliary Interrupt Flag */
\r
238 __sbit __at (0xdd) EAI; /* Enable Auxiliary Interrupt */
\r
239 __sbit __at (0xdf) SMOD1; /* Serial Port 1 Mode */
\r
240 __sfr __at (0xd9) ADRESL; /* ADC Conversion Result Low byte */
\r
241 __sfr __at (0xda) ADRESM; /* ADC Conversion Result Middle byte */
\r
242 __sfr __at (0xdb) ADRESH; /* ADC Conversion Result High byte */
\r
243 __sfr __at (0xdc) ADCON0; /* ADC Control 0 */
\r
244 __sfr __at (0xdd) ADCON1; /* ADC Control 1 */
\r
245 __sfr __at (0xde) ADCON2; /* ADC Control 2 */
\r
246 __sfr __at (0xdf) ADCON3; /* ADC Control 3 */
\r
247 __sfr __at (0xe0) ACC; /* Accumulator */
\r
248 __sfr __at (0xe1) SSCON; /* Summation and Shift Control */
\r
249 __sfr __at (0xe2) SUMR0; /* Summation Register 0 (LSB) */
\r
250 __sfr __at (0xe3) SUMR1; /* Summation Register 1 */
\r
251 __sfr __at (0xe4) SUMR2; /* Summation Register 2 */
\r
252 __sfr __at (0xe5) SUMR3; /* Summation Register 3 (MSB) */
\r
253 __sfr __at (0xe6) ODAC; /* (ADC) Offset DAC Register */
\r
254 __sfr __at (0xe7) LVDCON; /* Low Voltage Detection Control */
\r
255 __sfr __at (0xe8) EIE; /* Extended Interrupt Enable */
\r
256 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
\r
257 /* | | | |EWDI|EX5|EX4|EX3|EX2| */
\r
258 __sbit __at (0xe8) EX2; /* Enable External Interrupt 2 */
\r
259 __sbit __at (0xe9) EX3; /* Enable External Interrupt 3 */
\r
260 __sbit __at (0xea) EX4; /* Enable External Interrupt 4 */
\r
261 __sbit __at (0xeb) EX5; /* Enable External Interrupt 5 */
\r
262 __sbit __at (0xec) EWDI; /* Enable Watchdog Interrupt */
\r
263 __sfr __at (0xe9) HWPC0; /* Hardware Product Code 0 */
\r
264 __sfr __at (0xea) HWPC1; /* Hardware Product Code 1 */
\r
265 __sfr __at (0xeb) HWVER; /* Hardware Version number */
\r
266 __sfr __at (0xee) FMCON; /* Flash Memory Control */
\r
267 __sfr __at (0xef) FTCON; /* Flash Memory Timing Control */
\r
268 __sfr __at (0xf0) B; /* B Register */
\r
269 __sfr __at (0xf1) PDCON; /* Power Down Control */
\r
270 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
\r
271 /* | | | |PDPWM|PDAD|PDWDT|PDST|PDSPI| */
\r
272 __sbit __at (0xf1) PDSPI; /* SPI System Control */
\r
273 __sbit __at (0xf2) PDST; /* System Timer Control */
\r
274 __sbit __at (0xf3) PDWDT; /* Watchdog Timer Control */
\r
275 __sbit __at (0xf4) PDAD; /* A/D Control */
\r
276 __sbit __at (0xf5) PDPWM; /* PWM Control */
\r
277 __sfr __at (0xf2) PASEL; /* /PSEN|ALE Select */
\r
278 __sfr __at (0xf6) ACLK; /* Analog Clock */
\r
279 __sfr __at (0xf7) SRST; /* System Reset Register */
\r
280 __sfr __at (0xf8) EIP; /* Extended Interrupt Priority */
\r
281 /* _7_ _6_ _5_ _4_ _3_ _2_ _1_ _0_ */
\r
282 /* | | | |PWDI|PX5|PX4|PX3|PX2| */
\r
283 __sbit __at (0xf8) PX2; /* External Interrupt 2 Priority */
\r
284 __sbit __at (0xf9) PX3; /* External Interrupt 3 Priority */
\r
285 __sbit __at (0xfa) PX4; /* External Interrupt 4 Priority */
\r
286 __sbit __at (0xfb) PX5; /* External Interrupt 5 Priority */
\r
287 __sbit __at (0xfc) PWDI; /* Watchdog Interrupt Priority */
\r
288 __sfr __at (0xf9) SECINT; /* Seconds Timer Interrupt */
\r
289 __sfr __at (0xfa) MSINT; /* Milliseconds Interrupt */
\r
290 __sfr __at (0xfb) USEC; /* Microsecond Register */
\r
291 __sfr __at (0xfc) MSECL; /* Millisecond Low byte */
\r
292 __sfr __at (0xfd) MSECH; /* Millisecond High byte */
\r
293 __sfr __at (0xfe) HMSEC; /* Hundred Millisecond Clock */
\r
294 __sfr __at (0xff) WDTCON; /* Watchdog Control */
\r
296 /* Word Registers */
\r
297 __sfr16 __at (0x8c8a) TMR0;
\r
298 __sfr16 __at (0x8d8b) TMR1;
\r
299 __sfr16 __at (0xa3a2) PWM;
\r
300 __sfr16 __at (0xa3a2) TONE;
\r
301 __sfr16 __at (0xabaa) BP;
\r
302 __sfr16 __at (0xabaa) BREAKPT;
\r
303 __sfr16 __at (0xadac) P0DDR;
\r
304 __sfr16 __at (0xafae) P1DDR;
\r
305 __sfr16 __at (0xb2b1) P2DDR;
\r
306 __sfr16 __at (0xb4b3) P3DDR;
\r
307 __sfr16 __at (0xcbca) RCAP2;
\r
308 __sfr16 __at (0xcdcc) TMR2;
\r
309 __sfr16 __at (0xdfde) DECIMATION;
\r
310 __sfr16 __at (0xfdfc) ONEMS;
\r
311 __sfr16 __at (0xfdfc) MSEC;
\r
313 /* Double Word Registers */
\r
314 __sfr32 __at (0xe5e4e3e2) SUMR;
\r