1 /*-------------------------------------------------------------------------
2 Register Declarations for the mcs51 compatible microcontrollers
4 Written By - Bela Torok / bela.torok@kssg.ch (November 2000)
6 This library is free software; you can redistribute it and/or
7 modify it under the terms of the GNU Lesser General Public
8 License as published by the Free Software Foundation; either
9 version 2.1 of the License, or (at your option) any later version.
11 This library is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 Lesser General Public License for more details.
16 You should have received a copy of the GNU Lesser General Public
17 License along with this library; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 In other words, you are welcome to use, share and improve this program.
21 You are forbidden to forbid anyone else to use, share and improve
22 what you give them. Help stamp out software-hoarding!
27 Version 1.0 Nov 2, 2000 - B. Torok / bela.torok@kssg.ch
28 Initial release, supported microcontrollers:
29 8051, 8052, Atmel AT89C1051, AT89C2051, AT89C4051,
30 Infineon / Siemens SAB80515, SAB80535, SAB80515A
32 Version 1.0.1 (Nov 3, 2000)
33 SAB80515A definitions revised by Michael Schmitt / michael.schmitt@t-online.de
35 Version 1.0.2 (Nov 6, 2000)
36 T2CON bug corrected 8052 and SABX microcontrollers have different T2CONs
37 Support for the Atmel AT89C52, AT80LV52, AT89C55, AT80LV55
38 Support for the Dallas DS80C320 and DS80C323
39 B. Torok / bela.torok@kssg.ch
41 Version 1.0.3 (Nov 7, 2000)
42 SAB80517 definitions added by Michael Schmitt / michael.schmitt@t-online.de
43 Dallas AT89S53 definitions added by B. Torok / bela.torok@kssg.ch
44 Dallas DS87C520 and DS83C520 definitions added by B. Torok / bela.torok@kssg.ch
46 Version 1.0.4 (Nov 9, 2000)
47 To simplify the identication of registers, a large number of definitios
48 were renamed. Long register names now (hopefully) clearly define the
49 function of the registers.
50 Dallas DS89C420 definitions added by B. Torok / bela.torok@kssg.ch
52 Version 1.0.5 (Dec 15, 2000)
53 Definitions added: #ifdef MCS51REG_EXTERNAL_ROM
54 #ifdef MCS51REG_EXTERNAL_RAM
55 #ifndef MCS51REG_DISABLE_WARNINGS
58 Version 1.0.6 (March 10, 2001)
59 Support for the Dallas DS5000 & DS2250
60 Support for the Dallas DS5001 & DS2251
61 Support for the Dallas DS80C390
62 microcontrollers - B. Torok / bela.torok@kssg.ch
64 Version 1.0.7 (June 7, 2001)
65 #ifndef MCS51REG_DISABLE_WARNINGS removed
66 #ifdef MCS51REG_DISABLE_WARNINGS added - B. Torok / bela.torok@kssg.ch
67 Support for the Philips P80C552 added - Bernhard Held / Bernhard.Held@otelo-online.de
69 Version 1.0.8 (Feb 28, 2002)
70 Dallas DS89C420 definitions corrected by B. Torok / bela.torok@kssg.ch
71 Revised by lanius@ewetel.net
73 Version 1.0.9 (Sept 9, 2002)
74 Register declarations for the Atmel T89C51RD2 added by Johannes Hoelzl / johannes.hoelzl@gmx.de
76 Version 1.0.10 (Sept 19, 2002)
77 Register declarations for the Philips P89C668 added by Eric Limpens / Eric@limpens.net
79 Version 1.0.11 (Sept 19, 2004)
80 Dallas DS5000 MCON Register declarations corrected by Radek Zadera / a2i@swipnet.se
82 Version 1.0.12 (March 2, 2005)
83 Infineon SAB80C509 Register declarations added Thomas Boje / thomas@boje.name
85 Adding support for additional microcontrollers:
86 -----------------------------------------------
88 1. Don't modify this file!!!
90 2. Insert your code in a separate file e.g.: mcs51reg_update.h and include
91 this after the #define HEADER_MCS51REG statement in this file
93 3. The mcs51reg_update.h file should contain following definitions:
95 a. An entry with the inventory of the register set of the
96 microcontroller in the "Describe microcontrollers" section.
98 b. If necessary add entry(s) for registers not defined in this file
100 c. Define interrupt vectors
102 4. Compile a program for the microcontroller using the Preprocessor only, e.g.:,
103 sdcc -E test.c > t.txt
104 and check definitions for validity in the t.txt file.
106 5. If everithing seems to be OK send me the mcs51reg_update.h file. --> bela.torok@kssg.ch
107 I'm going to resolve conflicts & verify/merge new definitions to this file.
110 Microcontroller support:
112 Use one of the following options:
114 1. use #include <mcs51reg.h> in your program & define MICROCONTROLLER_XXXX in your makefile.
116 2. use following definitions prior the
117 #include <mcs51reg.h> line in your program:
119 #define MICROCONTROLLER_8052 -> 8052 type microcontroller
121 #define MICROCONTROLLER_AT89CX051 -> Atmel AT89C1051, AT89C2051 and AT89C4051 microcontrollers
124 Use only one of the following definitions!!!
126 Supported Microcontrollers:
129 MICROCONTROLLER_8051 8051
130 MICROCONTROLLER_8052 8052
131 MICROCONTROLLER_AT89CX051 Atmel AT89C1051, AT89C2051 and AT89C4051
132 MICROCONTROLLER_AT89S53 Atmel AT89S53 microcontroller
133 MICROCONTROLLER_AT89X52 Atmel AT89C52 and AT80LV52 microcontrollers
134 MICROCONTROLLER_AT89X55 Atmel AT89C55 and AT80LV55 microcontrollers
135 MICROCONTROLLER_DS5000 Dallas DS5000 & DS2250 microcontroller
136 MICROCONTROLLER_DS5001 Dallas DS5001 & DS2251 microcontroller
137 MICROCONTROLLER_DS80C32X Dallas DS80C320 and DS80C323 microcontrollers
138 MICROCONTROLLER_DS80C390 Dallas DS80C390 microcontroller
139 MICROCONTROLLER_DS89C420 Dallas DS89C420 microcontroller
140 MICROCONTROLLER_DS8XC520 Dallas DS87C520 and DS83C520 microcontrollers
141 MICROCONTROLLER_P80C552 Philips P80C552
142 MICROCONTROLLER_P89C668 Philips P89C668
143 MICROCONTROLLER_SAB80C509 Infineon / Siemens SAB80C509
144 MICROCONTROLLER_SAB80515 Infineon / Siemens SAB80515 & SAB80535
145 MICROCONTROLLER_SAB80515A Infineon / Siemens SAB80515A
146 MICROCONTROLLER_SAB80517 Infineon / Siemens SAB80517
147 MICROCONTROLLER_T89C51RD2 Atmel T89C51RD2
149 Additional definitions (use them prior the #include mcs51reg.h statement):
151 Ports P0 & P2 are not available if external ROM used.
152 Use statement "#define MCS51REG_EXTERNAL_ROM" to undefine P0 & P2.
154 Ports P0, P2, P3_6, WR, P3_7 & RD are not available if external RAM is used.
155 Use statement "#define MCS51REG_EXTERNAL_RAM" to undefine P0, P2,
158 #define MCS51REG_ENABLE_WARNINGS -> enable warnings
160 -----------------------------------------------------------------------*/
163 #ifndef HEADER_MCS51REG
164 #define HEADER_MCS51REG
166 ///////////////////////////////////////////////////////
167 /// Insert header here (for developers only) ///
168 /// remove "//" from the begining of the next line ///
169 //#include "mcs51reg_update.h" ///
170 ///////////////////////////////////////////////////////
172 //////////////////////////////////
173 /// Describe microcontrollers ///
174 /// (inventory of registers) ///
175 //////////////////////////////////
177 // definitions for the 8051
178 #ifdef MICROCONTROLLER_8051
179 #ifdef MICROCONTROLLER_DEFINED
180 #define MCS51REG_ERROR
182 #ifndef MICROCONTROLLER_DEFINED
183 #define MICROCONTROLLER_DEFINED
185 #ifdef MCS51REG_ENABLE_WARNINGS
186 #warning Selected HW: 8051
192 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
203 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
205 #define IP__x__x__x__PS__PT1__PX1__PT0__PX0
210 // end of definitions for the 8051
213 // definitions for the 8052 microcontroller
214 #ifdef MICROCONTROLLER_8052
215 #ifdef MICROCONTROLLER_DEFINED
216 #define MCS51REG_ERROR
218 #ifndef MICROCONTROLLER_DEFINED
219 #define MICROCONTROLLER_DEFINED
221 #ifdef MCS51REG_ENABLE_WARNINGS
222 #warning Selected HW: 8052
229 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
240 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
242 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
246 // 8052 specific registers
247 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
253 // end of definitions for the 8052 microcontroller
256 // definitionsons for the Atmel
257 // AT89C1051, AT89C2051 and AT89C4051 microcontrollers
258 #ifdef MICROCONTROLLER_AT89CX051
259 #ifdef MICROCONTROLLER_DEFINED
260 #define MCS51REG_ERROR
262 #ifndef MICROCONTROLLER_DEFINED
263 #define MICROCONTROLLER_DEFINED
265 #ifdef MCS51REG_ENABLE_WARNINGS
266 #warning Selected HW: Atmel AT89Cx051
268 // 8051 register set without P0 & P2
272 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
282 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
284 #define IP__x__x__x__PS__PT1__PX1__PT0__PX0
289 // end of definitionsons for the Atmel
290 // AT89C1051, AT89C2051 and AT89C4051 microcontrollers
293 // definitions for the Atmel AT89S53
294 #ifdef MICROCONTROLLER_AT89S53
295 #ifdef MICROCONTROLLER_DEFINED
296 #define MCS51REG_ERROR
298 #ifndef MICROCONTROLLER_DEFINED
299 #define MICROCONTROLLER_DEFINED
301 #ifdef MCS51REG_ENABLE_WARNINGS
302 #warning Selected HW: AT89S53
309 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
320 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
322 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
326 // 8052 specific registers
327 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
332 // AT89S53 specific register
333 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
334 #define P1_EXT__x__x__x__x__x__x__T2EX__T2
342 // end of definitions for the Atmel AT89S53 microcontroller
345 // definitions for the Atmel AT89C52 and AT89LV52 microcontrollers
346 #ifdef MICROCONTROLLER_AT89X52
347 #ifdef MICROCONTROLLER_DEFINED
348 #define MCS51REG_ERROR
350 #ifndef MICROCONTROLLER_DEFINED
351 #define MICROCONTROLLER_DEFINED
353 #ifdef MCS51REG_ENABLE_WARNINGS
354 #warning Selected HW: AT89C52 or AT89LV52
361 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
372 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
374 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
378 // 8052 specific registers
379 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
384 // AT89X55 specific register
385 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
386 #define P1_EXT__x__x__x__x__x__x__T2EX__T2
388 // end of definitions for the Atmel AT89C52 and AT89LV52 microcontrollers
391 // definitions for the Atmel AT89C55 and AT89LV55 microcontrollers
392 #ifdef MICROCONTROLLER_AT89X55
393 #ifdef MICROCONTROLLER_DEFINED
394 #define MCS51REG_ERROR
396 #ifndef MICROCONTROLLER_DEFINED
397 #define MICROCONTROLLER_DEFINED
399 #ifdef MCS51REG_ENABLE_WARNINGS
400 #warning Selected HW: AT89C55 or AT89LV55
407 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
418 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
420 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
424 // 8052 specific registers
425 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
430 // AT89X55 specific register
431 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
432 #define P1_EXT__x__x__x__x__x__x__T2EX__T2
434 // end of definitions for the Atmel AT89C55 and AT89LV55 microcontrollers
437 // definitions for the Dallas DS5000
438 #ifdef MICROCONTROLLER_DS5000
439 #ifdef MICROCONTROLLER_DEFINED
440 #define MCS51REG_ERROR
442 #ifndef MICROCONTROLLER_DEFINED
443 #define MICROCONTROLLER_DEFINED
445 #ifdef MCS51REG_ENABLE_WARNINGS
446 #warning Selected HW: DS5000
452 #define PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
463 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
465 #define IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
466 #define MCON__PA3__PA2__PA1__PA0__RA32_8__ECE2__PAA__SL
472 // end of definitions for the Dallas DS5000
475 // definitions for the Dallas DS5001
476 #ifdef MICROCONTROLLER_DS5001
477 #ifdef MICROCONTROLLER_DEFINED
478 #define MCS51REG_ERROR
480 #ifndef MICROCONTROLLER_DEFINED
481 #define MICROCONTROLLER_DEFINED
483 #ifdef MCS51REG_ENABLE_WARNINGS
484 #warning Selected HW: DS5001
490 #define PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
501 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
503 #define IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
507 #define MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL
512 #define STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF
516 // end of definitions for the Dallas DS5001
519 // definitions for the Dallas DS80C320 and DS80C323 microcontrollers
520 #ifdef MICROCONTROLLER_DS80C32X
521 #ifdef MICROCONTROLLER_DEFINED
522 #define MCS51REG_ERROR
524 #ifndef MICROCONTROLLER_DEFINED
525 #define MICROCONTROLLER_DEFINED
527 #ifdef MCS51REG_ENABLE_WARNINGS
528 #warning Selected HW: Dallas DS80C320 or DS80C323
535 #define PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
547 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
549 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
553 // 8052 specific registers
554 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
559 // DS80C320 specific register
562 #define DPS__x__x__x__x__x__x__x__SEL
563 #define CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
564 #define EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
571 #define STATUS__PIP__HIP__LIP__x__x__x__x__x
573 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
574 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
576 #define EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
577 #define EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2
579 // end of definitions for the Dallas DS80C320 and DS80C323 microcontrollers
582 // definitions for the Dallas DS80C390
583 #ifdef MICROCONTROLLER_DS80C390
584 #ifdef MICROCONTROLLER_DEFINED
585 #define MCS51REG_ERROR
587 #ifndef MICROCONTROLLER_DEFINED
588 #define MICROCONTROLLER_DEFINED
590 #ifdef MCS51REG_ENABLE_WARNINGS
591 #warning Selected HW: Dallas DS80C390
598 #define PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
610 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
612 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
616 // 8052 specific registers
617 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
622 // DS80C390 specific register
626 #define DPS__ID1__ID0__TSL__x__x__x__x__SEL
627 #define CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
628 #define EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
636 #define ACON__x__x__x__x__x__SA__AM1__AM0
667 #define PMR__CD1__CD0__SWB__CTM__4X_2X__ALEOFF__x__x
668 #define STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
669 #define MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0
671 #define T2MOD__x__x__x__D13T1__D13T2__x__T2OE__DCEN
688 #define EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2
699 #define EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
706 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
708 // end of definitions for the Dallas DS80C390
710 // definitions for the Dallas DS89C420 microcontroller
711 #ifdef MICROCONTROLLER_DS89C420
712 #ifdef MICROCONTROLLER_DEFINED
713 #define MCS51REG_ERROR
715 #ifndef MICROCONTROLLER_DEFINED
716 #define MICROCONTROLLER_DEFINED
718 #ifdef MCS51REG_ENABLE_WARNINGS
719 #warning Selected HW: Dallas DS89C420
726 #define PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
738 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
740 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
744 // 8052 specific registers
745 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
750 // DS8XC420 specific registers
751 #define ACON__PAGEE__PAGES1__PAGES0__x__x__x__x__x
754 #define DPS__ID1__ID0__TSL__AID__x__x__x__SEL
755 #define CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
757 #define IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
758 #define IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
759 #define EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
760 #define PMR__CD1__CD0__SWB__CTM__4X_2X__ALEON__DME1__DME0
767 #define STATUS__PIS2__PIS1__PIS0__x__SPTA1__SPRA1__SPTA0__SPRA0
769 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
770 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
771 #define ROMSIZE__x__x__x__x__PRAME__RMS2__RMS1__RMS0
773 #define EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
774 #define EIP0__x__x__x__LPWDI__LPX5__LPX4__LPX3__LPX2
775 #define EIP1__x__x__x__MPWDI__MPX5__MPX4__MPX3__MPX2
776 #define FCNTL__FBUSY__FERR__x__x__FC3__FC2__FC1__FC0
778 // end of definitions for the Dallas DS89C420 microcontroller
780 // definitions for the Dallas DS87C520 and DS83C520 microcontrollers
781 #ifdef MICROCONTROLLER_DS8XC520
782 #ifdef MICROCONTROLLER_DEFINED
783 #define MCS51REG_ERROR
785 #ifndef MICROCONTROLLER_DEFINED
786 #define MICROCONTROLLER_DEFINED
788 #ifdef MCS51REG_ENABLE_WARNINGS
789 #warning Selected HW: Dallas DS87C520 or DS85C520
796 #define PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
808 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
810 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
814 // 8052 specific registers
815 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
820 // DS8XC520 specific registers
823 #define DPS__x__x__x__x__x__x__x__SEL
824 #define CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
825 #define EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
826 #define PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1__DME0
833 #define STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
835 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
836 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
838 #define ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0
841 #define EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
842 #define EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2
844 // end of definitions for the Dallas DS87C520 and DS83C520 microcontrollers
847 // definitions for the Philips P80C552 microcontroller
848 #ifdef MICROCONTROLLER_P80C552
849 #ifdef MICROCONTROLLER_DEFINED
850 #define MCS51REG_ERROR
852 #ifndef MICROCONTROLLER_DEFINED
853 #define MICROCONTROLLER_DEFINED
855 #ifdef MCS51REG_ENABLE_WARNINGS
856 #warning Selected HW: Philips P80C552
863 #define PCON__SMOD__x__x__WLE__GF1__GF0__PD__IDL
874 #define IE__EA__EAD__ES1__ES0__ET1__EX1__ET0__EX0
876 #define IP__x__PAD__PS1__PS0__PT1__PX1__PT0__PX0
880 // P80C552 specific register-names
881 #define S0BUF // same as SBUF, set in mcs51reg.h
882 #define S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI
883 // P80C552 specific registers
885 #define ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0
886 #define CTCON__CTN3__CTP3__CTN2__CTP2__CTN1__CTP1__CTN0__CTP0
901 #define IEN1__ET2__ECM2__ECM1__ECM0__ECT3__ECT2__ECT1__ECT0
902 #define IP1__PT2__PCM2__PCM1__PCM0__PCT3__PCT2__PCT1__PCT0
906 #define P1_EXT__SDA__SCL__RT2__T2__CT3I__CT2I__CT1I__CT0I
907 #define P4_AT_0XC0__CMT0__CMT1__CMSR5__CMSR4__CMSR3__CMSR2__CMSR1__CMSR0
909 #define RTE__TP47__TP46__RP45__RP44__RP43__RP42__RP41__RP40
910 #define S1ADR__x__x__x__x__x__x__x__GC
911 #define S1DAT_AT_0XDA
912 #define S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x
913 #define S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0
914 #define STE__TG47__TG46__SP45__SP44__SP43__SP42__SP41__SP40
917 #define TM2CON__T2IS1__T2IS0__T2ER__T2B0__T2P1__T2P0__T2MS1__T2MS0
918 #define TM2IR__T20V__CMI2__CMI1__CMI0__CTI3__CTI2__CTI1__CTI0
921 // end of definitions for the Philips P80C552 microcontroller
924 // definitions for the Philips P89C668
925 #ifdef MICROCONTROLLER_P89C668
926 #ifdef MICROCONTROLLER_DEFINED
927 #define MCS51REG_ERROR
929 #ifndef MICROCONTROLLER_DEFINED
930 #define MICROCONTROLLER_DEFINED
932 #ifdef MCS51REG_ENABLE_WARNINGS
933 #warning Selected HW: P89C668
936 #define P0_EXT__AD7__AD6__AD5__AD4__AD3__AD2__AD1__AD0
938 #define P1_EXT__SDA__SCL__CEX2__CEX1__CEX0__ECI__T2EX__T2
940 #define P2_EXT__AD15__AD14__AD13__AD12__AD11__AD10__AD9__AD8
942 #define P3_EXT__x__x__CEX4__CEX3__x__x__x__x
948 #define PCON__SMOD1__SMOD0__x__POF__GF1__GF0__PD__IDL
954 #define S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI
955 #define S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0
962 #define SADEN_AT_0XB9
963 #define S1IST_AT_0XDC
964 #define S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x
965 #define S1DAT_AT_0XDA
966 #define S1ADR__x__x__x__x__x__x__x__GC
968 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
969 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
974 #define IEN0__EA__EC__ES1__ES0__ET1__EX1__ET0__EX0
975 #define IEN1__x__x__x__x__x__x__x__ET2
976 #define IP__PT2__PPC__PS1__PS0__PT1__PX1__PT0__PX0
977 #define IPH__PT2H__PPCH__PS1H__PS0H__PT1H__PX1H__PT0H__PX0H
978 #define CCON__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0
979 #define CMOD__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
980 #define AUXR__x__x__x__x__x__x__EXTRAM__A0
981 #define AUXR1__x__x__ENBOOT__x__GF2__0__x__DPS
982 #define WDTRST_AT_0XA6
983 #define CCAPM0_AT_0XC2
984 #define CCAPM1_AT_0XC3
985 #define CCAPM2_AT_0XC4
986 #define CCAPM3_AT_0XC5
987 #define CCAPM4_AT_0XC6
988 #define CCAP0L_AT_0XEA
989 #define CCAP1L_AT_0XEB
990 #define CCAP2L_AT_0XEC
991 #define CCAP3L_AT_0XED
992 #define CCAP4L_AT_0XEE
995 #define CCAP0H_AT_0XFA
996 #define CCAP1H_AT_0XFB
997 #define CCAP2H_AT_0XFC
998 #define CCAP3H_AT_0XFD
999 #define CCAP4H_AT_0XFE
1001 // end of definitions for the Philips P89C668
1004 // definitions for the Infineon / Siemens SAB80509
1005 #ifdef MICROCONTROLLER_SAB80509
1006 #ifdef MICROCONTROLLER_DEFINED
1007 #define MCS51REG_ERROR
1009 #ifndef MICROCONTROLLER_DEFINED
1010 #define MICROCONTROLLER_DEFINED
1012 #ifdef MCS51REG_ENABLE_WARNINGS
1013 #warning Selected HW: Infineon / Siemens SAB80509
1015 // 8051 register set without IP
1020 #define PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
1030 #define S0CON__SM0__SM1__SM20__REN0__TB80__RB80__TI0__RI0
1031 #define IEN2__SAB80517
1034 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
1035 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
1039 #define IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
1040 #define IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
1056 #define S1CON_AT_0X9B
1059 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
1082 #define CTCOM_AT_0XE1
1133 // end of definitions for the Infineon / Siemens SAB80509
1136 // definitions for the Infineon / Siemens SAB80515 & SAB80535
1137 #ifdef MICROCONTROLLER_SAB80515
1138 #ifdef MICROCONTROLLER_DEFINED
1139 #define MCS51REG_ERROR
1141 #ifndef MICROCONTROLLER_DEFINED
1142 #define MICROCONTROLLER_DEFINED
1144 #ifdef MCS51REG_ENABLE_WARNINGS
1145 #warning Selected HW: Infineon / Siemens SAB80515 & SAB80535
1147 // 8051 register set without IP
1152 #define PCON__SMOD__x__x__x__x__x__x__x
1163 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
1168 // SAB80515 specific registers
1169 #define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
1170 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
1171 #define IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
1180 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
1187 #define DAPR__SAB80515
1192 // end of definitions for the Infineon / Siemens SAB80515
1195 // definitions for the Infineon / Siemens SAB80515A
1196 #ifdef MICROCONTROLLER_SAB80515A
1197 #ifdef MICROCONTROLLER_DEFINED
1198 #define MCS51REG_ERROR
1200 #ifndef MICROCONTROLLER_DEFINED
1201 #define MICROCONTROLLER_DEFINED
1203 #ifdef MCS51REG_ENABLE_WARNINGS
1204 #warning Selected HW: Infineon / Siemens SAB80515A
1206 // 8051 register set without IP
1211 #define PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
1222 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
1227 // SAB80515A specific registers
1228 #define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
1229 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
1230 #define IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
1231 #define IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
1240 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
1257 // end of definitions for the Infineon / Siemens SAB80515A
1260 // definitions for the Infineon / Siemens SAB80517
1261 #ifdef MICROCONTROLLER_SAB80517
1262 #ifdef MICROCONTROLLER_DEFINED
1263 #define MCS51REG_ERROR
1265 #ifndef MICROCONTROLLER_DEFINED
1266 #define MICROCONTROLLER_DEFINED
1268 #ifdef MCS51REG_ENABLE_WARNINGS
1269 #warning Selected HW: Infineon / Siemens SAB80517
1271 // 8051 register set without IP, SCON & SBUF
1276 #define PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
1287 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
1292 // SAB80517 specific registers
1293 #define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
1294 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
1295 #define IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
1296 #define IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
1297 #define IEN2__SAB80517
1327 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
1330 #define CTCOM_AT_0XE1
1338 #define DAPR__SAB80517
1353 #define S0CON__SM0__SM1__SM20__REN0__TB80__RB80__TI0__RI0
1357 #define S1CON_AT_0X9B
1364 // end of definitions for the Infineon / Siemens SAB80517
1367 // definitions for the Atmel T89C51RD2
1368 #ifdef MICROCONTROLLER_T89C51RD2
1369 #ifdef MICROCONTROLLER_DEFINED
1370 #define MCS51REG_ERROR
1372 #ifndef MICROCONTROLLER_DEFINED
1373 #define MICROCONTROLLER_DEFINED
1375 #ifdef MCS51REG_ENABLE_WARNINGS
1376 #warning Selected HW: T89C51RD2
1379 // 8051 register set
1384 #define PCON__SMOD1__SMOD0__x__POF__GF1__GF0__PD__IDL
1395 #define IE__EA__EC__ET2__ES__ET1__EX1__ET0__EX0
1398 #define IP__x__PPC__PT2__PS__PT1__PX1__PT0__PX0
1403 // 8052 register set
1404 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
1410 // T89C51RD2 register set
1411 #define P4_AT_0XC0__P4_7__P4_6__P4_5__P4_3__P4_2__P4_1__P4_0
1415 #define AUXR1__x__x__x__x__GF3__x__x__DPS
1416 #define WDTRST_AT_0XA6
1417 #define WDTPRG_AT_0XA7
1418 #define AUXR__x__x__M0__x__XRS1__XRS0__EXTRAM__A0
1419 #define IPH__x__PPCH__PT2H__PSH__PT1H__PX1H__PT0H__PX0H
1423 #define CKCON__X2__T0X2__T1X2__T2X2__SiX2__PcaX2__WdX2__x
1424 #define CCON__0xD8__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0
1425 #define CMOD__0xD9__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
1426 #define CCAPM0_AT_0XDA
1427 #define CCAPM1_AT_0XDB
1428 #define CCAPM2_AT_0XDC
1429 #define CCAPM3_AT_0XDD
1430 #define CCAPM4_AT_0XDE
1432 #define CCAP0L_AT_0XEA
1433 #define CCAP1L_AT_0XEB
1434 #define CCAP2L_AT_0XEC
1435 #define CCAP3L_AT_0XED
1436 #define CCAP4L_AT_0XEE
1438 #define CCAP0H_AT_0XFA
1439 #define CCAP1H_AT_0XFB
1440 #define CCAP2H_AT_0XFC
1441 #define CCAP3H_AT_0XFD
1442 #define CCAP4H_AT_0XFE
1443 #endif /* MICROCONTROLLER_T89C51RD2 */
1444 /* end of definition for the Atmel T89C51RD2 */
1447 /////////////////////////////////////////////////////////
1448 /// don't specify microcontrollers below this line! ///
1449 /////////////////////////////////////////////////////////
1452 // default microcontroller -> 8051
1453 // use default if no microcontroller specified
1454 #ifndef MICROCONTROLLER_DEFINED
1455 #define MICROCONTROLLER_DEFINED
1456 #ifdef MCS51REG_ENABLE_WARNINGS
1457 #warning No microcontroller defined!
1458 #warning Code generated for the 8051
1460 // 8051 register set
1465 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
1476 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
1478 #define IP__x__x__x__PS__PT1__PX1__PT0__PX0
1483 // end of definitions for the default microcontroller
1486 #ifdef MCS51REG_ERROR
1487 #error Two or more microcontrollers defined!
1490 #ifdef MCS51REG_EXTERNAL_ROM
1491 #ifndef MCS51REG_UNDEFINE_P0
1492 #define MCS51REG_UNDEFINE_P0
1494 #ifndef MCS51REG_UNDEFINE_P2
1495 #define MCS51REG_UNDEFINE_P2
1499 #ifdef MCS51REG_EXTERNAL_RAM
1500 #ifndef MCS51REG_UNDEFINE_P0
1501 #define MCS51REG_UNDEFINE_P0
1503 #ifndef MCS51REG_UNDEFINE_P2
1504 #define MCS51REG_UNDEFINE_P2
1508 #ifdef MCS51REG_UNDEFINE_P0
1512 #ifdef MCS51REG_UNDEFINE_P2
1516 ////////////////////////////////
1517 /// Register definitions ///
1518 /// (In alphabetical order) ///
1519 ////////////////////////////////
1526 #ifdef ACON__PAGEE__PAGES1__PAGES0__x__x__x__x__x
1527 #undef ACON__PAGEE__PAGES1__PAGES0__x__x__x__x__x
1528 sfr at 0x9D ACON ; // DS89C420 specific
1529 // Not directly accessible bits
1535 #ifdef ACON__x__x__x__x__x__SA__AM1__AM0
1536 #undef ACON__x__x__x__x__x__SA__AM1__AM0
1537 sfr at 0x9D ACON ; // DS89C390 specific
1538 // Not directly accessible bits
1546 sfr at 0xC6 ADCH ; // A/D converter high
1551 sfr at 0xD8 ADCON ; // A/D-converter control register SAB80515 specific
1562 // ADCON0 ... Infineon / Siemens also called this register ADCON in the User Manual
1565 sfr at 0xD8 ADCON0 ; // A/D-converter control register 0 SAB80515A &
1566 // Bit registers // SAB80517 specific
1575 // Not directly accessible ADCON0
1576 #define ADCON0_MX0 0x01
1577 #define ADCON0_MX1 0x02
1578 #define ADCON0_MX2 0x04
1579 #define ADCON0_ADM 0x08
1580 #define ADCON0_BSY 0x10
1581 #define ADCON0_ADEX 0x20
1582 #define ADCON0_CLK 0x40
1583 #define ADCON0_BD 0x80
1588 sfr at 0xDC ADCON1 ; // A/D-converter control register 1 SAB80515A & SAB80517 specific
1589 // Not directly accessible ADCON1
1590 #define ADCON1_MX0 0x01
1591 #define ADCON1_MX1 0x02
1592 #define ADCON1_MX2 0x04
1593 #define ADCON1_ADCL 0x80
1596 #ifdef ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0
1597 #undef ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0
1598 sfr at 0xC5 ADCON ; // A/D control, P80C552 specific
1599 // Not directly accessible Bits.
1606 #define ADC_0 0x40 // different name as ADC0 in P5
1607 #define ADC_1 0x80 // different name as ADC1 in P5
1612 sfr at 0xD9 ADDAT ; // A/D-converter data register SAB80515 specific
1617 sfr at 0xD9 ADDATH ; // A/D data high byte SAB80515A specific
1622 sfr at 0xDA ADDATL ; // A/D data low byte SAB80515A specific
1627 sfr at 0xEF ARCON ; // arithmetic control register SAB80517
1632 sfr at 0x9C AP ; // DS80C390
1635 #ifdef AUXR__x__x__x__x__x__x__EXTRAM__A0
1636 #undef AUXR__x__x__x__x__x__x__EXTRAM__A0
1637 // P89C668 specific, Auxilary
1639 // not bit addressable:
1644 #ifdef AUXR__x__x__M0__x__XRS1__XRS0__EXTRAM__A0
1645 #undef AUXR__x__x__M0__x__XRS1__XRS0__EXTRAM__A0
1657 sbit at 0xF0 BREG_F0 ;
1658 sbit at 0xF1 BREG_F1 ;
1659 sbit at 0xF2 BREG_F2 ;
1660 sbit at 0xF3 BREG_F3 ;
1661 sbit at 0xF4 BREG_F4 ;
1662 sbit at 0xF5 BREG_F5 ;
1663 sbit at 0xF6 BREG_F6 ;
1664 sbit at 0xF7 BREG_F7 ;
1667 #ifdef AUXR1__x__x__x__x__GF3__x__x__DPS
1668 #undef AUXR1__x__x__x__x__GF3__x__x__DPS
1674 #ifdef AUXR1__x__x__ENBOOT__x__GF2__0__x__DPS
1675 #undef AUXR1__x__x__ENBOOT__x__GF2__0__x__DPS
1676 // P89C668 specific, Auxilary 1
1680 #define ALWAYS_ZERO 0x04
1687 // Not directly accessible bits
1698 sfr at 0xA3 C0C ; // DS80C390 specific
1699 // Not directly accessible bits
1712 sfr at 0xA5 C0IR ; // DS80C390 specific
1713 // Not directly accessible bits
1726 sfr at 0xAB C0M1C ; // DS80C390 specific
1727 // Not directly accessible bits
1729 #define ROW_TIH 0x02
1740 sfr at 0xAC C0M2C ; // DS80C390 specific
1745 sfr at 0xAD C0M3C ; // DS80C390 specific
1750 sfr at 0xAE C0M4C ; // DS80C390 specific
1755 sfr at 0xAF C0M5C ; // DS80C390 specific
1760 sfr at 0xB3 C0M6C ; // DS80C390 specific
1765 sfr at 0xB4 C0M7C ; // DS80C390 specific
1770 sfr at 0xB5 C0M8C ; // DS80C390 specific
1775 sfr at 0xB6 C0M9C ; // DS80C390 specific
1780 sfr at 0xB7 C0M10C ; // DS80C390 specific
1785 sfr at 0xBB C0M11C ; // DS80C390 specific
1790 sfr at 0xBC C0M12C ; // DS80C390 specific
1795 sfr at 0xBD C0M13C ; // DS80C390 specific
1800 sfr at 0xBE C0M14C ; // DS80C390 specific
1805 sfr at 0xBF C0M15C ; // DS80C390 specific
1810 sfr at 0xA7 C0RE ; // DS80C390 specific
1815 sfr at 0x96 C0RMS0 ; // DS80C390 specific
1820 sfr at 0x97 C0RMS1 ; // DS80C390 specific
1825 sfr at 0xA4 C0S ; // DS80C390 specific
1826 // Not directly accessible bits
1833 #define EC96_128 0x40
1839 sfr at 0xA6 C0TE ; // DS80C390 specific
1844 sfr at 0x9E C0TMA0 ; // DS80C390 specific
1849 sfr at 0x9F C0TMA1 ; // DS80C390 specific
1854 sfr at 0xE3 C1C ; // DS80C390 specific
1855 // Not directly accessible bits
1868 sfr at 0xE5 C1IR ; // DS80C390 specific
1869 // Not directly accessible bits
1882 sfr at 0xE7 C1RE ; // DS80C390 specific
1887 sfr at 0xEB C1M1C ; // DS80C390 specific
1892 sfr at 0xEC C1M2C ; // DS80C390 specific
1897 sfr at 0xED C1M3C ; // DS80C390 specific
1902 sfr at 0xEE C1M4C ; // DS80C390 specific
1907 sfr at 0xEF C1M5C ; // DS80C390 specific
1912 sfr at 0xF3 C1M6C ; // DS80C390 specific
1917 sfr at 0xF4 C1M7C ; // DS80C390 specific
1922 sfr at 0xF5 C1M8C ; // DS80C390 specific
1927 sfr at 0xF6 C1M9C ; // DS80C390 specific
1932 sfr at 0xF7 C1M10C ; // DS80C390 specific
1937 sfr at 0xFB C1M11C ; // DS80C390 specific
1942 sfr at 0xFC C1M12C ; // DS80C390 specific
1947 sfr at 0xFD C1M13C ; // DS80C390 specific
1952 sfr at 0xFE C1M14C ; // DS80C390 specific
1957 sfr at 0xFF C1M15C ; // DS80C390 specific
1962 sfr at 0xE4 C1S ; // DS80C390 specific
1963 // Not directly accessible bits
1976 sfr at 0xE6 C1TE ; // DS80C390 specific
1981 sfr at 0xD6 C1RSM0 ; // DS80C390 specific
1986 sfr at 0xD7 C1RSM1 ; // DS80C390 specific
1991 sfr at 0xDE C1TMA0 ; // DS80C390 specific
1996 sfr at 0xDF C1TMA1 ; // DS80C390 specific
2021 sfr at 0xC9 CC4EN ; // compare/capture 4 enable register SAB80517 specific
2024 #ifdef CCAP0H_AT_0XFA
2025 #undef CCAP0H_AT_0XFA
2026 sfr at 0xFA CCAP0H ;
2029 #ifdef CCAP1H_AT_0XFB
2030 #undef CCAP1H_AT_0XFB
2031 sfr at 0xFB CCAP1H ;
2034 #ifdef CCAP2H_AT_0XFC
2035 #undef CCAP2H_AT_0XFC
2036 sfr at 0xFC CCAP2H ;
2039 #ifdef CCAP3H_AT_0XFD
2040 #undef CCAP3H_AT_0XFD
2041 sfr at 0xFD CCAP3H ;
2044 #ifdef CCAP4H_AT_0XFE
2045 #undef CCAP4H_AT_0XFE
2046 sfr at 0xFE CCAP4H ;
2049 #ifdef CCAP0L_AT_0XEA
2050 #undef CCAP0L_AT_0XEA
2051 sfr at 0xEA CCAP0L ;
2054 #ifdef CCAP1L_AT_0XEB
2055 #undef CCAP1L_AT_0XEB
2056 sfr at 0xEB CCAP1L ;
2059 #ifdef CCAP2L_AT_0XEC
2060 #undef CCAP2L_AT_0XEC
2061 sfr at 0xEC CCAP2L ;
2064 #ifdef CCAP3L_AT_0XED
2065 #undef CCAP3L_AT_0XED
2066 sfr at 0xED CCAP3L ;
2069 #ifdef CCAP4L_AT_0XEE
2070 #undef CCAP4L_AT_0XEE
2071 sfr at 0xEE CCAP4L ;
2074 #ifdef CCAPM0_AT_0XC2
2075 #undef CCAPM0_AT_0XC2
2076 // P89C668 specific, Capture module:
2077 sfr at 0xC2 CCAPM0 ;
2080 #ifdef CCAPM0_AT_0XDA
2081 #undef CCAPM0_AT_0XDA
2082 sfr at 0xDA CCAPM0 ;
2092 #ifdef CCAPM1_AT_0XC3
2093 #undef CCAPM1_AT_0XC3
2094 sfr at 0xC3 CCAPM1 ;
2097 #ifdef CCAPM1_AT_0XDB
2098 #undef CCAPM1_AT_0XDB
2099 sfr at 0xDB CCAPM1 ;
2102 #ifdef CCAPM2_AT_0XC4
2103 #undef CCAPM2_AT_0XC4
2104 sfr at 0xC4 CCAPM2 ;
2107 #ifdef CCAPM2_AT_0XDC
2108 #undef CCAPM2_AT_0XDC
2109 sfr at 0x0DC CCAPM2 ;
2112 #ifdef CCAPM3_AT_0XC5
2113 #undef CCAPM3_AT_0XC5
2114 sfr at 0xC5 CCAPM3 ;
2117 #ifdef CCAPM3_AT_0XDD
2118 #undef CCAPM3_AT_0XDD
2119 sfr at 0x0DD CCAPM3 ;
2122 #ifdef CCAPM4_AT_0XDE
2123 #undef CCAPM4_AT_0XDE
2124 sfr at 0x0DE CCAPM4 ;
2127 #ifdef CCAPM4_AT_0XC6
2128 #undef CCAPM4_AT_0XC6
2129 sfr at 0xC6 CCAPM4 ;
2134 sfr at 0xC1 CCEN ; // compare/capture enable register SAB80515 specific
2139 sfr at 0xC3 CCH1 ; // compare/capture register 1, high byte SAB80515 specific
2144 sfr at 0xC5 CCH2 ; // compare/capture register 2, high byte SAB80515 specific
2149 sfr at 0xC7 CCH3 ; // compare/capture register 3, high byte SAB80515 specific
2154 sfr at 0xCF CCH4 ; // compare/capture register 4, high byte SAB80515 specific
2159 sfr at 0xC2 CCL1 ; // compare/capture register 1, low byte SAB80515 specific
2164 sfr at 0xC4 CCL2 ; // compare/capture register 2, low byte SAB80515 specific
2169 sfr at 0xC6 CCL3 ; // compare/capture register 3, low byte SAB80515 specific
2174 sfr at 0xCE CCL4 ; // compare/capture register 4, low byte SAB80515 specific
2177 #ifdef CCON__0xD8__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0
2178 #undef CCON__0xD8__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0
2179 sfr at 0xD8 CCON ; // T89C51RD2 specific register
2190 #ifdef CCON__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0
2191 #undef CCON__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0
2192 // P89C668 specific, PCA Counter control:
2215 #ifdef CMOD__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
2216 #undef CMOD__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
2217 // P89C668 specific, PCA Counter mode:
2219 // not bit addressable:
2227 #ifdef CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
2228 #undef CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
2229 sfr at 0x8E CKCON ; // DS80C320 & DS80C390 specific
2230 // Not directly accessible Bits.
2241 #ifdef CKCON__X2__T0X2__T1X2__T2X2__SiX2__PcaX2__WdX2__x
2242 #undef CKCON__X2__T0X2__T1X2__T2X2__SiX2__PcaX2__WdX2__x
2255 sfr at 0x96 CKMOD ; // DS89C420 specific
2256 // Not directly accessible Bits.
2274 sfr at 0xF6 CMEN ; // compare enable register SAB80517 specific
2279 sfr at 0xD3 CMH0 ; // compare register 0 high byte SAB80517 specific
2284 sfr at 0xD5 CMH1 ; // compare register 1 high byte SAB80517 specific
2289 sfr at 0xD7 CMH2 ; // compare register 2 high byte SAB80517 specific
2294 sfr at 0xE3 CMH3 ; // compare register 3 high byte SAB80517 specific
2299 sfr at 0xE5 CMH4 ; // compare register 4 high byte SAB80517 specific
2304 sfr at 0xE7 CMH5 ; // compare register 5 high byte SAB80517 specific
2309 sfr at 0xF3 CMH6 ; // compare register 6 high byte SAB80517 specific
2314 sfr at 0xF5 CMH7 ; // compare register 7 high byte SAB80517 specific
2319 sfr at 0xC9 CMH0 ; // Compare high 0, P80C552 specific
2324 sfr at 0xCA CMH1 ; // Compare high 1, P80C552 specific
2329 sfr at 0xCB CMH2 ; // Compare high 2, P80C552 specific
2334 sfr at 0xD2 CML0 ; // compare register 0 low byte SAB80517 specific
2339 sfr at 0xD4 CML1 ; // compare register 1 low byte SAB80517 specific
2344 sfr at 0xD6 CML2 ; // compare register 2 low byte SAB80517 specific
2349 sfr at 0xE2 CML3 ; // compare register 3 low byte SAB80517 specific
2354 sfr at 0xE4 CML4 ; // compare register 4 low byte SAB80517 specific
2359 sfr at 0xE6 CML5 ; // compare register 5 low byte SAB80517 specific
2364 sfr at 0xF2 CML6 ; // compare register 6 low byte SAB80517 specific
2369 sfr at 0xF4 CML7 ; // compare register 7 low byte SAB80517 specific
2374 sfr at 0xA9 CML0 ; // Compare low 0, P80C552 specific
2379 sfr at 0xAA CML1 ; // Compare low 1, P80C552 specific
2384 sfr at 0xAB CML2 ; // Compare low 2, P80C552 specific
2387 #ifdef CMOD__0xD9__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
2388 #undef CMOD__0xD9__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
2399 sfr at 0xF7 CMSEL ; // compare input select SAB80517
2404 sfr at 0xA4 COMCLRH;
2409 sfr at 0xA3 COMCLRL;
2414 sfr at 0xA2 COMSETH;
2419 sfr at 0xA1 COMSETL;
2424 sfr at 0xCE COR ; // Dallas DS80C390 specific
2437 sfr at 0xC1 CRC ; // Dallas DS5001 specific
2448 sfr at 0xCB CRCH ; // compare/reload/capture register, high byte SAB80515 specific
2453 sfr at 0xC3 CRCHIGH ; // DS5001 specific
2458 sfr at 0xCA CRCL ; // compare/reload/capture register, low byte SAB80515 specific
2463 sfr at 0xC2 CRCLOW ; // DS5001 specific
2471 #ifdef CTCOM_AT_0XE1
2472 #undef CTCOM_AT_0XE1
2473 sfr at 0xE1 CTCON ; // com.timer control register SAB80517
2476 #ifdef CTCON__CTN3__CTP3__CTN2__CTP2__CTN1__CTP1__CTN0__CTP0
2477 #undef CTCON__CTN3__CTP3__CTN2__CTP2__CTN1__CTP1__CTN0__CTP0
2478 sfr at 0xEB CTCON ; // Capture control, P80C552 specific
2479 // Not directly accessible Bits.
2492 sfr at 0xCC CTH0 ; // Capture high 0, P80C552 specific
2497 sfr at 0xCD CTH1 ; // Capture high 1, P80C552 specific
2502 sfr at 0xCE CTH2 ; // Capture high 2, P80C552 specific
2507 sfr at 0xCF CTH3 ; // Capture high 3, P80C552 specific
2512 sfr at 0xAC CTL0 ; // Capture low 0, P80C552 specific
2517 sfr at 0xAD CTL1 ; // Capture low 1, P80C552 specific
2522 sfr at 0xAE CTL2 ; // Capture low 2, P80C552 specific
2527 sfr at 0xAF CTL3 ; // Capture low 3, P80C552 specific
2532 sfr at 0xDF CTRELH ; // com.timer rel register high byte SAB80517
2537 sfr at 0xDE CTRELL ; // com.timer rel register low byte SAB80517
2540 #ifdef DAPR__SAB80515
2541 #undef DAPR__SAB80515
2542 sfr at 0xDA DAPR ; // D/A-converter program register SAB80515 specific
2545 #ifdef DAPR__SAB80517
2546 #undef DAPR__SAB80517
2547 sfr at 0xDA DAPR ; // D/A-converter program register SAB80517 specific
2553 sfr at 0x83 DP0H ; // Alternate name for AT89S53
2558 sfr at 0x85 DPH1 ; // DS80C320 specific
2559 sfr at 0x85 DP1H ; // Alternate name for AT89S53
2564 sfr at 0x82 DPL ; // Alternate name for AT89S53
2570 sfr at 0x84 DPL1 ; // DS80C320 specific
2571 sfr at 0x84 DP1L ; // Alternate name for AT89S53
2574 #ifdef DPS__x__x__x__x__x__x__x__SEL
2575 #undef DPS__x__x__x__x__x__x__x__SEL
2577 // Not directly accessible DPS Bit. DS80C320 & DPS8XC520 specific
2581 #ifdef DPS__ID1__ID0__TSL__x__x__x__x__SEL
2582 #undef DPS__ID1__ID0__TSL__x__x__x__x__SEL
2584 // Not directly accessible DPS Bit. DS89C390 specific
2591 #ifdef DPS__ID1__ID0__TSL__AID__x__x__x__SEL
2592 #undef DPS__ID1__ID0__TSL__AID__x__x__x__SEL
2594 // Not directly accessible DPS Bit. DS89C420 specific
2604 sfr at 0x92 DPSEL ; // data pointer select register SAB80517
2609 sfr at 0x93 DPX1 ; // DS80C390 specific
2614 sfr at 0x95 DPX1 ; // DS80C390 specific
2639 #ifdef EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
2640 #undef EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
2642 // Bit registers DS80C320 specific
2650 #ifdef EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2
2651 #undef EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2
2653 // Bit registers DS80C390 specific
2661 sbit at 0xEF CANBIE ;
2664 #ifdef EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2
2665 #undef EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2
2667 // Bit registers DS80C320 specific
2675 #ifdef EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
2676 #undef EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
2678 // Bit registers DS80C320 specific
2686 sbit at 0xFF CANBIP ;
2689 #ifdef EIP0__x__x__x__LPWDI__LPX5__LPX4__LPX3__LPX2
2690 #undef EIP0__x__x__x__LPWDI__LPX5__LPX4__LPX3__LPX2
2692 // Bit registers DS89C420 specific
2697 sbit at 0xFC LPWDI ;
2700 #ifdef EIP1__x__x__x__MPWDI__MPX5__MPX4__MPX3__MPX2
2701 #undef EIP1__x__x__x__MPWDI__MPX5__MPX4__MPX3__MPX2
2703 // Not directly accessible Bits DS89C420 specific
2714 // Not directly accessible Bits DS80C390 specific
2719 #ifdef EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
2720 #undef EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
2722 // Not directly accessible EXIF Bits DS80C320 specific
2732 #ifdef EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
2733 #undef EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
2735 // Not directly accessible EXIF Bits DS87C520 specific
2746 #ifdef EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
2747 #undef EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
2749 // Not directly accessible EXIF Bits DS80C390 & DS89C420 specific
2760 #ifdef FCNTL__FBUSY__FERR__x__x__FC3__FC2__FC1__FC0
2761 #undef FCNTL__FBUSY__FERR__x__x__FC3__FC2__FC1__FC0
2763 // Not directly accessible DS89C420 specific
2796 #ifdef IE__EA__x__x__ES__ET1__EX1__ET0__EX0
2797 #undef IE__EA__x__x__ES__ET1__EX1__ET0__EX0
2808 #ifdef IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
2809 #undef IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
2817 sbit at 0xAD ET2 ; // Enable timer2 interrupt
2821 #ifdef IE__EA__EAD__ES1__ES0__ET1__EX1__ET0__EX0
2822 #undef IE__EA__EAD__ES1__ES0__ET1__EX1__ET0__EX0
2823 sfr at 0xA8 IE ; // same as IEN0 - Interrupt enable 0, P80C552 specific
2824 sfr at 0xA8 IEN0 ; // alternate name
2836 #ifdef IE__EA__EC__ET2__ES__ET1__EX1__ET0__EX0
2837 #undef IE__EA__EC__ET2__ES__ET1__EX1__ET0__EX0
2849 #ifdef IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
2850 #undef IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
2858 sbit at 0xAC ES0 ; // Alternate name
2859 sbit at 0xAD ET2 ; // Enable timer2 interrupt
2864 #ifdef IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
2865 #undef IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
2867 sfr at 0xA8 IEN0 ; // Alternate name
2868 // Bit registers for the SAB80515 and compatible IE
2875 sbit at 0xAD ET2 ; // Enable timer 2 overflow SAB80515 specific
2876 sbit at 0xAE WDT ; // watchdog timer reset - SAB80515 specific
2878 sbit at 0xAF EAL ; // EA as called by Infineon / Siemens
2881 #ifdef IEN0__EA__EC__ES1__ES0__ET1__EX1__ET0__EX0
2882 #undef IEN0__EA__EC__ES1__ES0__ET1__EX1__ET0__EX0
2896 #ifdef IEN1__x__x__x__x__x__x__x__ET2
2897 #undef IEN1__x__x__x__x__x__x__x__ET2
2898 // P89C668 specific bit registers
2904 #ifdef IEN1__ET2__ECM2__ECM1__ECM0__ECT3__ECT2__ECT1__ECT0
2905 #undef IEN1__ET2__ECM2__ECM1__ECM0__ECT3__ECT2__ECT1__ECT0
2906 sfr at 0xE8 IEN1 ; // Interrupt enable 1, P80C552 specific
2918 #ifdef IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
2919 #undef IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
2920 sfr at 0xB8 IEN1 ; // interrupt enable register - SAB80515 specific
2922 sbit at 0xB8 EADC ; // A/D converter interrupt enable
2928 sbit at 0xBE SWDT ; // watchdog timer start/reset
2929 sbit at 0xBF EXEN2 ; // timer2 external reload interrupt enable
2932 #ifdef IEN2__SAB80517
2933 #undef IEN2__SAB80517
2934 sfr at 0x9A IEN2 ; // interrupt enable register 2 SAB80517
2942 #ifdef IP__x__x__x__PS__PT1__PX1__PT0__PX0
2943 #undef IP__x__x__x__PS__PT1__PX1__PT0__PX0
2953 #ifdef IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
2954 #undef IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
2962 sbit at 0xBC PS0 ; // alternate name
2966 #ifdef IP__x__PAD__PS1__PS0__PT1__PX1__PT0__PX0
2967 #undef IP__x__PAD__PS1__PS0__PT1__PX1__PT0__PX0
2968 sfr at 0xB8 IP ; // Interrupt priority 0, P80C552 specific
2969 sfr at 0xB8 IP0 ; // alternate name
2980 #ifdef IP__x__PPC__PT2__PS__PT1__PX1__PT0__PX0
2981 #undef IP__x__PPC__PT2__PS__PT1__PX1__PT0__PX0
2993 #ifdef IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
2994 #undef IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
3006 #ifdef IP__PT2__PPC__PS1__PS0__PT1__PX1__PT0__PX0
3007 #undef IP__PT2__PPC__PS1__PS0__PT1__PX1__PT0__PX0
3008 // P89C668 specific:
3021 #ifdef IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
3022 #undef IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
3033 #ifdef IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
3034 #undef IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
3035 sfr at 0xA9 IP0 ; // interrupt priority register SAB80515 specific
3036 // Not directly accessible IP0 bits
3046 #ifdef IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
3047 #undef IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
3048 sfr at 0xB8 IP0 ; // interrupt priority register DS89C420 specific
3059 #ifdef IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
3060 #undef IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
3061 sfr at 0xB9 IP1 ; // interrupt priority register SAB80515 specific
3062 // Not directly accessible IP1 bits
3071 #ifdef IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
3072 #undef IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
3073 sfr at 0xB1 IP1 ; // interrupt priority register DS89C420 specific
3074 // Not directly accessible IP1 bits
3084 #ifdef IP1__PT2__PCM2__PCM1__PCM0__PCT3__PCT2__PCT1__PCT0
3085 #undef IP1__PT2__PCM2__PCM1__PCM0__PCT3__PCT2__PCT1__PCT0
3086 sfr at 0xF8 IP1 ; // Interrupt priority 1, P80C552 specific
3098 #ifdef IPH__x__PPCH__PT2H__PSH__PT1H__PX1H__PT0H__PX0H
3099 #undef IPH__x__PPCH__PT2H__PSH__PT1H__PX1H__PT0H__PX0H
3110 #ifdef IPH__PT2H__PPCH__PS1H__PS0H__PT1H__PX1H__PT0H__PX0H
3111 #undef IPH__PT2H__PPCH__PS1H__PS0H__PT1H__PX1H__PT0H__PX0H
3112 // P89C668 specific:
3114 // not bit addressable:
3127 sfr at 0xC0 IRCON ; // interrupt control register - SAB80515 specific
3129 sbit at 0xC0 IADC ; // A/D converter irq flag
3130 sbit at 0xC1 IEX2 ; // external interrupt edge detect flag
3135 sbit at 0xC6 TF2 ; // timer 2 owerflow flag
3136 sbit at 0xC7 EXF2 ; // timer2 reload flag
3141 sfr at 0xC0 IRCON0 ; // interrupt control register - SAB80515 specific
3143 sbit at 0xC0 IADC ; // A/D converter irq flag
3144 sbit at 0xC1 IEX2 ; // external interrupt edge detect flag
3149 sbit at 0xC6 TF2 ; // timer 2 owerflow flag
3150 sbit at 0xC7 EXF2 ; // timer2 reload flag
3155 sfr at 0xD1 IRCON1 ; // interrupt control register - SAB80515 specific
3165 sfr at 0xD3 MA ; // DS80C390
3170 sfr at 0xD4 MB ; // DS80C390
3175 sfr at 0xD5 MC ; // DS80C390
3180 sfr at 0xD1 MCNT0 ; // DS80C390
3193 sfr at 0xD2 MCNT1 ; // DS80C390
3199 #ifdef MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0
3200 #undef MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0
3201 sfr at 0xC6 MCON ; // DS80C390
3211 #ifdef MCON__PA3__PA2__PA1__PA0__RA32_8__ECE2__PAA__SL
3212 #undef MCON__PA3__PA2__PA1__PA0__RA32_8__ECE2__PAA__SL
3213 sfr at 0xC6 MCON ; // DS5000
3224 #ifdef MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL
3225 #undef MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL
3226 sfr at 0xC6 MCON ; // DS5001
3239 sfr at 0xE9 MD0 ; // MUL / DIV register 0 SAB80517
3244 sfr at 0xEA MD1 ; // MUL / DIV register 1 SAB80517
3249 sfr at 0xEB MD2 ; // MUL / DIV register 2 SAB80517
3254 sfr at 0xEC MD3 ; // MUL / DIV register 3 SAB80517
3259 sfr at 0xED MD4 ; // MUL / DIV register 4 SAB80517
3264 sfr at 0xEE MD5 ; // MUL / DIV register 5 SAB80517
3269 sfr at 0xEA MXAX ; // Dallas DS80C390
3286 #ifdef P0_EXT__AD7__AD6__AD5__AD4__AD3__AD2__AD1__AD0
3287 #undef P0_EXT__AD7__AD6__AD5__AD4__AD3__AD2__AD1__AD0
3288 // P89C668 alternate names for bits in P0
3313 #ifdef P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
3314 #undef P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
3315 // P1 alternate functions
3326 #ifdef P1_EXT__SDA__SCL__CEX2__CEX1__CEX0__ECI__T2EX__T2
3327 #undef P1_EXT__SDA__SCL__CEX2__CEX1__CEX0__ECI__T2EX__T2
3328 // P89C669 alternate names for bits at P1
3329 // P1_EXT__SDA__SCL__CEX2__CEX1__CEX0__ECI__T2EX__T2
3340 #ifdef P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
3341 sbit at 0x90 INT3_CC0 ; // P1 alternate functions - SAB80515 specific
3342 sbit at 0x91 INT4_CC1 ;
3343 sbit at 0x92 INT5_CC2 ;
3344 sbit at 0x93 INT6_CC3 ;
3347 sbit at 0x96 CLKOUT ;
3351 #ifdef P1_EXT__CT0I__CT1I__CT2I__CT3I__T2__RT2__SCL__SDA
3352 #undef P1_EXT__CT0I__CT1I__CT2I__CT3I__T2__RT2__SCL__SDA
3354 sbit at 0x90 CT0I ; // Port 1 alternate functions, P80C552 specific
3364 #ifdef P1_EXT__x__x__x__x__x__x__T2EX__T2
3365 #undef P1_EXT__x__x__x__x__x__x__T2EX__T2
3366 // P1 alternate functions
3385 #ifdef P2_EXT__AD15__AD14__AD13__AD12__AD11__AD10__AD9__AD8
3386 #undef P2_EXT__AD15__AD14__AD13__AD12__AD11__AD10__AD9__AD8
3387 // P89C668 specific bit registers at P2:
3408 #ifndef MCS51REG_EXTERNAL_RAM
3421 #ifndef MCS51REG_EXTERNAL_RAM
3427 #ifdef P3_EXT__x__x__CEX4__CEX3__x__x__x__x
3428 #undef P3_EXT__x__x__CEX4__CEX3__x__x__x__x
3429 // P89C668 specific bit registers at P3 (alternate names)
3436 sfr at 0x80 P4 ; // Port 4 - DS80C390
3448 #ifdef P4_AT_0XC0__CMT0__CMT1__CMSR5__CMSR4__CMSR3__CMSR2__CMSR1__CMSR0
3449 #undef P4_AT_0XC0__CMT0__CMT1__CMSR5__CMSR4__CMSR3__CMSR2__CMSR1__CMSR0
3450 sfr at 0xC0 P4 ; // Port 4, P80C552 specific
3452 sbit at 0xC0 CMSR0 ;
3453 sbit at 0xC1 CMSR1 ;
3454 sbit at 0xC2 CMSR2 ;
3455 sbit at 0xC3 CMSR3 ;
3456 sbit at 0xC4 CMSR4 ;
3457 sbit at 0xC5 CMSR5 ;
3462 #ifdef P4_AT_0XC0__P4_7__P4_6__P4_5__P4_3__P4_2__P4_1__P4_0
3463 #undef P4_AT_0XC0__P4_7__P4_6__P4_5__P4_3__P4_2__P4_1__P4_0
3464 sfr at 0xC0 P4 ; // Port 4, T89C51 specific
3478 sfr at 0xE8 P4 ; // Port 4 - SAB80515 & compatible microcontrollers
3492 sfr at 0x92 P4CNT ; // DS80C390
3493 // Not directly accessible bits
3494 #define P4CNT_0 0x01
3495 #define P4CNT_1 0x02
3496 #define P4CNT_2 0x04
3497 #define P4CNT_3 0x08
3498 #define P4CNT_4 0x10
3499 #define P4CNT_5 0x20
3505 sfr at 0xA1 P5 ; // Port 5 - DS80C390
3510 sfr at 0xE8 P5 ; // Port 5 - T89C51RD2
3524 sfr at 0xA2 P5CNT ; // DS80C390
3525 // Not directly accessible bits
3526 #define P5CNT_0 0x01
3527 #define P5CNT_1 0x02
3528 #define P5CNT_2 0x04
3532 #define SBCAN0BA 0x40
3533 #define SBCAN1BA 0x80
3538 sfr at 0xC4 P5 ; // Port 5, P80C552 specific
3539 // Not directly accessible Bits.
3552 sfr at 0xF8 P5 ; // Port 5 - SAB80515 & compatible microcontrollers
3566 sfr at 0xDB P6 ; // Port 6 - SAB80515 & compatible microcontrollers
3571 sfr at 0xFA P6 ; // Port 6 - SAB80517 specific
3576 sfr at 0xDB P7 ; // Port 7 - SAB80517 specific
3581 sfr at 0xDD P8 ; // Port 6 - SAB80517 specific
3589 #ifdef PCON__SMOD__x__x__x__x__x__x__x
3590 #undef PCON__SMOD__x__x__x__x__x__x__x
3592 // Not directly accessible PCON bits
3596 #ifdef PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
3597 #undef PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
3599 // Not directly accessible PCON bits
3607 #ifdef PCON__SMOD__x__x__WLE__GF1__GF0__PD__IDL
3608 #undef PCON__SMOD__x__x__WLE__GF1__GF0__PD__IDL
3609 sfr at 0x87 PCON ; // PCON, P80C552 specific
3610 // Not directly accessible Bits.
3612 #define IDLE 0x01 /* same as IDL */
3620 #ifdef PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
3621 #undef PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
3623 // Not directly accessible PCON bits
3625 #define IDLE 0x01 /* same as IDL */
3627 #define PDE 0x02 /* same as PD */
3632 #define PCON_IDLE 0x01
3633 #define PCON_PDE 0x02
3634 #define PCON_GF0 0x04
3635 #define PCON_GF1 0x08
3636 #define PCON_IDLS 0x20
3637 #define PCON_PDS 0x40
3638 #define PCON_SMOD 0x80
3641 #ifdef PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
3642 #undef PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
3644 // Not directly accessible PCON bits
3646 #define IDLE 0x01 /* same as IDL */
3656 #ifdef PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
3657 #undef PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
3659 // Not directly accessible PCON bits
3661 #define IDLE 0x01 /* same as IDL */
3669 #ifdef PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
3670 #undef PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
3672 // Not directly accessible PCON bits
3674 #define IDLE 0x01 /* same as IDL */
3682 #define SMOD_0 0x80 /* same as SMOD */
3685 #ifdef PCON__SMOD1__SMOD0__x__POF__GF1__GF0__PD__IDL
3686 #undef PCON__SMOD1__SMOD0__x__POF__GF1__GF0__PD__IDL
3697 #ifdef PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1__DME0
3698 #undef PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1__DME0
3699 sfr at 0xC4 PMR ; // DS87C520, DS83C520
3700 // Not directly accessible bits
3710 #ifdef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEOFF__x__x
3711 #undef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEOFF__x__x
3712 sfr at 0xC4 PMR ; // DS80C390
3713 // Not directly accessible bits
3722 #ifdef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEON__DME1__DME0
3723 #undef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEON__DME1__DME0
3724 sfr at 0xC4 PMR ; // DS89C420
3725 // Not directly accessible bits
3757 sfr at 0xFC PWM0 ; // PWM register 0, P80C552 specific
3762 sfr at 0xFD PWM1 ; // PWM register 1, P80C552 specific
3767 sfr at 0xFE PWMP ; // PWM prescaler, P80C552 specific
3772 sfr at 0xCB RCAP2H ;
3777 sfr at 0xCA RCAP2L ;
3785 #ifdef ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0
3786 #undef ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0
3787 sfr at 0xC2 ROMSIZE ; // DS87C520, DS83C520
3788 // Not directly accessible bits
3794 #ifdef ROMSIZE__x__x__x__x__PRAME__RMS2__RMS1__RMS0
3795 #undef ROMSIZE__x__x__x__x__PRAME__RMS2__RMS1__RMS0
3796 sfr at 0xC2 ROMSIZE ; // DS89C420
3797 // Not directly accessible bits
3804 #ifdef ROMSIZE__HBPF__BPF__TE__MOVCX__PRAME__RMS2__RMS1__RMS0
3805 #undef ROMSIZE__HBPF__BPF__TE__MOVCX__PRAME__RMS2__RMS1__RMS0
3806 sfr at 0xC2 ROMSIZE ; // DS87C520, DS83C520
3807 // Not directly accessible bits
3820 sfr at 0xD8 RPCTL ; // Dallas DS5001 specific
3822 sbit at 0xD9 RPCON ;
3827 sbit at 0xDF RNR_FLAG ;
3830 #ifdef RTE__TP47__TP46__RP45__RP44__RP43__RP42__RP41__RP40
3831 #undef RTE__TP47__TP46__RP45__RP44__RP43__RP42__RP41__RP40
3832 sfr at 0xEF RTE ; // Reset/toggle enable, P80C552 specific
3833 // Not directly accessible Bits.
3846 sfr at 0x99 S0BUF ; // serial channel 0 buffer register SAB80517 specific
3849 #ifdef S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI
3850 #undef S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI
3851 sfr at 0x98 S0CON ; // serial channel 0 control register P80C552 specific
3853 // Already defined in SCON
3854 //sbit at 0x98 RI0 ;
3855 //sbit at 0x99 TI0 ;
3856 //sbit at 0x9A RB8 ;
3857 //sbit at 0x9B TB8 ;
3858 //sbit at 0x9C REN ;
3859 //sbit at 0x9D SM2 ;
3860 //sbit at 0x9E SM1 ;
3861 //sbit at 0x9F SM0 ;
3864 #ifdef S0CON__SM0__SM1__SM20__REN0__TB80__RB80__TI0__RI0
3865 #undef S0CON__SM0__SM1__SM20__REN0__TB80__RB80__TI0__RI0
3866 // serial channel 0 buffer register SAB80517 specific(same as stock SCON)
3880 sfr at 0xAA S0RELL ; // serial channel 0 reload register low byte SAB80517 specific
3885 sfr at 0xBA S0RELH ; // serial channel 0 reload register high byte SAB80517 specific
3888 #ifdef S1ADR__x__x__x__x__x__x__x__GC
3889 #undef S1ADR__x__x__x__x__x__x__x__GC
3890 sfr at 0xDB S1ADR ; // Serial 1 address, P80C552 specific
3891 // Not directly accessible Bits.
3897 sfr at 0x9C S1BUF ; // serial channel 1 buffer register SAB80517 specific
3900 #ifdef S1CON_AT_0X9B
3901 #undef S1CON_AT_0X9B
3902 sfr at 0x9B S1CON ; // serial channel 1 control register SAB80517 specific
3905 #ifdef S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0
3906 #undef S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0
3907 sfr at 0xD8 S1CON ; // Serial 1 control, P80C552 specific
3908 sfr at 0xD8 SICON ; // sometimes called SICON
3920 #ifdef S1DAT_AT_0XDA
3921 #undef S1DAT_AT_0XDA
3922 sfr at 0xDA S1DAT ; // Serial 1 data, P80C552 specific
3923 sfr at 0xDA SIDAT ; // sometimes called SIDAT
3926 #ifdef S1IST_AT_0XDC
3927 #undef S1IST_AT_0XDC
3934 sfr at 0x9D S1RELL ; // serial channel 1 reload register low byte SAB80517 specific
3939 sfr at 0xBB S1RELH ; // serial channel 1 reload register high byte SAB80517 specific
3942 #ifdef S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x
3943 #undef S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x
3944 sfr at 0xD9 S1STA ; // Serial 1 status, P80C552 specific
3945 // Not directly accessible Bits.
3960 // DS80C320 specific
3961 sfr at 0xA9 SADDR0 ;
3966 // DS80C320 specific
3967 sfr at 0xAA SADDR1 ;
3970 #ifdef SADEN_AT_0XB9
3971 #undef SADEN_AT_0XB9
3977 // DS80C320 & DS80C390 specific
3978 sfr at 0xB9 SADEN0 ;
3983 // DS80C320 & DS80C390 specific
3984 sfr at 0xBA SADEN1 ;
3995 // DS80C320 & DS80C390 specific
4019 sbit at 0x9A RB8_0 ;
4020 sbit at 0x9B TB8_0 ;
4021 sbit at 0x9C REN_0 ;
4022 sbit at 0x9D SM2_0 ;
4023 sbit at 0x9E SM1_0 ;
4024 sbit at 0x9F SM0_0 ;
4026 sbit at 0x9F SM0_FE_0 ;
4031 // DS80C320 - 80C390 specific
4036 sbit at 0xC2 RB8_1 ;
4037 sbit at 0xC3 TB8_1 ;
4038 sbit at 0xC4 REN_1 ;
4039 sbit at 0xC5 SM2_1 ;
4040 sbit at 0xC6 SM1_1 ;
4041 sbit at 0xC7 SM0_1 ;
4043 sbit at 0xC7 SM0_FE_1 ;
4058 sfr at 0xD5 SPCR ; // AT89S53 specific
4059 // Not directly accesible bits
4072 sfr at 0x86 SPDR ; // AT89S53 specific
4073 // Not directly accesible bits
4086 sfr at 0xAA SPSR ; // AT89S53 specific
4087 // Not directly accesible bits
4094 sfr at 0xBA SRELH ; // Baudrate generator reload high
4099 sfr at 0xAA SRELL ; // Baudrate generator reload low
4102 #ifdef STATUS__PIP__HIP__LIP__x__x__x__x__x
4103 #undef STATUS__PIP__HIP__LIP__x__x__x__x__x
4104 // DS80C320 specific
4105 sfr at 0xC5 STATUS ;
4106 // Not directly accessible Bits. DS80C320 specific
4112 #ifdef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
4113 #undef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
4114 sfr at 0xC5 STATUS ; // DS80C390 specific
4115 // Not directly accessible Bits.
4125 #ifdef STATUS__PIS2__PIS1__PIS0__x__SPTA1__SPRA1__SPTA0__SPRA0
4126 #undef STATUS__PIS2__PIS1__PIS0__x__SPTA1__SPRA1__SPTA0__SPRA0
4127 sfr at 0xC5 STATUS ; // DS89C420 specific
4128 // Not directly accessible Bits.
4138 #ifdef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
4139 #undef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
4140 sfr at 0xC5 STATUS ; // DS80C390 specific
4141 // Not directly accessible Bits.
4151 #ifdef STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
4152 #undef STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
4153 sfr at 0xC5 STATUS ; // DS87C520 & DS83520specific
4154 // Not directly accessible Bits.
4165 #ifdef STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF
4166 #undef STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF
4167 sfr at 0xDA STATUS ; // DS5001specific
4168 // Not directly accessible Bits.
4179 #ifdef STE__TG47__TG46__SP45__SP44__SP43__SP42__SP41__SP40
4180 #undef STE__TG47__TG46__SP45__SP44__SP43__SP42__SP41__SP40
4181 sfr at 0xEE STE ; // Set enable, P80C552 specific
4182 // Not directly accessible Bits.
4195 sfr at 0xB1 SYSCON ; // XRAM Controller Access Control
4197 #define SYSCON_XMAP0 0x01
4198 #define SYSCON_XMAP1 0x02
4199 #define SYSCON_RMAP 0x10
4200 #define SYSCON_EALE 0x20
4205 sfr at 0xB2 SYSCON1;
4213 #ifdef T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
4214 #undef T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
4216 // Definitions for the 8052 compatible microcontrollers.
4218 sbit at 0xC8 CP_RL2 ;
4221 sbit at 0xCB EXEN2 ;
4227 sbit at 0xC8 T2CON_0 ;
4228 sbit at 0xC9 T2CON_1 ;
4229 sbit at 0xCA T2CON_2 ;
4230 sbit at 0xCB T2CON_3 ;
4231 sbit at 0xCC T2CON_4 ;
4232 sbit at 0xCD T2CON_5 ;
4233 sbit at 0xCE T2CON_6 ;
4234 sbit at 0xCF T2CON_7 ;
4237 #ifdef T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
4238 #undef T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
4240 // Definitions for the Infineon / Siemens SAB80515, SAB80515A, SAB80517
4251 sbit at 0xC8 T2CON_0 ;
4252 sbit at 0xC9 T2CON_1 ;
4253 sbit at 0xCA T2CON_2 ;
4254 sbit at 0xCB T2CON_3 ;
4255 sbit at 0xCC T2CON_4 ;
4256 sbit at 0xCD T2CON_5 ;
4257 sbit at 0xCE T2CON_6 ;
4258 sbit at 0xCF T2CON_7 ;
4261 #ifdef T2MOD__x__x__x__D13T1__D13T2__x__T2OE__DCEN
4262 #undef T2MOD__x__x__x__D13T1__D13T2__x__T2OE__DCEN
4263 // Definitions for the timer/counter 2 of the Atmel & Dallas microcontrollers
4265 // Not not directly accessible T2MOD bits
4272 #ifdef T2MOD__x__x__x__x__x__x__T2OE__DCEN
4273 #undef T2MOD__x__x__x__x__x__x__T2OE__DCEN
4274 // Definitions for the timer/counter 2 of the Atmel 89x52 microcontroller
4276 // Not not directly accessible T2MOD bits
4286 sfr at 0xFF T3 ; // Timer 3, P80C552 specific
4291 // DS500x, DS80C320 & DS80C390 specific
4342 // Not directly accessible TMOD bits
4346 #define T0_GATE 0x08
4350 #define T1_GATE 0x80
4352 #define T0_MASK 0x0F
4353 #define T1_MASK 0xF0
4356 #ifdef TM2CON__T2IS1__T2IS0__T2ER__T2B0__T2P1__T2P0__T2MS1__T2MS0
4357 #undef TM2CON__T2IS1__T2IS0__T2ER__T2B0__T2P1__T2P0__T2MS1__T2MS0
4358 sfr at 0xEA TM2CON ; // Timer 2 control, P80C552 specific
4359 // Not directly accessible Bits.
4370 #ifdef TM2IR__T20V__CMI2__CMI1__CMI0__CTI3__CTI2__CTI1__CTI0
4371 #undef TM2IR__T20V__CMI2__CMI1__CMI0__CTI3__CTI2__CTI1__CTI0
4372 sfr at 0xC8 TM2IR ; // Timer 2 int flag reg, P80C552 specific
4386 sfr at 0xED TMH2 ; // Timer high 2, P80C552 specific
4391 sfr at 0xEC TML2 ; // Timer low 2, P80C552 specific
4396 sfr at 0x96 WCON ; // AT89S53 specific
4397 // Not directly accesible bits
4408 // DS80C320 - 390, DS89C420, etc. specific
4418 sbit at 0xDF SMOD_1 ;
4421 #ifdef WDTPRG_AT_0XA7
4422 #undef WDTPRG_AT_0XA7
4423 sfr at 0xA7 WDTPRG ;
4424 #define WDTRPRG_S0 0x01
4425 #define WDTRPRG_S1 0x02
4426 #define WDTRPRG_S2 0x04
4431 sfr at 0x86 WDTREL ; // Watchdof Timer reload register
4434 #ifdef WDTRST_AT_0XA6
4435 #undef WDTRST_AT_0XA6
4436 sfr at 0xA6 WDTRST ;
4441 sfr at 0x91 XPAGE ; // Page Address Register for Extended On-Chip Ram - Infineon / Siemens SAB80515A specific
4444 /////////////////////////
4445 /// Interrupt vectors ///
4446 /////////////////////////
4448 // Interrupt numbers: address = (number * 8) + 3
4449 #define IE0_VECTOR 0 // 0x03 external interrupt 0
4450 #define TF0_VECTOR 1 // 0x0b timer 0
4451 #define IE1_VECTOR 2 // 0x13 external interrupt 1
4452 #define TF1_VECTOR 3 // 0x1b timer 1
4453 #define SI0_VECTOR 4 // 0x23 serial port 0
4455 #ifdef MICROCONTROLLER_AT89S53
4456 #define TF2_VECTOR 5 /* 0x2B timer 2 */
4457 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
4460 #ifdef MICROCONTROLLER_AT89X52
4461 #define TF2_VECTOR 5 /* 0x2B timer 2 */
4462 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
4465 #ifdef MICROCONTROLLER_AT89X55
4466 #define TF2_VECTOR 5 /* 0x2B timer 2 */
4467 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
4470 #ifdef MICROCONTROLLER_DS5000
4471 #define PFW_VECTOR 5 /* 0x2B */
4474 #ifdef MICROCONTROLLER_DS5001
4475 #define PFW_VECTOR 5 /* 0x2B */
4478 #ifdef MICROCONTROLLER_DS80C32X
4479 #define TF2_VECTOR 5 /* 0x2B */
4480 #define PFI_VECTOR 6 /* 0x33 */
4481 #define SIO1_VECTOR 7 /* 0x3B */
4482 #define IE2_VECTOR 8 /* 0x43 */
4483 #define IE3_VECTOR 9 /* 0x4B */
4484 #define IE4_VECTOR 10 /* 0x53 */
4485 #define IE5_VECTOR 11 /* 0x5B */
4486 #define WDI_VECTOR 12 /* 0x63 */
4489 #ifdef MICROCONTROLLER_DS89C420
4490 #define TF2_VECTOR 5 /* 0x2B */
4491 #define PFI_VECTOR 6 /* 0x33 */
4492 #define SIO1_VECTOR 7 /* 0x3B */
4493 #define IE2_VECTOR 8 /* 0x43 */
4494 #define IE3_VECTOR 9 /* 0x4B */
4495 #define IE4_VECTOR 10 /* 0x53 */
4496 #define IE5_VECTOR 11 /* 0x5B */
4497 #define WDI_VECTOR 12 /* 0x63 */
4500 #ifdef MICROCONTROLLER_DS8XC520
4501 #define TF2_VECTOR 5 /* 0x2B */
4502 #define PFI_VECTOR 6 /* 0x33 */
4503 #define SIO1_VECTOR 7 /* 0x3B */
4504 #define IE2_VECTOR 8 /* 0x43 */
4505 #define IE3_VECTOR 9 /* 0x4B */
4506 #define IE4_VECTOR 10 /* 0x53 */
4507 #define IE5_VECTOR 11 /* 0x5B */
4508 #define WDI_VECTOR 12 /* 0x63 */
4511 #ifdef MICROCONTROLLER_P80C552
4512 #define SIO1_VECTOR 5 // 0x2B SIO1 (I2C)
4513 #define CT0_VECTOR 6 // 0x33 T2 capture 0
4514 #define CT1_VECTOR 7 // 0x3B T2 capture 1
4515 #define CT2_VECTOR 8 // 0x43 T2 capture 2
4516 #define CT3_VECTOR 9 // 0x4B T2 capture 3
4517 #define ADC_VECTOR 10 // 0x53 ADC completion
4518 #define CM0_VECTOR 11 // 0x5B T2 compare 0
4519 #define CM1_VECTOR 12 // 0x63 T2 compare 1
4520 #define CM2_VECTOR 13 // 0x6B T2 compare 2
4521 #define TF2_VECTOR 14 // 0x73 T2 overflow
4524 #ifdef MICROCONTROLLER_P89C668
4525 #define SIO1_VECTOR 5 // 0x2b SIO1 (i2c)
4526 #define PCA_VECTOR 6 // 0x33 (Programmable Counter Array)
4527 #define TF2_VECTOR 7 // 0x3B (Timer 2)
4530 #ifdef MICROCONTROLLER_SAB80509
4531 #define RI0_VECTOR 4 // 0x23 serial port 0
4532 #define TI0_VECTOR 4 // 0x23 serial port 0
4533 #define TF2_VECTOR 5 // 0x2B timer 2
4534 #define EX2_VECTOR 5 // 0x2B external interrupt 2
4537 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt
4538 #define IEX2_VECTOR 9 // 0x4B external interrupt 2
4539 #define IEX3_VECTOR 10 // 0x53 external interrupt 3
4540 #define IEX4_VECTOR 11 // 0x5B external interrupt 4
4541 #define IEX5_VECTOR 12 // 0x63 external interrupt 5
4542 #define IEX6_VECTOR 13 // 0x6B external interrupt 6
4545 #define SI1_VECTOR 16 // 0x83 serial port 1
4546 #define RI1_VECTOR 16 // 0x83 serial port 1
4547 #define TI1_VECTOR 16 // 0x83 serial port 1
4549 #define ICM_VECTOR 18 // 0x93 compare registers CM0-CM7
4550 #define CTF_VECTOR 19 // 0x9B compare time overflow
4551 #define ICS_VECTOR 20 // 0xA3 compare register COMSET
4552 #define ICR_VECTOR 21 // 0xAB compare register COMCLR
4553 #define ICC_VECTOR 26 // 0xD3 compare event interrupt ICC10-ICC17
4554 #define CT1_VECTOR 27 // 0xDB compare timer 1 oveflow
4557 #ifdef MICROCONTROLLER_SAB80515
4558 #define TF2_VECTOR 5 // 0x2B timer 2
4559 #define EX2_VECTOR 5 // 0x2B external interrupt 2
4560 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt
4561 #define IEX2_VECTOR 9 // 0x4B external interrupt 2
4562 #define IEX3_VECTOR 10 // 0x53 external interrupt 3
4563 #define IEX4_VECTOR 11 // 0x5B external interrupt 4
4564 #define IEX5_VECTOR 12 // 0x63 external interrupt 5
4565 #define IEX6_VECTOR 13 // 0x6B external interrupt 6
4568 #ifdef MICROCONTROLLER_SAB80515A
4569 #define TF2_VECTOR 5 // 0x2B timer 2
4570 #define EX2_VECTOR 5 // 0x2B external interrupt 2
4571 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt
4572 #define IEX2_VECTOR 9 // 0x4B external interrupt 2
4573 #define IEX3_VECTOR 10 // 0x53 external interrupt 3
4574 #define IEX4_VECTOR 11 // 0x5B external interrupt 4
4575 #define IEX5_VECTOR 12 // 0x63 external interrupt 5
4576 #define IEX6_VECTOR 13 // 0x6B external interrupt 6
4579 #ifdef MICROCONTROLLER_SAB80517
4580 #define TF2_VECTOR 5 // 0x2B timer 2
4581 #define EX2_VECTOR 5 // 0x2B external interrupt 2
4582 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt
4583 #define IEX2_VECTOR 9 // 0x4B external interrupt 2
4584 #define IEX3_VECTOR 10 // 0x53 external interrupt 3
4585 #define IEX4_VECTOR 11 // 0x5B external interrupt 4
4586 #define IEX5_VECTOR 12 // 0x63 external interrupt 5
4587 #define IEX6_VECTOR 13 // 0x6B external interrupt 6
4590 #define SI1_VECTOR 16 // 0x83 serial port 1
4593 #define COMPARE_VECTOR 19 // 0x9B compare
4596 #ifdef MICROCONTORLLER_T89C51RD2
4597 #define TF2_VECTOR 5 /* 0x2B timer 2 */
4598 #define PCA_VECTOR 6 /* 0x33 Programmable Counter Array interrupt */
4599 #endif /* MICROCONTORLLER_T89C51RD2 */
4601 #endif // End of the header -> #ifndef MCS51REG_H