1 /*-------------------------------------------------------------------------
2 Register Declarations for the Cygnal/SiLabs C8051F326/7 Processor Range
4 Copyright (C) 2006 - Maarten Brock, sourceforge.brock@dse.nl
6 This library is free software; you can redistribute it and/or
7 modify it under the terms of the GNU Lesser General Public
8 License as published by the Free Software Foundation; either
9 version 2.1 of the License, or (at your option) any later version.
11 This library is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 Lesser General Public License for more details.
16 You should have received a copy of the GNU Lesser General Public
17 License along with this library; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------*/
26 __sfr __at (0x80) P0 ; /* PORT 0 */
27 __sfr __at (0x81) SP ; /* STACK POINTER */
28 __sfr __at (0x82) DPL ; /* DATA POINTER - LOW BYTE */
29 __sfr __at (0x83) DPH ; /* DATA POINTER - HIGH BYTE */
30 __sfr __at (0x87) PCON ; /* POWER CONTROL */
31 __sfr __at (0x88) TCON ; /* TIMER CONTROL */
32 __sfr __at (0x89) TMOD ; /* TIMER MODE */
33 __sfr __at (0x8A) TL0 ; /* TIMER 0 - LOW BYTE */
34 __sfr __at (0x8B) TL1 ; /* TIMER 1 - LOW BYTE */
35 __sfr __at (0x8C) TH0 ; /* TIMER 0 - HIGH BYTE */
36 __sfr __at (0x8D) TH1 ; /* TIMER 1 - HIGH BYTE */
37 __sfr __at (0x8E) CKCON ; /* CLOCK CONTROL */
38 __sfr __at (0x8F) PSCTL ; /* PROGRAM STORE R/W CONTROL */
39 __sfr __at (0x91) SBCON0 ; /* BAUDRATE GENERATOR 0 CONTROL */
40 __sfr __at (0x93) SBRLL0 ; /* BAUDRATE GENERATOR 0 RELOAD VALUE - LOW BYTE */
41 __sfr __at (0x94) SBRLH0 ; /* BAUDRATE GENERATOR 0 RELOAD VALUE - HIGH BYTE */
42 __sfr __at (0x96) USB0ADR ; /* USB0 INDIRECT ADDRESS REGISTER */
43 __sfr __at (0x97) USB0DAT ; /* USB0 DATA REGISTER */
44 __sfr __at (0x98) SCON ; /* UART0 CONTROL */
45 __sfr __at (0x98) SCON0 ; /* UART0 CONTROL */
46 __sfr __at (0x99) SBUF ; /* UART0 BUFFER */
47 __sfr __at (0x99) SBUF0 ; /* UART0 BUFFER */
48 __sfr __at (0x9A) SMOD0 ; /* UART0 MODE */
49 __sfr __at (0xA0) P2 ; /* PORT 2 */
50 __sfr __at (0xA4) P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */
51 __sfr __at (0xA6) P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
52 __sfr __at (0xA7) P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */
53 __sfr __at (0xA8) IE ; /* INTERRUPT ENABLE */
54 __sfr __at (0xA9) CLKSEL ; /* SYSTEM CLOCK SELECT */
55 __sfr __at (0xAA) EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
56 __sfr __at (0xAA) _XPAGE ; /* XDATA/PDATA PAGE */
57 __sfr __at (0xB0) P3 ; /* PORT 3 */
58 __sfr __at (0xB2) OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
59 __sfr __at (0xB3) OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
60 __sfr __at (0xB6) FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
61 __sfr __at (0xB7) FLKEY ; /* FLASH ACESS LIMIT */
62 __sfr __at (0xB8) IP ; /* INTERRUPT PRIORITY */
63 __sfr __at (0xB9) CLKMUL ; /* CLOCK MULTIPLIER CONTROL REGISTER */
64 __sfr __at (0xC9) REG0CN ; /* VOLTAGE REGULATOR CONTROL */
65 __sfr __at (0xD0) PSW ; /* PROGRAM STATUS WORD */
66 __sfr __at (0xD7) USB0XCN ; /* USB0 TRANSCEIVER CONTROL */
67 __sfr __at (0xE0) ACC ; /* ACCUMULATOR */
68 __sfr __at (0xE2) GPIOCN ; /* GLOBAL PORT I/O CONTROL */
69 __sfr __at (0xE3) OSCLCN ; /* LOW-FREQUENCY OSCILLATOR CONTROL */
70 __sfr __at (0xE6) EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
71 __sfr __at (0xE7) EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
72 __sfr __at (0xEF) RSTSRC ; /* RESET SOURCE */
73 __sfr __at (0xF0) B ; /* B REGISTER */
74 __sfr __at (0xF6) EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
75 __sfr __at (0xF7) EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
76 __sfr __at (0xFF) VDM0CN ; /* VDD MONITOR CONTROL */
79 /* WORD/DWORD Registers */
81 __sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */
82 __sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */
83 __sfr16 __at (0x9493) SBRL0 ; /* BAUDRATE GENERATOR 0 RELOAD VALUE WORD */
89 __sbit __at (0x80) P0_0 ;
90 __sbit __at (0x81) P0_1 ;
91 __sbit __at (0x82) P0_2 ;
92 __sbit __at (0x83) P0_3 ;
93 __sbit __at (0x84) P0_4 ;
94 __sbit __at (0x85) P0_5 ;
95 __sbit __at (0x86) P0_6 ;
96 __sbit __at (0x87) P0_7 ;
99 __sbit __at (0x88) IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
100 __sbit __at (0x89) IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
101 __sbit __at (0x8A) IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
102 __sbit __at (0x8B) IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
103 __sbit __at (0x8C) TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
104 __sbit __at (0x8D) TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
105 __sbit __at (0x8E) TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
106 __sbit __at (0x8F) TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
109 __sbit __at (0x98) RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
110 __sbit __at (0x98) RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
111 __sbit __at (0x99) TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
112 __sbit __at (0x99) TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
113 __sbit __at (0x9A) RB8 ; /* SCON.2 - RECEIVE BIT 8 */
114 __sbit __at (0x9A) RBX0 ; /* SCON.2 - EXTRA RECEIVE BIT */
115 __sbit __at (0x9B) TB8 ; /* SCON.3 - TRANSMIT BIT 8 */
116 __sbit __at (0x9B) TBX0 ; /* SCON.3 - EXTRA TRANSMIT BIT */
117 __sbit __at (0x9C) REN ; /* SCON.4 - RECEIVE ENABLE */
118 __sbit __at (0x9C) REN0 ; /* SCON.4 - RECEIVE ENABLE */
119 __sbit __at (0x9E) PERR0 ; /* SCON.6 - PARITY ERROR FLAG */
120 __sbit __at (0x9F) OVR0 ; /* SCON.7 - RECEIVE FIFO OVERRUN FLAG */
123 __sbit __at (0xA0) P2_0 ;
124 __sbit __at (0xA1) P2_1 ;
125 __sbit __at (0xA2) P2_2 ;
126 __sbit __at (0xA3) P2_3 ;
127 __sbit __at (0xA4) P2_4 ;
128 __sbit __at (0xA5) P2_5 ;
131 __sbit __at (0xA8) EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
132 __sbit __at (0xA9) ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
133 __sbit __at (0xAA) EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
134 __sbit __at (0xAB) ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
135 __sbit __at (0xAC) ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
136 __sbit __at (0xAC) ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
137 __sbit __at (0xAF) EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
140 __sbit __at (0xB0) P3_0 ;
143 __sbit __at (0xB8) PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
144 __sbit __at (0xB9) PT0 ; /* IP.1 - TIMER 0 PRIORITY */
145 __sbit __at (0xBA) PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
146 __sbit __at (0xBB) PT1 ; /* IP.3 - TIMER 1 PRIORITY */
147 __sbit __at (0xBC) PS ; /* IP.4 - SERIAL PORT PRIORITY */
148 __sbit __at (0xBC) PS0 ; /* IP.4 - SERIAL PORT PRIORITY */
151 __sbit __at (0xD0) PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
152 __sbit __at (0xD1) F1 ; /* PSW.1 - FLAG 1 */
153 __sbit __at (0xD2) OV ; /* PSW.2 - OVERFLOW FLAG */
154 __sbit __at (0xD3) RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */
155 __sbit __at (0xD4) RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */
156 __sbit __at (0xD5) F0 ; /* PSW.5 - FLAG 0 */
157 __sbit __at (0xD6) AC ; /* PSW.6 - AUXILIARY CARRY FLAG */
158 __sbit __at (0xD7) CY ; /* PSW.7 - CARRY FLAG */
161 /* Predefined SFR Bit Masks */
163 #define PCON_IDLE 0x01 /* PCON */
164 #define PCON_STOP 0x02 /* PCON */
165 #define T0M 0x04 /* CKCON */
166 #define T1M 0x08 /* CKCON */
167 #define PSWE 0x01 /* PSCTL */
168 #define PSEE 0x02 /* PSCTL */
169 #define EUSB0 0x02 /* EIE1 */
170 #define EVBUS 0x01 /* EIE2 */
171 #define PORSF 0x02 /* RSTSRC */
172 #define SWRSF 0x10 /* RSTSRC */