1 /*-------------------------------------------------------------------------
2 Register Declarations for the Cygnal/SiLabs C8051F30x Processor Range
4 Copyright (C) 2004 - Maarten Brock, sourceforge.brock@dse.nl
6 This library is free software; you can redistribute it and/or
7 modify it under the terms of the GNU Lesser General Public
8 License as published by the Free Software Foundation; either
9 version 2.1 of the License, or (at your option) any later version.
11 This library is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 Lesser General Public License for more details.
16 You should have received a copy of the GNU Lesser General Public
17 License along with this library; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------*/
26 sfr at 0x80 P0 ; /* PORT 0 */
27 sfr at 0x81 SP ; /* STACK POINTER */
28 sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */
29 sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */
30 sfr at 0x87 PCON ; /* POWER CONTROL */
31 sfr at 0x88 TCON ; /* TIMER CONTROL */
32 sfr at 0x89 TMOD ; /* TIMER MODE */
33 sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */
34 sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */
35 sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */
36 sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */
37 sfr at 0x8E CKCON ; /* CLOCK CONTROL */
38 sfr at 0x8F PSCTL ; /* PROGRAM STORE R/W CONTROL */
39 sfr at 0x98 SCON ; /* SERIAL PORT CONTROL */
40 sfr at 0x98 SCON0 ; /* SERIAL PORT CONTROL */
41 sfr at 0x99 SBUF ; /* SERIAL PORT BUFFER */
42 sfr at 0x99 SBUF0 ; /* SERIAL PORT BUFFER */
43 sfr at 0x9D CPT0MD ; /* COMPARATOR 0 MODE SELECTION */
44 sfr at 0x9F CPT0MX ; /* COMPARATOR 0 MUX SELECTION */
45 sfr at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */
46 sfr at 0xA8 IE ; /* INTERRUPT ENABLE */
47 sfr at 0xB1 OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
48 sfr at 0xB2 OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
49 sfr at 0xB3 OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
50 sfr at 0xB6 FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
51 sfr at 0xB7 FLKEY ; /* FLASH ACESS LIMIT */
52 sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */
53 sfr at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */
54 sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */
55 sfr at 0xBE ADC0 ; /* ADC 0 DATA */
56 sfr at 0xC0 SMB0CN ; /* SMBUS CONTROL */
57 sfr at 0xC1 SMB0CF ; /* SMBUS CONFIGURATION */
58 sfr at 0xC2 SMB0DAT ; /* SMBUS DATA */
59 sfr at 0xC4 ADC0GT ; /* ADC 0 GREATER-THAN REGISTER */
60 sfr at 0xC6 ADC0LT ; /* ADC 0 LESS-THAN REGISTER */
61 sfr at 0xC8 T2CON ; /* TIMER 2 CONTROL */
62 sfr at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */
63 sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
64 sfr at 0xCA TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
65 sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
66 sfr at 0xCB TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
67 sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */
68 sfr at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */
69 sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */
70 sfr at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */
71 sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */
72 sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
73 sfr at 0xD8 PCA0CN ; /* PCA CONTROL */
74 sfr at 0xD9 PCA0MD ; /* PCA MODE */
75 sfr at 0xDA PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */
76 sfr at 0xDB PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */
77 sfr at 0xDC PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */
78 sfr at 0xE0 ACC ; /* ACCUMULATOR */
79 sfr at 0xE1 PRT0MX ; /* PORT MUX CONFIGURATION REGISTER 0 */
80 sfr at 0xE1 XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */
81 sfr at 0xE2 PRT1MX ; /* PORT MUX CONFIGURATION REGISTER 1 */
82 sfr at 0xE2 XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */
83 sfr at 0xE3 PRT2MX ; /* PORT MUX CONFIGURATION REGISTER 2 */
84 sfr at 0xE3 XBR2 ; /* PORT MUX CONFIGURATION REGISTER 2 */
85 sfr at 0xE4 IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
86 sfr at 0xE4 INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
87 sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
88 sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */
89 sfr at 0xE9 PCA0CPL1 ; /* PCA CAPTURE 1 LOW */
90 sfr at 0xEA PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */
91 sfr at 0xEB PCA0CPL2 ; /* PCA CAPTURE 2 LOW */
92 sfr at 0xEC PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */
93 sfr at 0xEF RSTSRC ; /* RESET SOURCE */
94 sfr at 0xF0 B ; /* B REGISTER */
95 sfr at 0xF1 P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */
96 sfr at 0xF1 P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */
97 sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
98 sfr at 0xF8 CPT0CN ; /* COMPARATOR 0 CONTROL */
99 sfr at 0xF9 PCA0L ; /* PCA COUNTER LOW */
100 sfr at 0xFA PCA0H ; /* PCA COUNTER HIGH */
101 sfr at 0xFB PCA0CPL0 ; /* PCA CAPTURE 0 LOW */
102 sfr at 0xFC PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */
118 sbit at 0x88 IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
119 sbit at 0x89 IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
120 sbit at 0x8A IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
121 sbit at 0x8B IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
122 sbit at 0x8C TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
123 sbit at 0x8D TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
124 sbit at 0x8E TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
125 sbit at 0x8F TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
128 sbit at 0x98 RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
129 sbit at 0x98 RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
130 sbit at 0x99 TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
131 sbit at 0x99 TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
132 sbit at 0x9A RB8 ; /* SCON.2 - RECEIVE BIT 8 */
133 sbit at 0x9A RB80 ; /* SCON.2 - RECEIVE BIT 8 */
134 sbit at 0x9B TB8 ; /* SCON.3 - TRANSMIT BIT 8 */
135 sbit at 0x9B TB80 ; /* SCON.3 - TRANSMIT BIT 8 */
136 sbit at 0x9C REN ; /* SCON.4 - RECEIVE ENABLE */
137 sbit at 0x9C REN0 ; /* SCON.4 - RECEIVE ENABLE */
138 sbit at 0x9D SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
139 sbit at 0x9D MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
140 sbit at 0x9F SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
141 sbit at 0x9F S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
144 sbit at 0xA8 EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
145 sbit at 0xA9 ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
146 sbit at 0xAA EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
147 sbit at 0xAB ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
148 sbit at 0xAC ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
149 sbit at 0xAC ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
150 sbit at 0xAD ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */
151 sbit at 0xAE IEGF0 ; /* IE.6 - GENERAL PURPOSE FLAG 0 */
152 sbit at 0xAF EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
155 sbit at 0xB8 PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
156 sbit at 0xB9 PT0 ; /* IP.1 - TIMER 0 PRIORITY */
157 sbit at 0xBA PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
158 sbit at 0xBB PT1 ; /* IP.3 - TIMER 1 PRIORITY */
159 sbit at 0xBC PS ; /* IP.4 - SERIAL PORT PRIORITY */
160 sbit at 0xBC PS0 ; /* IP.4 - SERIAL PORT PRIORITY */
161 sbit at 0xBD PT2 ; /* IP.5 - TIMER 2 PRIORITY */
164 sbit at 0xC0 SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */
165 sbit at 0xC1 ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */
166 sbit at 0xC2 ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */
167 sbit at 0xC3 ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */
168 sbit at 0xC4 STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */
169 sbit at 0xC5 STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */
170 sbit at 0xC6 TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */
171 sbit at 0xC7 MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */
174 sbit at 0xC8 T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */
175 sbit at 0xCA TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */
176 sbit at 0xCB T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */
177 sbit at 0xCD TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */
178 sbit at 0xCE TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */
179 sbit at 0xCF TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */
180 sbit at 0xCF TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */
183 sbit at 0xD0 PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
184 sbit at 0xD1 F1 ; /* PSW.1 - FLAG 1 */
185 sbit at 0xD2 OV ; /* PSW.2 - OVERFLOW FLAG */
186 sbit at 0xD3 RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */
187 sbit at 0xD4 RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */
188 sbit at 0xD5 F0 ; /* PSW.5 - FLAG 0 */
189 sbit at 0xD6 AC ; /* PSW.6 - AUXILIARY CARRY FLAG */
190 sbit at 0xD7 CY ; /* PSW.7 - CARRY FLAG */
193 sbit at 0xD8 CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */
194 sbit at 0xD9 CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */
195 sbit at 0xDA CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */
196 sbit at 0xDE CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */
197 sbit at 0xDF CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */
200 sbit at 0xE8 AD0CM0 ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */
201 sbit at 0xE9 AD0CM1 ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */
202 sbit at 0xEA AD0CM2 ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */
203 sbit at 0xEB AD0WINT ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */
204 sbit at 0xEC AD0BUSY ; /* ADC0CN.4 - ADC 0 BUSY FLAG */
205 sbit at 0xED AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
206 sbit at 0xEE AD0TM ; /* ADC0CN.6 - ADC 0 TRACK MODE */
207 sbit at 0xEF AD0EN ; /* ADC0CN.7 - ADC 0 ENABLE */
210 sbit at 0xF8 CP0HYN0 ; /* CPT0CN.0 - Comp.0 Neg. Hysteresis Control Bit0*/
211 sbit at 0xF9 CP0HYN1 ; /* CPT0CN.1 - Comp.0 Neg. Hysteresis Control Bit1*/
212 sbit at 0xFA CP0HYP0 ; /* CPT0CN.2 - Comp.0 Pos. Hysteresis Control Bit0*/
213 sbit at 0xFB CP0HYP1 ; /* CPT0CN.3 - Comp.0 Pos. Hysteresis Control Bit1*/
214 sbit at 0xFC CP0FIF ; /* CPT0CN.4 - Comparator0 Falling-Edge Int. Flag */
215 sbit at 0xFD CP0RIF ; /* CPT0CN.5 - Comparator0 Rising-Edge Int. Flag */
216 sbit at 0xFE CP0OUT ; /* CPT0CN.6 - Comparator0 Output State Flag */
217 sbit at 0xFF CP0EN ; /* CPT0CN.7 - Comparator0 Enable Bit */
220 /* Predefined SFR Bit Masks */
222 #define IDLE 0x01 /* PCON */
223 #define STOP 0x02 /* PCON */
224 #define T1M 0x10 /* CKCON */
225 #define PSWE 0x01 /* PSCTL */
226 #define PSEE 0x02 /* PSCTL */
227 #define ECP0F 0x10 /* EIE1 */
228 #define ECP0R 0x20 /* EIE1 */
229 #define PORSF 0x02 /* RSTSRC */
230 #define SWRSF 0x10 /* RSTSRC */
231 #define ECCF 0x01 /* PCA0CPMn */
232 #define PWM 0x02 /* PCA0CPMn */
233 #define TOG 0x04 /* PCA0CPMn */
234 #define MAT 0x08 /* PCA0CPMn */
235 #define CAPN 0x10 /* PCA0CPMn */
236 #define CAPP 0x20 /* PCA0CPMn */
237 #define ECOM 0x40 /* PCA0CPMn */
238 #define PWM16 0x80 /* PCA0CPMn */
239 #define CP0E 0x10 /* XBR1 */
240 #define CP0OEN 0x10 /* XBR1 */
241 #define CP0AE 0x20 /* XBR1 */
242 #define CP0AOEN 0x20 /* XBR1 */
projects / fw / sdcc / blob