1 /*---------------------------------------------------------------------------
2 Register Declarations for the Cygnal/SiLabs C8051F2xx Processor Range
4 Copyright (C) 2006 - Maarten Brock, sourceforge.brock@dse.nl
6 This library is free software; you can redistribute it and/or
7 modify it under the terms of the GNU Lesser General Public
8 License as published by the Free Software Foundation; either
9 version 2.1 of the License, or (at your option) any later version.
11 This library is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 Lesser General Public License for more details.
16 You should have received a copy of the GNU Lesser General Public
17 License along with this library; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 ---------------------------------------------------------------------------*/
26 __sfr __at (0x80) P0 ; /* PORT 0 */
27 __sfr __at (0x81) SP ; /* STACK POINTER */
28 __sfr __at (0x82) DPL ; /* DATA POINTER - LOW BYTE */
29 __sfr __at (0x83) DPH ; /* DATA POINTER - HIGH BYTE */
30 __sfr __at (0x87) PCON ; /* POWER Control */
31 __sfr __at (0x88) TCON ; /* TIMER Control */
32 __sfr __at (0x89) TMOD ; /* TIMER MODE */
33 __sfr __at (0x8A) TL0 ; /* TIMER 0 - LOW BYTE */
34 __sfr __at (0x8B) TL1 ; /* TIMER 1 - LOW BYTE */
35 __sfr __at (0x8C) TH0 ; /* TIMER 0 - HIGH BYTE */
36 __sfr __at (0x8D) TH1 ; /* TIMER 1 - HIGH BYTE */
37 __sfr __at (0x8E) CKCON ; /* CLOCK Control */
38 __sfr __at (0x8F) PSCTL ; /* PROGRAM STORE R/W Control */
39 __sfr __at (0x90) P1 ; /* PORT 1 */
40 __sfr __at (0x98) SCON ; /* SERIAL PORT Control */
41 __sfr __at (0x99) SBUF ; /* SERIAL PORT BUFFER */
42 __sfr __at (0x9A) SPI0CFG ; /* SERIAL PERIPHERAL INTERFACE 0 Configuration */
43 __sfr __at (0x9B) SPI0DAT ; /* SERIAL PERIPHERAL INTERFACE 0 DATA */
44 __sfr __at (0x9D) SPI0CKR ; /* SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE Control */
45 __sfr __at (0x9E) CPT0CN ; /* COMPARATOR 0 Control */
46 __sfr __at (0x9F) CPT1CN ; /* COMPARATOR 1 Control */
47 __sfr __at (0xA0) P2 ; /* PORT 2 */
48 __sfr __at (0xA4) PRT0CF ; /* PORT 0 OUTPUT MODE Configuration */
49 __sfr __at (0xA5) PRT1CF ; /* PORT 1 OUTPUT MODE Configuration */
50 __sfr __at (0xA6) PRT2CF ; /* PORT 2 OUTPUT MODE Configuration */
51 __sfr __at (0xA7) PRT3CF ; /* PORT 3 OUTPUT MODE Configuration */
52 __sfr __at (0xA8) IE ; /* Interrupt Enable */
53 __sfr __at (0xAD) SWCINT ; /* SOFTWARE-Controlled Interrupt FLAGS */
54 __sfr __at (0xAD) PRT1IF ; /* SOFTWARE-Controlled Interrupt FLAGS (LEGACY NAME) */
55 __sfr __at (0xAF) EMI0CN ; /* EXTERNAL MEMORY INTERFACE Control (F206/F226/F236)*/
56 __sfr __at (0xB0) P3 ; /* PORT 3 */
57 __sfr __at (0xB1) OSCXCN ; /* EXTERNAL OSCILLATOR Control */
58 __sfr __at (0xB2) OSCICN ; /* INTERNAL OSCILLATOR Control */
59 __sfr __at (0xB6) FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
60 __sfr __at (0xB7) FLACL ; /* FLASH ACESS LIMIT */
61 __sfr __at (0xB8) IP ; /* Interrupt Priority */
62 __sfr __at (0xBB) AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION (Not on F230/1/6) */
63 __sfr __at (0xBC) ADC0CF ; /* ADC 0 Configuration (Not on F230/1/6) */
64 __sfr __at (0xBE) ADC0L ; /* ADC 0 Data LOW ( F206 only ) */
65 __sfr __at (0xBF) ADC0H ; /* ADC 0 Data High */
66 __sfr __at (0xC4) ADC0GTL ; /* ADC 0 GREATER-THAN Register LOW( F206 only ) */ ( F206 only ) */
67 __sfr __at (0xC5) ADC0GTH ; /* ADC 0 GREATER-THAN Register (Not on F230/1/6) */
68 __sfr __at (0xC6) ADC0LTL ; /* ADC 0 LESS-THAN Register LOW ( F206 only ) */
69 __sfr __at (0xC7) ADC0LTH ; /* ADC 0 LESS-THAN Register (Not on F230/1/6) */
70 __sfr __at (0xC8) T2CON ; /* TIMER 2 Control */
71 __sfr __at (0xCA) RCAP2L ; /* TIMER 2 CAPTURE Register - LOW BYTE */
72 __sfr __at (0xCB) RCAP2H ; /* TIMER 2 CAPTURE Register - HIGH BYTE */
73 __sfr __at (0xCC) TL2 ; /* TIMER 2 - LOW BYTE */
74 __sfr __at (0xCD) TH2 ; /* TIMER 2 - HIGH BYTE */
75 __sfr __at (0xD0) PSW ; /* PROGRAM STATUS WORD */
76 __sfr __at (0xD1) REF0CN ; /* VOLTAGE REFERENCE 0 Control */
77 __sfr __at (0xE0) ACC ; /* ACCUMULATOR */
78 __sfr __at (0xE1) PRT0MX ; /* PORT MUX Configuration Register 0 */
79 __sfr __at (0xE2) PRT1MX ; /* PORT MUX Configuration Register 1 */
80 __sfr __at (0xE3) PRT2MX ; /* PORT MUX Configuration Register 2 */
81 __sfr __at (0xE6) EIE1 ; /* EXTERNAL Interrupt Enable 1 */
82 __sfr __at (0xE7) EIE2 ; /* EXTERNAL Interrupt Enable 2 */
83 __sfr __at (0xE8) ADC0CN ; /* ADC 0 Control (Not on F230/1/6) */
84 __sfr __at (0xEF) RSTSRC ; /* RESET SOURCE */
85 __sfr __at (0xF0) B ; /* B Register */
86 __sfr __at (0xF1) P0MODE ; /* PORT 0 INPUT MODE Configuration */
87 __sfr __at (0xF2) P1MODE ; /* PORT 1 INPUT MODE Configuration */
88 __sfr __at (0xF3) P2MODE ; /* PORT 2 INPUT MODE Configuration */
89 __sfr __at (0xF4) P3MODE ; /* PORT 3 INPUT MODE Configuration (Not on F221/F231)*/
90 __sfr __at (0xF6) EIP1 ; /* EXTERNAL Interrupt Priority Register 1 */
91 __sfr __at (0xF7) EIP2 ; /* EXTERNAL Interrupt Priority Register 2 */
92 __sfr __at (0xF8) SPI0CN ; /* SERIAL PERIPHERAL INTERFACE 0 Control */
93 __sfr __at (0xFF) WDTCN ; /* WATCHDOG TIMER Control */
96 /* WORD/DWORD Registers */
98 __sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */
99 __sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */
100 __sfr16 __at (0xCDCC) TMR2 ; /* TIMER 2 COUNTER */
101 __sfr16 __at (0xCBCA) RCAP2 ; /* TIMER 2 CAPTURE REGISTER WORD */
102 __sfr16 __at (0xBFBE) ADC0 ; /* ADC 0 DATA WORD */
103 __sfr16 __at (0xC5C4) ADC0GT ; /* ADC 0 GREATER-THAN REGISTER WORD */
104 __sfr16 __at (0xC7C6) ADC0LT ; /* ADC 0 LESS-THAN REGISTER WORD */
110 __sbit __at (0x80) P0_0 ;
111 __sbit __at (0x81) P0_1 ;
112 __sbit __at (0x82) P0_2 ;
113 __sbit __at (0x83) P0_3 ;
114 __sbit __at (0x84) P0_4 ; /* Port0 I/O Bits */
115 __sbit __at (0x85) P0_5 ;
116 __sbit __at (0x86) P0_6 ;
117 __sbit __at (0x87) P0_7 ;
120 __sbit __at (0x88) IT0 ; /* EXT. Interrupt 0 TYPE */
121 __sbit __at (0x89) IE0 ; /* EXT. Interrupt 0 EDGE FLAG */
122 __sbit __at (0x8A) IT1 ; /* EXT. Interrupt 1 TYPE */
123 __sbit __at (0x8B) IE1 ; /* EXT. Interrupt 1 EDGE FLAG */
124 __sbit __at (0x8C) TR0 ; /* TIMER 0 ON/OFF Control */
125 __sbit __at (0x8D) TF0 ; /* TIMER 0 Overflow FLAG */
126 __sbit __at (0x8E) TR1 ; /* TIMER 1 ON/OFF Control */
127 __sbit __at (0x8F) TF1 ; /* TIMER 1 Overflow FLAG */
130 __sbit __at (0x90) P1_0 ;
131 __sbit __at (0x91) P1_1 ;
132 __sbit __at (0x92) P1_2 ;
133 __sbit __at (0x93) P1_3 ;
134 __sbit __at (0x94) P1_4 ; /* Port1 I/O Bits */
135 __sbit __at (0x95) P1_5 ;
136 __sbit __at (0x96) P1_6 ;
137 __sbit __at (0x97) P1_7 ;
140 __sbit __at (0x98) RI ; /* RECEIVE Interrupt FLAG */
141 __sbit __at (0x99) TI ; /* TRANSMIT Interrupt FLAG */
142 __sbit __at (0x9A) RB8 ; /* RECEIVE BIT 8 */
143 __sbit __at (0x9B) TB8 ; /* TRANSMIT BIT 8 */
144 __sbit __at (0x9C) REN ; /* RECEIVE Enable */
145 __sbit __at (0x9D) SM2 ; /* MULTIPROCESSOR COMMUNICATION Enable */
146 __sbit __at (0x9E) SM1 ; /* SERIAL MODE Control BIT 1 */
147 __sbit __at (0x9F) SM0 ; /* SERIAL MODE Control BIT 0 */
150 __sbit __at (0xA0) P2_0 ;
151 __sbit __at (0xA1) P2_1 ;
152 __sbit __at (0xA2) P2_2 ;
153 __sbit __at (0xA3) P2_3 ;
154 __sbit __at (0xA4) P2_4 ; /* Port2 I/O Bits */
155 __sbit __at (0xA5) P2_5 ;
156 __sbit __at (0xA6) P2_6 ;
157 __sbit __at (0xA7) P2_7 ;
160 __sbit __at (0xA8) EX0 ; /* EXTERNAL Interrupt 0 Enable */
161 __sbit __at (0xA9) ET0 ; /* TIMER 0 Interrupt Enable */
162 __sbit __at (0xAA) EX1 ; /* EXTERNAL Interrupt 1 Enable */
163 __sbit __at (0xAB) ET1 ; /* TIMER 1 Interrupt Enable */
164 __sbit __at (0xAC) ES ; /* SERIAL PORT Interrupt Enable */
165 __sbit __at (0xAD) ET2 ; /* TIMER 2 Interrupt Enable */
166 //------------- /* Bit 6 not used */
167 __sbit __at (0xAF) EA ; /* GLOBAL Interrupt Enable */
170 __sbit __at (0xB0) P3_0 ;
171 __sbit __at (0xB1) P3_1 ;
172 __sbit __at (0xB2) P3_2 ;
173 __sbit __at (0xB3) P3_3 ;
174 __sbit __at (0xB4) P3_4 ; /* Port3 I/O Bits */
175 __sbit __at (0xB5) P3_5 ;
176 __sbit __at (0xB6) P3_6 ;
177 __sbit __at (0xB7) P3_7 ;
180 __sbit __at (0xB8) PX0 ; /* EXTERNAL Interrupt 0 Priority */
181 __sbit __at (0xB9) PT0 ; /* TIMER 0 Priority */
182 __sbit __at (0xBA) PX1 ; /* EXTERNAL Interrupt 1 Priority */
183 __sbit __at (0xBB) PT1 ; /* TIMER 1 Priority */
184 __sbit __at (0xBC) PS ; /* SERIAL PORT Priority */
185 __sbit __at (0xBD) PT2 ; /* TIMER 2 Priority */
186 //------------- /* Bit 6 not used */
187 //------------- /* Bit 7 not used */
190 __sbit __at (0xC8) CPRL2 ; /* CAPTURE OR RELOAD SELECT */
191 __sbit __at (0xC9) CT2 ; /* TIMER OR COUNTER SELECT */
192 __sbit __at (0xCA) TR2 ; /* TIMER 2 ON/OFF Control */
193 __sbit __at (0xCB) EXEN2 ; /* TIMER 2 EXTERNAL Enable FLAG */
194 __sbit __at (0xCC) TCLK ; /* TRANSMIT CLOCK FLAG */
195 __sbit __at (0xCD) RCLK ; /* RECEIVE CLOCK FLAG */
196 __sbit __at (0xCE) EXF2 ; /* EXTERNAL FLAG */
197 __sbit __at (0xCF) TF2 ; /* TIMER 2 Overflow FLAG */
200 __sbit __at (0xD0) P ; /* ACCUMULATOR PARITY FLAG */
201 __sbit __at (0xD1) F1 ; /* USER FLAG 1 */
202 __sbit __at (0xD2) OV ; /* Overflow FLAG */
203 __sbit __at (0xD3) RS0 ; /* Register BANK SELECT 0 */
204 __sbit __at (0xD4) RS1 ; /* Register BANK SELECT 1 */
205 __sbit __at (0xD5) F0 ; /* USER FLAG 0 */
206 __sbit __at (0xD6) AC ; /* AUXILIARY CARRY FLAG */
207 __sbit __at (0xD7) CY ; /* CARRY FLAG */
210 __sbit __at (0xE8) ADLJST ; /* Left Justify Data (F206 only) */
211 __sbit __at (0xE9) ADWINT ; /* WINDOW COMPARE Interrupt FLAG */
212 __sbit __at (0xEA) ADSTM0 ; /* START OF CONVERSION MODE BIT 0 */
213 __sbit __at (0xEB) ADSTM1 ; /* START OF CONVERSION MODE BIT 1 */
214 __sbit __at (0xEC) ADBUSY ; /* BUSY FLAG */
215 __sbit __at (0xED) ADCINT ; /* CONVERISION COMPLETE Interrupt FLAG */
216 __sbit __at (0xEE) ADCTM ; /* TRACK MODE */
217 __sbit __at (0xEF) ADCEN ; /* Enable */
220 __sbit __at (0xF8) SPIEN ; /* SPI Enable */
221 __sbit __at (0xF9) MSTEN ; /* MASTER Enable */
222 __sbit __at (0xFA) SLVSEL ; /* SLAVE SELECT */
223 __sbit __at (0xFB) TXBSY ; /* TX BUSY FLAG */
224 __sbit __at (0xFC) RXOVRN ; /* RX OVERRUN FLAG */
225 __sbit __at (0xFD) MODF ; /* MODE FAULT FLAG */
226 __sbit __at (0xFE) WCOL ; /* WRITE COLLISION FLAG */
227 __sbit __at (0xFF) SPIF ; /* Interrupt FLAG */
projects / fw / sdcc / blob