1 /*---------------------------------------------------------------------------
2 Register Declarations for the Cygnal/SiLabs C8051F12x-F13x Processor Range
4 Copyright (C) 2003 - Maarten Brock, sourceforge.brock@dse.nl
6 This library is free software; you can redistribute it and/or
7 modify it under the terms of the GNU Lesser General Public
8 License as published by the Free Software Foundation; either
9 version 2.1 of the License, or (at your option) any later version.
11 This library is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 Lesser General Public License for more details.
16 You should have received a copy of the GNU Lesser General Public
17 License along with this library; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 ---------------------------------------------------------------------------*/
28 sfr at 0x80 P0 ; /* PORT 0 */
29 sfr at 0x81 SP ; /* STACK POINTER */
30 sfr at 0x82 DPL ; /* DATA POINTER - LOW BYTE */
31 sfr at 0x83 DPH ; /* DATA POINTER - HIGH BYTE */
32 sfr at 0x84 SFRPAGE ; /* SFR PAGE SELECT */
33 sfr at 0x85 SFRNEXT ; /* SFR STACK NEXT PAGE */
34 sfr at 0x86 SFRLAST ; /* SFR STACK LAST PAGE */
35 sfr at 0x87 PCON ; /* POWER CONTROL */
36 sfr at 0x90 P1 ; /* PORT 1 */
37 sfr at 0xA0 P2 ; /* PORT 2 */
38 sfr at 0xA8 IE ; /* INTERRUPT ENABLE */
39 sfr at 0xB0 P3 ; /* PORT 3 */
40 sfr at 0xB1 PSBANK ; /* FLASH BANK SELECT */
41 sfr at 0xB8 IP ; /* INTERRUPT PRIORITY */
42 sfr at 0xD0 PSW ; /* PROGRAM STATUS WORD */
43 sfr at 0xE0 ACC ; /* ACCUMULATOR */
44 sfr at 0xE6 EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
45 sfr at 0xE7 EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
46 sfr at 0xF0 B ; /* B REGISTER */
47 sfr at 0xF6 EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
48 sfr at 0xF7 EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
49 sfr at 0xFF WDTCN ; /* WATCHDOG TIMER CONTROL */
52 sfr at 0x88 TCON ; /* TIMER CONTROL */
53 sfr at 0x89 TMOD ; /* TIMER MODE */
54 sfr at 0x8A TL0 ; /* TIMER 0 - LOW BYTE */
55 sfr at 0x8B TL1 ; /* TIMER 1 - LOW BYTE */
56 sfr at 0x8C TH0 ; /* TIMER 0 - HIGH BYTE */
57 sfr at 0x8D TH1 ; /* TIMER 1 - HIGH BYTE */
58 sfr at 0x8E CKCON ; /* TIMER 0/1 CLOCK CONTROL */
59 sfr at 0x8F PSCTL ; /* FLASH WRITE/ERASE CONTROL */
60 sfr at 0x91 SSTA0 ; /* UART 0 STATUS */
61 sfr at 0x98 SCON0 ; /* UART 0 CONTROL */
62 sfr at 0x98 SCON ; /* UART 0 CONTROL */
63 sfr at 0x99 SBUF0 ; /* UART 0 BUFFER */
64 sfr at 0x99 SBUF ; /* UART 0 BUFFER */
65 sfr at 0x9A SPI0CFG ; /* SPI 0 CONFIGURATION */
66 sfr at 0x9B SPI0DAT ; /* SPI 0 DATA */
67 sfr at 0x9D SPI0CKR ; /* SPI 0 CLOCK RATE CONTROL */
68 sfr at 0xA1 EMI0TC ; /* EMIF TIMING CONTROL */
69 sfr at 0xA2 EMI0CN ; /* EMIF CONTROL */
70 sfr at 0xA2 _XPAGE ; /* XDATA/PDATA PAGE */
71 sfr at 0xA3 EMI0CF ; /* EMIF CONFIGURATION */
72 sfr at 0xA9 SADDR0 ; /* UART 0 SLAVE ADDRESS */
73 sfr at 0xB7 FLSCL ; /* FLASH SCALE */
74 sfr at 0xB9 SADEN0 ; /* UART 0 SLAVE ADDRESS MASK */
75 sfr at 0xBA AMX0CF ; /* ADC 0 MUX CONFIGURATION */
76 sfr at 0xBB AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */
77 sfr at 0xBC ADC0CF ; /* ADC 0 CONFIGURATION */
78 sfr at 0xBE ADC0L ; /* ADC 0 DATA - LOW BYTE */
79 sfr at 0xBF ADC0H ; /* ADC 0 DATA - HIGH BYTE */
80 sfr at 0xC0 SMB0CN ; /* SMBUS 0 CONTROL */
81 sfr at 0xC1 SMB0STA ; /* SMBUS 0 STATUS */
82 sfr at 0xC2 SMB0DAT ; /* SMBUS 0 DATA */
83 sfr at 0xC3 SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */
84 sfr at 0xC4 ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
85 sfr at 0xC5 ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
86 sfr at 0xC6 ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
87 sfr at 0xC7 ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
88 sfr at 0xC8 TMR2CN ; /* TIMER 2 CONTROL */
89 sfr at 0xC9 TMR2CF ; /* TIMER 2 CONFIGURATION */
90 sfr at 0xCA RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
91 sfr at 0xCB RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
92 sfr at 0xCC TMR2L ; /* TIMER 2 - LOW BYTE */
93 sfr at 0xCC TL2 ; /* TIMER 2 - LOW BYTE */
94 sfr at 0xCD TMR2H ; /* TIMER 2 - HIGH BYTE */
95 sfr at 0xCD TH2 ; /* TIMER 2 - HIGH BYTE */
96 sfr at 0xCF SMB0CR ; /* SMBUS 0 CLOCK RATE */
97 sfr at 0xD1 REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
98 sfr at 0xD2 DAC0L ; /* DAC 0 REGISTER - LOW BYTE */
99 sfr at 0xD3 DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */
100 sfr at 0xD4 DAC0CN ; /* DAC 0 CONTROL */
101 sfr at 0xD8 PCA0CN ; /* PCA 0 COUNTER CONTROL */
102 sfr at 0xD9 PCA0MD ; /* PCA 0 COUNTER MODE */
103 sfr at 0xDA PCA0CPM0 ; /* PCA 0 MODULE 0 CONTROL */
104 sfr at 0xDB PCA0CPM1 ; /* PCA 0 MODULE 1 CONTROL */
105 sfr at 0xDC PCA0CPM2 ; /* PCA 0 MODULE 2 CONTROL */
106 sfr at 0xDD PCA0CPM3 ; /* PCA 0 MODULE 3 CONTROL */
107 sfr at 0xDE PCA0CPM4 ; /* PCA 0 MODULE 4 CONTROL */
108 sfr at 0xDF PCA0CPM5 ; /* PCA 0 MODULE 5 CONTROL */
109 sfr at 0xE1 PCA0CPL5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - LOW BYTE */
110 sfr at 0xE2 PCA0CPH5 ; /* PCA 0 MODULE 5 CAPTURE/COMPARE - HIGH BYTE */
111 sfr at 0xE8 ADC0CN ; /* ADC 0 CONTROL */
112 sfr at 0xE9 PCA0CPL2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - LOW BYTE */
113 sfr at 0xEA PCA0CPH2 ; /* PCA 0 MODULE 2 CAPTURE/COMPARE - HIGH BYTE */
114 sfr at 0xEB PCA0CPL3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - LOW BYTE */
115 sfr at 0xEC PCA0CPH3 ; /* PCA 0 MODULE 3 CAPTURE/COMPARE - HIGH BYTE */
116 sfr at 0xED PCA0CPL4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - LOW BYTE */
117 sfr at 0xEE PCA0CPH4 ; /* PCA 0 MODULE 4 CAPTURE/COMPARE - HIGH BYTE */
118 sfr at 0xEF RSTSRC ; /* RESET SOURCE */
119 sfr at 0xF8 SPI0CN ; /* SPI 0 CONTROL */
120 sfr at 0xF9 PCA0L ; /* PCA 0 TIMER - LOW BYTE */
121 sfr at 0xFA PCA0H ; /* PCA 0 TIMER - HIGH BYTE */
122 sfr at 0xFB PCA0CPL0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - LOW BYTE */
123 sfr at 0xFC PCA0CPH0 ; /* PCA 0 MODULE 0 CAPTURE/COMPARE - HIGH BYTE */
124 sfr at 0xFD PCA0CPL1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - LOW BYTE */
125 sfr at 0xFE PCA0CPH1 ; /* PCA 0 MODULE 1 CAPTURE/COMPARE - HIGH BYTE */
128 sfr at 0x88 CPT0CN ; /* COMPARATOR 0 CONTROL */
129 sfr at 0x89 CPT0MD ; /* COMPARATOR 0 CONFIGURATION */
130 sfr at 0x98 SCON1 ; /* UART 1 CONTROL */
131 sfr at 0x99 SBUF1 ; /* UART 1 BUFFER */
132 sfr at 0xC8 TMR3CN ; /* TIMER 3 CONTROL */
133 sfr at 0xC9 TMR3CF ; /* TIMER 3 CONFIGURATION */
134 sfr at 0xCA RCAP3L ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
135 sfr at 0xCB RCAP3H ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
136 sfr at 0xCC TMR3L ; /* TIMER 3 - LOW BYTE */
137 sfr at 0xCD TMR3H ; /* TIMER 3 - HIGH BYTE */
138 sfr at 0xD2 DAC1L ; /* DAC 1 REGISTER - LOW BYTE */
139 sfr at 0xD3 DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */
140 sfr at 0xD4 DAC1CN ; /* DAC 1 CONTROL */
143 sfr at 0x88 CPT1CN ; /* COMPARATOR 1 CONTROL */
144 sfr at 0x89 CPT1MD ; /* COMPARATOR 1 CONFIGURATION */
145 sfr at 0xBA AMX2CF ; /* ADC 2 MUX CONFIGURATION */
146 sfr at 0xBB AMX2SL ; /* ADC 2 MUX CHANNEL SELECTION */
147 sfr at 0xBC ADC2CF ; /* ADC 2 CONFIGURATION */
148 sfr at 0xBE ADC2 ; /* ADC 2 DATA */
149 sfr at 0xC4 ADC2GT ; /* ADC 2 GREATER-THAN REGISTER */
150 sfr at 0xC6 ADC2LT ; /* ADC 2 LESS-THAN REGISTER */
151 sfr at 0xC8 TMR4CN ; /* TIMER 4 CONTROL */
152 sfr at 0xC9 TMR4CF ; /* TIMER 4 CONFIGURATION */
153 sfr at 0xCA RCAP4L ; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */
154 sfr at 0xCB RCAP4H ; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */
155 sfr at 0xCC TMR4L ; /* TIMER 4 - LOW BYTE */
156 sfr at 0xCD TMR4H ; /* TIMER 4 - HIGH BYTE */
157 sfr at 0xE8 ADC2CN ; /* ADC 2 CONTROL */
160 sfr at 0x91 MAC0BL ; /* MAC0 B Register Low Byte */
161 sfr at 0x92 MAC0BH ; /* MAC0 B Register High Byte */
162 sfr at 0x93 MAC0ACC0 ; /* MAC0 Accumulator Byte 0 (LSB) */
163 sfr at 0x94 MAC0ACC1 ; /* MAC0 Accumulator Byte 1 */
164 sfr at 0x95 MAC0ACC2 ; /* MAC0 Accumulator Byte 2 */
165 sfr at 0x96 MAC0ACC3 ; /* MAC0 Accumulator Byte 3 (MSB) */
166 sfr at 0x97 MAC0OVR ; /* MAC0 Accumulator Overflow */
167 sfr at 0xC0 MAC0STA ; /* MAC0 Status Register */
168 sfr at 0xC1 MAC0AL ; /* MAC0 A Register Low Byte */
169 sfr at 0xC2 MAC0AH ; /* MAC0 A Register High Byte */
170 sfr at 0xC3 MAC0CF ; /* MAC0 Configuration */
171 sfr at 0xCE MAC0RNDL ; /* MAC0 Rounding Register Low Byte */
172 sfr at 0xCF MAC0RNDH ; /* MAC0 Rounding Register High Byte */
175 sfr at 0x88 FLSTAT ; /* FLASH STATUS */
176 sfr at 0x89 PLL0CN ; /* PLL 0 CONTROL */
177 sfr at 0x8A OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
178 sfr at 0x8B OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
179 sfr at 0x8C OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
180 sfr at 0x8D PLL0DIV ; /* PLL 0 DIVIDER */
181 sfr at 0x8E PLL0MUL ; /* PLL 0 MULTIPLIER */
182 sfr at 0x8F PLL0FLT ; /* PLL 0 FILTER */
183 sfr at 0x96 SFRPGCN ; /* SFR PAGE CONTROL */
184 sfr at 0x97 CLKSEL ; /* SYSTEM CLOCK SELECT */
185 sfr at 0x9A CCH0MA ; /* CACHE MISS ACCUMULATOR */
186 sfr at 0x9C P4MDOUT ; /* PORT 4 OUTPUT MODE */
187 sfr at 0x9D P5MDOUT ; /* PORT 5 OUTPUT MODE */
188 sfr at 0x9E P6MDOUT ; /* PORT 6 OUTPUT MODE */
189 sfr at 0x9F P7MDOUT ; /* PORT 7 OUTPUT MODE */
190 sfr at 0xA1 CCH0CN ; /* CACHE CONTROL */
191 sfr at 0xA2 CCH0TN ; /* CACHE TUNING REGISTER */
192 sfr at 0xA3 CCH0LC ; /* CACHE LOCK */
193 sfr at 0xA4 P0MDOUT ; /* PORT 0 OUTPUT MODE */
194 sfr at 0xA5 P1MDOUT ; /* PORT 1 OUTPUT MODE */
195 sfr at 0xA6 P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
196 sfr at 0xA7 P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */
197 sfr at 0xAD P1MDIN ; /* PORT 1 INPUT MODE */
198 sfr at 0xB7 FLACL ; /* FLASH ACCESS LIMIT */
199 sfr at 0xC8 P4 ; /* PORT 4 */
200 sfr at 0xD8 P5 ; /* PORT 5 */
201 sfr at 0xE1 XBR0 ; /* CROSSBAR CONFIGURATION REGISTER 0 */
202 sfr at 0xE2 XBR1 ; /* CROSSBAR CONFIGURATION REGISTER 1 */
203 sfr at 0xE3 XBR2 ; /* CROSSBAR CONFIGURATION REGISTER 2 */
204 sfr at 0xE8 P6 ; /* PORT 6 */
205 sfr at 0xF8 P7 ; /* PORT 7 */
221 sbit at 0x88 IT0 ; /* EXT. INTERRUPT 0 TYPE */
222 sbit at 0x89 IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */
223 sbit at 0x8A IT1 ; /* EXT. INTERRUPT 1 TYPE */
224 sbit at 0x8B IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */
225 sbit at 0x8C TR0 ; /* TIMER 0 ON/OFF CONTROL */
226 sbit at 0x8D TF0 ; /* TIMER 0 OVERFLOW FLAG */
227 sbit at 0x8E TR1 ; /* TIMER 1 ON/OFF CONTROL */
228 sbit at 0x8F TF1 ; /* TIMER 1 OVERFLOW FLAG */
231 sbit at 0x88 CP0HYN0 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 0 */
232 sbit at 0x89 CP0HYN1 ; /* COMPARATOR 0 NEGATIVE HYSTERESIS 1 */
233 sbit at 0x8A CP0HYP0 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 0 */
234 sbit at 0x8B CP0HYP1 ; /* COMPARATOR 0 POSITIVE HYSTERESIS 1 */
235 sbit at 0x8C CP0FIF ; /* COMPARATOR 0 FALLING EDGE INTERRUPT */
236 sbit at 0x8D CP0RIF ; /* COMPARATOR 0 RISING EDGE INTERRUPT */
237 sbit at 0x8E CP0OUT ; /* COMPARATOR 0 OUTPUT */
238 sbit at 0x8F CP0EN ; /* COMPARATOR 0 ENABLE */
241 sbit at 0x88 CP1HYN0 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 0 */
242 sbit at 0x89 CP1HYN1 ; /* COMPARATOR 1 NEGATIVE HYSTERESIS 1 */
243 sbit at 0x8A CP1HYP0 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 0 */
244 sbit at 0x8B CP1HYP1 ; /* COMPARATOR 1 POSITIVE HYSTERESIS 1 */
245 sbit at 0x8C CP1FIF ; /* COMPARATOR 1 FALLING EDGE INTERRUPT */
246 sbit at 0x8D CP1RIF ; /* COMPARATOR 1 RISING EDGE INTERRUPT */
247 sbit at 0x8E CP1OUT ; /* COMPARATOR 1 OUTPUT */
248 sbit at 0x8F CP1EN ; /* COMPARATOR 1 ENABLE */
251 sbit at 0x88 FLHBUSY ; /* FLASH BUSY */
254 sbit at 0x98 RI0 ; /* UART 0 RX INTERRUPT FLAG */
255 sbit at 0x98 RI ; /* UART 0 RX INTERRUPT FLAG */
256 sbit at 0x99 TI0 ; /* UART 0 TX INTERRUPT FLAG */
257 sbit at 0x99 TI ; /* UART 0 TX INTERRUPT FLAG */
258 sbit at 0x9A RB80 ; /* UART 0 RX BIT 8 */
259 sbit at 0x9B TB80 ; /* UART 0 TX BIT 8 */
260 sbit at 0x9C REN0 ; /* UART 0 RX ENABLE */
261 sbit at 0x9C REN ; /* UART 0 RX ENABLE */
262 sbit at 0x9D SM20 ; /* UART 0 MULTIPROCESSOR EN */
263 sbit at 0x9E SM10 ; /* UART 0 MODE 1 */
264 sbit at 0x9F SM00 ; /* UART 0 MODE 0 */
267 sbit at 0x98 RI1 ; /* UART 1 RX INTERRUPT FLAG */
268 sbit at 0x99 TI1 ; /* UART 1 TX INTERRUPT FLAG */
269 sbit at 0x9A RB81 ; /* UART 1 RX BIT 8 */
270 sbit at 0x9B TB81 ; /* UART 1 TX BIT 8 */
271 sbit at 0x9C REN1 ; /* UART 1 RX ENABLE */
272 sbit at 0x9D MCE1 ; /* UART 1 MCE */
273 sbit at 0x9F S1MODE ; /* UART 1 MODE */
276 sbit at 0xA8 EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */
277 sbit at 0xA9 ET0 ; /* TIMER 0 INTERRUPT ENABLE */
278 sbit at 0xAA EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */
279 sbit at 0xAB ET1 ; /* TIMER 1 INTERRUPT ENABLE */
280 sbit at 0xAC ES0 ; /* UART0 INTERRUPT ENABLE */
281 sbit at 0xAC ES ; /* UART0 INTERRUPT ENABLE */
282 sbit at 0xAD ET2 ; /* TIMER 2 INTERRUPT ENABLE */
283 sbit at 0xAF EA ; /* GLOBAL INTERRUPT ENABLE */
286 sbit at 0xB8 PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */
287 sbit at 0xB9 PT0 ; /* TIMER 0 PRIORITY */
288 sbit at 0xBA PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */
289 sbit at 0xBB PT1 ; /* TIMER 1 PRIORITY */
290 sbit at 0xBC PS ; /* SERIAL PORT PRIORITY */
291 sbit at 0xBD PT2 ; /* TIMER 2 PRIORITY */
294 sbit at 0xC0 SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */
295 sbit at 0xC1 SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */
296 sbit at 0xC2 AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
297 sbit at 0xC3 SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */
298 sbit at 0xC4 STO ; /* SMBUS 0 STOP FLAG */
299 sbit at 0xC5 STA ; /* SMBUS 0 START FLAG */
300 sbit at 0xC6 ENSMB ; /* SMBUS 0 ENABLE */
301 sbit at 0xC7 BUSY ; /* SMBUS 0 BUSY */
304 sbit at 0xC8 CPRL2 ; /* TIMER 2 CAPTURE SELECT */
305 sbit at 0xC9 CT2 ; /* TIMER 2 COUNTER SELECT */
306 sbit at 0xCA TR2 ; /* TIMER 2 ON/OFF CONTROL */
307 sbit at 0xCB EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */
308 sbit at 0xCE EXF2 ; /* TIMER 2 EXTERNAL FLAG */
309 sbit at 0xCF TF2 ; /* TIMER 2 OVERFLOW FLAG */
312 sbit at 0xC8 CPRL3 ; /* TIMER 3 CAPTURE SELECT */
313 sbit at 0xC9 CT3 ; /* TIMER 3 COUNTER SELECT */
314 sbit at 0xCA TR3 ; /* TIMER 3 ON/OFF CONTROL */
315 sbit at 0xCB EXEN3 ; /* TIMER 3 EXTERNAL ENABLE FLAG */
316 sbit at 0xCE EXF3 ; /* TIMER 3 EXTERNAL FLAG */
317 sbit at 0xCF TF3 ; /* TIMER 3 OVERFLOW FLAG */
320 sbit at 0xC8 CPRL4 ; /* TIMER 4 CAPTURE SELECT */
321 sbit at 0xC9 CT4 ; /* TIMER 4 COUNTER SELECT */
322 sbit at 0xCA TR4 ; /* TIMER 4 ON/OFF CONTROL */
323 sbit at 0xCB EXEN4 ; /* TIMER 4 EXTERNAL ENABLE FLAG */
324 sbit at 0xCE EXF4 ; /* TIMER 4 EXTERNAL FLAG */
325 sbit at 0xCF TF4 ; /* TIMER 4 OVERFLOW FLAG */
338 sbit at 0xD0 P ; /* ACCUMULATOR PARITY FLAG */
339 sbit at 0xD1 F1 ; /* USER FLAG 1 */
340 sbit at 0xD2 OV ; /* OVERFLOW FLAG */
341 sbit at 0xD3 RS0 ; /* REGISTER BANK SELECT 0 */
342 sbit at 0xD4 RS1 ; /* REGISTER BANK SELECT 1 */
343 sbit at 0xD5 F0 ; /* USER FLAG 0 */
344 sbit at 0xD6 AC ; /* AUXILIARY CARRY FLAG */
345 sbit at 0xD7 CY ; /* CARRY FLAG */
348 sbit at 0xD8 CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */
349 sbit at 0xD9 CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */
350 sbit at 0xDA CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */
351 sbit at 0xDB CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */
352 sbit at 0xDC CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */
353 sbit at 0xDD CCF5 ; /* PCA 0 MODULE 5 INTERRUPT FLAG */
354 sbit at 0xDE CR ; /* PCA 0 COUNTER RUN CONTROL BIT */
355 sbit at 0xDF CF ; /* PCA 0 COUNTER OVERFLOW FLAG */
368 sbit at 0xE8 AD0LJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */
369 sbit at 0xE9 AD0WINT ; /* ADC 0 WINDOW INTERRUPT FLAG */
370 sbit at 0xEA AD0CM0 ; /* ADC 0 CONVERT START MODE BIT 0 */
371 sbit at 0xEB AD0CM1 ; /* ADC 0 CONVERT START MODE BIT 1 */
372 sbit at 0xEC AD0BUSY ; /* ADC 0 BUSY FLAG */
373 sbit at 0xED AD0INT ; /* ADC 0 EOC INTERRUPT FLAG */
374 sbit at 0xEE AD0TM ; /* ADC 0 TRACK MODE */
375 sbit at 0xEF AD0EN ; /* ADC 0 ENABLE */
378 sbit at 0xE8 AD2WINT ; /* ADC 2 WINDOW INTERRUPT FLAG */
379 sbit at 0xE9 AD2CM0 ; /* ADC 2 CONVERT START MODE BIT 0 */
380 sbit at 0xEA AD2CM1 ; /* ADC 2 CONVERT START MODE BIT 1 */
381 sbit at 0xEB AD2CM2 ; /* ADC 2 CONVERT START MODE BIT 2 */
382 sbit at 0xEC AD2BUSY ; /* ADC 2 BUSY FLAG */
383 sbit at 0xED AD2INT ; /* ADC 2 EOC INTERRUPT FLAG */
384 sbit at 0xEE AD2TM ; /* ADC 2 TRACK MODE */
385 sbit at 0xEF AD2EN ; /* ADC 2 ENABLE */
398 sbit at 0xF8 SPIEN ; /* SPI 0 SPI ENABLE */
399 sbit at 0xF9 TXBMT ; /* SPI 0 TX BUFFER EMPTY FLAG */
400 sbit at 0xFA NSSMD0 ; /* SPI 0 SLAVE SELECT MODE 0 */
401 sbit at 0xFB NSSMD1 ; /* SPI 0 SLAVE SELECT MODE 1 */
402 sbit at 0xFC RXOVRN ; /* SPI 0 RX OVERRUN FLAG */
403 sbit at 0xFD MODF ; /* SPI 0 MODE FAULT FLAG */
404 sbit at 0xFE WCOL ; /* SPI 0 WRITE COLLISION FLAG */
405 sbit at 0xFF SPIF ; /* SPI 0 INTERRUPT FLAG */
418 /* Predefined SFR Bit Masks */
420 #define IDLE 0x01 /* PCON */
421 #define STOP 0x02 /* PCON */
422 #define ECCF 0x01 /* PCA0CPMn */
423 #define PWM 0x02 /* PCA0CPMn */
424 #define TOG 0x04 /* PCA0CPMn */
425 #define MAT 0x08 /* PCA0CPMn */
426 #define CAPN 0x10 /* PCA0CPMn */
427 #define CAPP 0x20 /* PCA0CPMn */
428 #define ECOM 0x40 /* PCA0CPMn */
429 #define PWM16 0x80 /* PCA0CPMn */
430 #define PORSF 0x02 /* RSTSRC */
431 #define SWRSF 0x10 /* RSTSRC */
434 /* SFR PAGE DEFINITIONS */
436 #define CONFIG_PAGE 0x0F /* SYSTEM AND PORT CONFIGURATION PAGE */
437 #define LEGACY_PAGE 0x00 /* LEGACY SFR PAGE */
438 #define TIMER01_PAGE 0x00 /* TIMER 0 AND TIMER 1 */
439 #define CPT0_PAGE 0x01 /* COMPARATOR 0 */
440 #define CPT1_PAGE 0x02 /* COMPARATOR 1 */
441 #define UART0_PAGE 0x00 /* UART 0 */
442 #define UART1_PAGE 0x01 /* UART 1 */
443 #define SPI0_PAGE 0x00 /* SPI 0 */
444 #define EMI0_PAGE 0x00 /* EXTERNAL MEMORY INTERFACE */
445 #define ADC0_PAGE 0x00 /* ADC 0 */
446 #define ADC2_PAGE 0x02 /* ADC 2 */
447 #define SMB0_PAGE 0x00 /* SMBUS 0 */
448 #define TMR2_PAGE 0x00 /* TIMER 2 */
449 #define TMR3_PAGE 0x01 /* TIMER 3 */
450 #define TMR4_PAGE 0x02 /* TIMER 4 */
451 #define DAC0_PAGE 0x00 /* DAC 0 */
452 #define DAC1_PAGE 0x01 /* DAC 1 */
453 #define PCA0_PAGE 0x00 /* PCA 0 */
454 #define PLL0_PAGE 0x0F /* PLL 0 */