1 /*-------------------------------------------------------------------------
2 Register Declarations for ATMEL 89x52 Processors
4 Written By - Bernd Bartmann
5 Bernd.Bartmann@picard.isdn.cs.tu-berlin.de (1999)
6 based on reg51.h by Sandeep Dutta sandeep.dutta@usa.net
7 KEIL C compatible definitions are included
9 This program is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published by the
11 Free Software Foundation; either version 2, or (at your option) any
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 In other words, you are welcome to use, share and improve this program.
24 You are forbidden to forbid anyone else to use, share and improve
25 what you give them. Help stamp out software-hoarding!
26 -------------------------------------------------------------------------*/
31 /* BYTE addressable registers */
36 __sfr __at 0x87 PCON ;
37 __sfr __at 0x88 TCON ;
38 __sfr __at 0x89 TMOD ;
44 __sfr __at 0x98 SCON ;
45 __sfr __at 0x99 SBUF ;
50 __sfr __at 0xC8 T2CON ;
51 __sfr __at 0xC9 T2MOD ;
52 __sfr __at 0xCA RCAP2L ;
53 __sfr __at 0xCB RCAP2H ;
62 /* BIT addressable registers */
64 __sbit __at 0x80 P0_0 ;
65 __sbit __at 0x81 P0_1 ;
66 __sbit __at 0x82 P0_2 ;
67 __sbit __at 0x83 P0_3 ;
68 __sbit __at 0x84 P0_4 ;
69 __sbit __at 0x85 P0_5 ;
70 __sbit __at 0x86 P0_6 ;
71 __sbit __at 0x87 P0_7 ;
74 __sbit __at 0x88 IT0 ;
75 __sbit __at 0x89 IE0 ;
76 __sbit __at 0x8A IT1 ;
77 __sbit __at 0x8B IE1 ;
78 __sbit __at 0x8C TR0 ;
79 __sbit __at 0x8D TF0 ;
80 __sbit __at 0x8E TR1 ;
81 __sbit __at 0x8F TF1 ;
84 __sbit __at 0x90 P1_0 ;
85 __sbit __at 0x91 P1_1 ;
86 __sbit __at 0x92 P1_2 ;
87 __sbit __at 0x93 P1_3 ;
88 __sbit __at 0x94 P1_4 ;
89 __sbit __at 0x95 P1_5 ;
90 __sbit __at 0x96 P1_6 ;
91 __sbit __at 0x97 P1_7 ;
94 __sbit __at 0x91 T2EX ;
99 __sbit __at 0x9A RB8 ;
100 __sbit __at 0x9B TB8 ;
101 __sbit __at 0x9C REN ;
102 __sbit __at 0x9D SM2 ;
103 __sbit __at 0x9E SM1 ;
104 __sbit __at 0x9F SM0 ;
107 __sbit __at 0xA0 P2_0 ;
108 __sbit __at 0xA1 P2_1 ;
109 __sbit __at 0xA2 P2_2 ;
110 __sbit __at 0xA3 P2_3 ;
111 __sbit __at 0xA4 P2_4 ;
112 __sbit __at 0xA5 P2_5 ;
113 __sbit __at 0xA6 P2_6 ;
114 __sbit __at 0xA7 P2_7 ;
117 __sbit __at 0xA8 EX0 ;
118 __sbit __at 0xA9 ET0 ;
119 __sbit __at 0xAA EX1 ;
120 __sbit __at 0xAB ET1 ;
121 __sbit __at 0xAC ES ;
122 __sbit __at 0xAD ET2 ;
123 __sbit __at 0xAF EA ;
126 __sbit __at 0xB0 P3_0 ;
127 __sbit __at 0xB1 P3_1 ;
128 __sbit __at 0xB2 P3_2 ;
129 __sbit __at 0xB3 P3_3 ;
130 __sbit __at 0xB4 P3_4 ;
131 __sbit __at 0xB5 P3_5 ;
132 __sbit __at 0xB6 P3_6 ;
133 __sbit __at 0xB7 P3_7 ;
135 __sbit __at 0xB0 RXD ;
136 __sbit __at 0xB1 TXD ;
137 __sbit __at 0xB2 INT0 ;
138 __sbit __at 0xB3 INT1 ;
139 __sbit __at 0xB4 T0 ;
140 __sbit __at 0xB5 T1 ;
141 __sbit __at 0xB6 WR ;
142 __sbit __at 0xB7 RD ;
145 __sbit __at 0xB8 PX0 ;
146 __sbit __at 0xB9 PT0 ;
147 __sbit __at 0xBA PX1 ;
148 __sbit __at 0xBB PT1 ;
149 __sbit __at 0xBC PS ;
150 __sbit __at 0xBD PT2 ;
153 __sbit __at 0xC8 T2CON_0 ;
154 __sbit __at 0xC9 T2CON_1 ;
155 __sbit __at 0xCA T2CON_2 ;
156 __sbit __at 0xCB T2CON_3 ;
157 __sbit __at 0xCC T2CON_4 ;
158 __sbit __at 0xCD T2CON_5 ;
159 __sbit __at 0xCE T2CON_6 ;
160 __sbit __at 0xCF T2CON_7 ;
162 __sbit __at 0xC8 CP_RL2 ;
163 __sbit __at 0xC9 C_T2 ;
164 __sbit __at 0xCA TR2 ;
165 __sbit __at 0xCB EXEN2 ;
166 __sbit __at 0xCC TCLK ;
167 __sbit __at 0xCD RCLK ;
168 __sbit __at 0xCE EXF2 ;
169 __sbit __at 0xCF TF2 ;
173 __sbit __at 0xD1 FL ;
174 __sbit __at 0xD2 OV ;
175 __sbit __at 0xD3 RS0 ;
176 __sbit __at 0xD4 RS1 ;
177 __sbit __at 0xD5 F0 ;
178 __sbit __at 0xD6 AC ;
179 __sbit __at 0xD7 CY ;
182 /* BIT definitions for bits that are not directly accessible */
227 #define T0_GATE_ 0x08
231 #define T1_GATE_ 0x80
236 #define T0_MASK_ 0x0F
237 #define T1_MASK_ 0xF0
247 /* Interrupt numbers: address = (number * 8) + 3 */
248 #define IE0_VECTOR 0 /* 0x03 external interrupt 0 */
249 #define TF0_VECTOR 1 /* 0x0b timer 0 */
250 #define IE1_VECTOR 2 /* 0x13 external interrupt 1 */
251 #define TF1_VECTOR 3 /* 0x1b timer 1 */
252 #define SI0_VECTOR 4 /* 0x23 serial port 0 */
253 #define TF2_VECTOR 5 /* 0x2B timer 2 */
254 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */