1 /*-------------------------------------------------------------------------
2 Register Declarations for ATMEL 89x51 Processors
4 Written By - Bernd Bartmann
5 Bernd.Bartmann@picard.isdn.cs.tu-berlin.de (1999)
6 based on reg51.h by Sandeep Dutta sandeep.dutta@usa.net
7 KEIL C compatible definitions are included
9 This program is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published by the
11 Free Software Foundation; either version 2, or (at your option) any
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 In other words, you are welcome to use, share and improve this program.
24 You are forbidden to forbid anyone else to use, share and improve
25 what you give them. Help stamp out software-hoarding!
26 -------------------------------------------------------------------------*/
31 /* BYTE addressable registers */
36 __sfr __at 0x87 PCON ;
37 __sfr __at 0x88 TCON ;
38 __sfr __at 0x89 TMOD ;
44 __sfr __at 0x98 SCON ;
45 __sfr __at 0x99 SBUF ;
56 /* BIT addressable registers */
58 __sbit __at 0x80 P0_0 ;
59 __sbit __at 0x81 P0_1 ;
60 __sbit __at 0x82 P0_2 ;
61 __sbit __at 0x83 P0_3 ;
62 __sbit __at 0x84 P0_4 ;
63 __sbit __at 0x85 P0_5 ;
64 __sbit __at 0x86 P0_6 ;
65 __sbit __at 0x87 P0_7 ;
68 __sbit __at 0x88 IT0 ;
69 __sbit __at 0x89 IE0 ;
70 __sbit __at 0x8A IT1 ;
71 __sbit __at 0x8B IE1 ;
72 __sbit __at 0x8C TR0 ;
73 __sbit __at 0x8D TF0 ;
74 __sbit __at 0x8E TR1 ;
75 __sbit __at 0x8F TF1 ;
78 __sbit __at 0x90 P1_0 ;
79 __sbit __at 0x91 P1_1 ;
80 __sbit __at 0x92 P1_2 ;
81 __sbit __at 0x93 P1_3 ;
82 __sbit __at 0x94 P1_4 ;
83 __sbit __at 0x95 P1_5 ;
84 __sbit __at 0x96 P1_6 ;
85 __sbit __at 0x97 P1_7 ;
90 __sbit __at 0x9A RB8 ;
91 __sbit __at 0x9B TB8 ;
92 __sbit __at 0x9C REN ;
93 __sbit __at 0x9D SM2 ;
94 __sbit __at 0x9E SM1 ;
95 __sbit __at 0x9F SM0 ;
98 __sbit __at 0xA0 P2_0 ;
99 __sbit __at 0xA1 P2_1 ;
100 __sbit __at 0xA2 P2_2 ;
101 __sbit __at 0xA3 P2_3 ;
102 __sbit __at 0xA4 P2_4 ;
103 __sbit __at 0xA5 P2_5 ;
104 __sbit __at 0xA6 P2_6 ;
105 __sbit __at 0xA7 P2_7 ;
108 __sbit __at 0xA8 EX0 ;
109 __sbit __at 0xA9 ET0 ;
110 __sbit __at 0xAA EX1 ;
111 __sbit __at 0xAB ET1 ;
112 __sbit __at 0xAC ES ;
113 __sbit __at 0xAF EA ;
116 __sbit __at 0xB0 P3_0 ;
117 __sbit __at 0xB1 P3_1 ;
118 __sbit __at 0xB2 P3_2 ;
119 __sbit __at 0xB3 P3_3 ;
120 __sbit __at 0xB4 P3_4 ;
121 __sbit __at 0xB5 P3_5 ;
122 __sbit __at 0xB6 P3_6 ;
123 __sbit __at 0xB7 P3_7 ;
125 __sbit __at 0xB0 RXD ;
126 __sbit __at 0xB1 TXD ;
127 __sbit __at 0xB2 INT0 ;
128 __sbit __at 0xB3 INT1 ;
129 __sbit __at 0xB4 T0 ;
130 __sbit __at 0xB5 T1 ;
131 __sbit __at 0xB6 WR ;
132 __sbit __at 0xB7 RD ;
135 __sbit __at 0xB8 PX0 ;
136 __sbit __at 0xB9 PT0 ;
137 __sbit __at 0xBA PX1 ;
138 __sbit __at 0xBB PT1 ;
139 __sbit __at 0xBC PS ;
143 __sbit __at 0xD1 FL ;
144 __sbit __at 0xD2 OV ;
145 __sbit __at 0xD3 RS0 ;
146 __sbit __at 0xD4 RS1 ;
147 __sbit __at 0xD5 F0 ;
148 __sbit __at 0xD6 AC ;
149 __sbit __at 0xD7 CY ;
152 /* BIT definitions for bits that are not directly accessible */
197 #define T0_GATE_ 0x08
201 #define T1_GATE_ 0x80
206 #define T0_MASK_ 0x0F
207 #define T1_MASK_ 0xF0
210 /* Interrupt numbers: address = (number * 8) + 3 */
211 #define IE0_VECTOR 0 /* 0x03 external interrupt 0 */
212 #define TF0_VECTOR 1 /* 0x0b timer 0 */
213 #define IE1_VECTOR 2 /* 0x13 external interrupt 1 */
214 #define TF1_VECTOR 3 /* 0x1b timer 1 */
215 #define SI0_VECTOR 4 /* 0x23 serial port 0 */