1 /*-------------------------------------------------------------------------
2 Register Declarations for ATMEL 89S8253 Processors
4 Written By - Krzysztof Polomka <del_p@op.pl>
6 based on at89S8252.h By - Dipl.-Ing. (FH) Michael Schmitt
7 mschmitt@mainz-online.de
8 michael.schmitt@t-online.de
12 Additional definitions Nov 23 1999
13 by Bernd Krueger-Knauber <bkk@infratec-plus.de>
15 based on reg51.h by Sandeep Dutta sandeep.dutta@usa.net
16 KEIL C compatible definitions are included
18 This program is free software; you can redistribute it and/or modify it
19 under the terms of the GNU General Public License as published by the
20 Free Software Foundation; either version 2, or (at your option) any
23 This program is distributed in the hope that it will be useful,
24 but WITHOUT ANY WARRANTY; without even the implied warranty of
25 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 GNU General Public License for more details.
28 You should have received a copy of the GNU General Public License
29 along with this program; if not, write to the Free Software
30 Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
32 In other words, you are welcome to use, share and improve this program.
33 You are forbidden to forbid anyone else to use, share and improve
34 what you give them. Help stamp out software-hoarding!
35 -------------------------------------------------------------------------*/
40 /* BYTE addressable registers */
41 __sfr __at (0x80) P0 ;
42 __sfr __at (0x81) SP ;
43 __sfr __at (0x82) DPL ;
44 __sfr __at (0x82) DP0L ; /* as called by Atmel */
45 __sfr __at (0x83) DPH ;
46 __sfr __at (0x83) DP0H ; /* as called by Atmel */
47 __sfr __at (0x84) DP1L ; /* at89S8253 specific register */
48 __sfr __at (0x85) DP1H ; /* at89S8253 specific register */
49 __sfr __at (0x86) SPDR ; /* at89S8253 specific register */
50 __sfr __at (0x87) PCON ;
51 __sfr __at (0x88) TCON ;
52 __sfr __at (0x89) TMOD ;
53 __sfr __at (0x8A) TL0 ;
54 __sfr __at (0x8B) TL1 ;
55 __sfr __at (0x8C) TH0 ;
56 __sfr __at (0x8D) TH1 ;
57 __sfr __at (0x8E) AUXR ; /* at89S8253 specific register */
58 __sfr __at (0x8F) CLKREG ; /* at89S8253 specific register */
59 __sfr __at (0x90) P1 ;
60 __sfr __at (0x96) EECON ; /* at89S8253 specific register */
61 __sfr __at (0x98) SCON ;
62 __sfr __at (0x99) SBUF ;
63 __sfr __at (0xA0) P2 ;
64 __sfr __at (0xA6) WDTRST ; /* at89S8253 specific register */
65 __sfr __at (0xA7) WDTCON ; /* at89S8253 specific register */
66 __sfr __at (0xA8) IE ;
67 __sfr __at (0xA9) SADDR ; /* at89S8253 specific register */
68 __sfr __at (0xAA) SPSR ; /* at89S8253 specific register */
69 __sfr __at (0xB0) P3 ;
70 __sfr __at (0xB7) IPH ; /* at89S8253 specific register */
71 __sfr __at (0xB8) IP ;
72 __sfr __at (0xB9) SADEN ; /* at89S8253 specific register */
73 __sfr __at (0xC8) T2CON ;
74 __sfr __at (0xC9) T2MOD ;
75 __sfr __at (0xCA) RCAP2L ;
76 __sfr __at (0xCB) RCAP2H ;
77 __sfr __at (0xCC) TL2 ;
78 __sfr __at (0xCD) TH2 ;
79 __sfr __at (0xD0) PSW ;
80 __sfr __at (0xD5) SPCR ; /* at89S8253 specific register */
81 __sfr __at (0xE0) ACC ;
86 /* BIT addressable registers */
88 __sbit __at (0x80) P0_0 ;
89 __sbit __at (0x81) P0_1 ;
90 __sbit __at (0x82) P0_2 ;
91 __sbit __at (0x83) P0_3 ;
92 __sbit __at (0x84) P0_4 ;
93 __sbit __at (0x85) P0_5 ;
94 __sbit __at (0x86) P0_6 ;
95 __sbit __at (0x87) P0_7 ;
98 __sbit __at (0x88) IT0 ;
99 __sbit __at (0x89) IE0 ;
100 __sbit __at (0x8A) IT1 ;
101 __sbit __at (0x8B) IE1 ;
102 __sbit __at (0x8C) TR0 ;
103 __sbit __at (0x8D) TF0 ;
104 __sbit __at (0x8E) TR1 ;
105 __sbit __at (0x8F) TF1 ;
108 __sbit __at (0x90) P1_0 ;
109 __sbit __at (0x91) P1_1 ;
110 __sbit __at (0x92) P1_2 ;
111 __sbit __at (0x93) P1_3 ;
112 __sbit __at (0x94) P1_4 ;
113 __sbit __at (0x95) P1_5 ;
114 __sbit __at (0x96) P1_6 ;
115 __sbit __at (0x97) P1_7 ;
117 __sbit __at (0x90) T2 ;
118 __sbit __at (0x91) T2EX ;
120 /* P1 SPI portpins */
121 __sbit __at (0x94) SS ; /* SPI: SS - Slave port select input */
122 __sbit __at (0x95) MOSI ; /* SPI: MOSI - Master data output, slave data input */
123 __sbit __at (0x96) MISO ; /* SPI: MISO - Master data input, slave data output */
124 __sbit __at (0x97) SCK ; /* SPI: SCK - Master clock output, slave clock input */
128 __sbit __at (0x98) RI ;
129 __sbit __at (0x99) TI ;
130 __sbit __at (0x9A) RB8 ;
131 __sbit __at (0x9B) TB8 ;
132 __sbit __at (0x9C) REN ;
133 __sbit __at (0x9D) SM2 ;
134 __sbit __at (0x9E) SM1 ;
135 __sbit __at (0x9F) SM0 ;
138 __sbit __at (0xA0) P2_0 ;
139 __sbit __at (0xA1) P2_1 ;
140 __sbit __at (0xA2) P2_2 ;
141 __sbit __at (0xA3) P2_3 ;
142 __sbit __at (0xA4) P2_4 ;
143 __sbit __at (0xA5) P2_5 ;
144 __sbit __at (0xA6) P2_6 ;
145 __sbit __at (0xA7) P2_7 ;
148 __sbit __at (0xA8) EX0 ;
149 __sbit __at (0xA9) ET0 ;
150 __sbit __at (0xAA) EX1 ;
151 __sbit __at (0xAB) ET1 ;
152 __sbit __at (0xAC) ES ;
153 __sbit __at (0xAD) ET2 ;
154 __sbit __at (0xAF) EA ;
157 __sbit __at (0xB0) P3_0 ;
158 __sbit __at (0xB1) P3_1 ;
159 __sbit __at (0xB2) P3_2 ;
160 __sbit __at (0xB3) P3_3 ;
161 __sbit __at (0xB4) P3_4 ;
162 __sbit __at (0xB5) P3_5 ;
163 __sbit __at (0xB6) P3_6 ;
164 __sbit __at (0xB7) P3_7 ;
166 __sbit __at (0xB0) RXD ;
167 __sbit __at (0xB1) TXD ;
168 __sbit __at (0xB2) INT0 ;
169 __sbit __at (0xB3) INT1 ;
170 __sbit __at (0xB4) T0 ;
171 __sbit __at (0xB5) T1 ;
172 __sbit __at (0xB6) WR ;
173 __sbit __at (0xB7) RD ;
176 __sbit __at (0xB8) PX0 ;
177 __sbit __at (0xB9) PT0 ;
178 __sbit __at (0xBA) PX1 ;
179 __sbit __at (0xBB) PT1 ;
180 __sbit __at (0xBC) PS ;
181 __sbit __at (0xBD) PT2 ;
184 __sbit __at (0xC8) T2CON_0 ;
185 __sbit __at (0xC9) T2CON_1 ;
186 __sbit __at (0xCA) T2CON_2 ;
187 __sbit __at (0xCB) T2CON_3 ;
188 __sbit __at (0xCC) T2CON_4 ;
189 __sbit __at (0xCD) T2CON_5 ;
190 __sbit __at (0xCE) T2CON_6 ;
191 __sbit __at (0xCF) T2CON_7 ;
193 __sbit __at (0xC8) CP_RL2 ;
194 __sbit __at (0xC9) C_T2 ;
195 __sbit __at (0xCA) TR2 ;
196 __sbit __at (0xCB) EXEN2 ;
197 __sbit __at (0xCC) TCLK ;
198 __sbit __at (0xCD) RCLK ;
199 __sbit __at (0xCE) EXF2 ;
200 __sbit __at (0xCF) TF2 ;
203 __sbit __at (0xD0) P ;
204 __sbit __at (0xD1) FL ;
205 __sbit __at (0xD2) OV ;
206 __sbit __at (0xD3) RS0 ;
207 __sbit __at (0xD4) RS1 ;
208 __sbit __at (0xD5) F0 ;
209 __sbit __at (0xD6) AC ;
210 __sbit __at (0xD7) CY ;
213 __sbit __at (0xF0) BREG_F0 ;
214 __sbit __at (0xF1) BREG_F1 ;
215 __sbit __at (0xF2) BREG_F2 ;
216 __sbit __at (0xF3) BREG_F3 ;
217 __sbit __at (0xF4) BREG_F4 ;
218 __sbit __at (0xF5) BREG_F5 ;
219 __sbit __at (0xF6) BREG_F6 ;
220 __sbit __at (0xF7) BREG_F7 ;
223 /* BIT definitions for bits that are not directly accessible */
268 #define T0_GATE_ 0x08
272 #define T1_GATE_ 0x80
277 #define T0_MASK_ 0x0F
278 #define T1_MASK_ 0xF0
288 #define EECON_WRTINH 0x01
289 #define EECON_RDY 0x02
290 #define EECON_DPS 0x04
291 #define EECON_EEMEN 0x08
292 #define EECON_EEMWE 0x10
293 #define EECON_EELD 0x20
296 #define WDTCON_WDTEN 0x01
297 #define WDTCON_WSWRST 0x02
298 #define WDTCON_HWDT 0x04
299 #define WDTCON_DISRTO 0x08
300 #define WDTCON_WDIDLE 0x10
301 #define WDTCON_PS0 0x20
302 #define WDTCON_PS1 0x40
303 #define WDTCON_PS2 0x80
306 #define SPCR_SPR0 0x01
307 #define SPCR_SPR1 0x02
308 #define SPCR_CPHA 0x04
309 #define SPCR_CPOL 0x08
310 #define SPCR_MSTR 0x10
311 #define SPCR_DORD 0x20
312 #define SPCR_SPE 0x40
313 #define SPCR_SPIE 0x80
316 #define SPSR_ENH 0x01
317 #define SPSR_DISSO 0x02
318 #define SPSR_LDEN 0x20
319 #define SPSR_WCOL 0x40
320 #define SPSR_SPIF 0x80
323 #define SPDR_SPD0 0x01
324 #define SPDR_SPD1 0x02
325 #define SPDR_SPD2 0x04
326 #define SPDR_SPD3 0x08
327 #define SPDR_SPD4 0x10
328 #define SPDR_SPD5 0x20
329 #define SPDR_SPD6 0x40
330 #define SPDR_SPD7 0x80
333 #define IPH_PX0H 0x01
334 #define IPH_PT0H 0x02
335 #define IPH_PX1H 0x04
336 #define IPH_PT1H 0x08
338 #define IPH_PT2H 0x20
340 /* Interrupt numbers: address = (number * 8) + 3 */
341 #define IE0_VECTOR 0 /* 0x03 external interrupt 0 */
342 #define EX0_VECTOR 0 /* 0x03 external interrupt 0 */
343 #define TF0_VECTOR 1 /* 0x0b timer 0 */
344 #define IE1_VECTOR 2 /* 0x13 external interrupt 1 */
345 #define EX1_VECTOR 2 /* 0x13 external interrupt 1 */
346 #define TF1_VECTOR 3 /* 0x1b timer 1 */
347 #define SI0_VECTOR 4 /* 0x23 serial port 0 */
348 #define TF2_VECTOR 5 /* 0x2B timer 2 */
349 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
352 #define AUXR_DISALE 0x01
353 #define AUXR_INTEL_PWD_EXIT 0x02
356 #define CLKREG_X2 0x01
358 /* This is one of the addons coming from Bernd Krueger-Knauber */
360 /* ALE (0x8E) Bit Values */
361 __sfr __at (0x8E) ALE; /* at89S8252 specific register */
363 /* Macro to enable and disable the toggling of the ALE-pin (EMV) */
365 /* Explanation : Original Intel 8051 Cores (Atmel has to use the */
366 /* Intel Core) have a feature that ALE is only active during */
367 /* MOVX or MOVC instruction. Otherwise the ALE-Pin is weakly */
368 /* pulled high. This can be used to force some external devices */
369 /* into standby mode and reduced EMI noise */
371 #define ALE_OFF ALE = ALE | 0x01
372 #define ALE_ON ALE = ALE & 0xFE