1 /*-------------------------------------------------------------------------
2 Register Declarations for the Atmel AT89C51SND1C Processor
4 Written By - Weston Schmidt <weston_schmidt@alumni.purdue.edu> (Sept 2005)
6 This document is based on the AT8xC51SND1C document
9 $Id: at89c51snd1c.h 4388 2006-09-27 09:31:14Z MaartenBrock $
11 This library is free software; you can redistribute it and/or
12 modify it under the terms of the GNU Lesser General Public
13 License as published by the Free Software Foundation; either
14 version 2.1 of the License, or (at your option) any later version.
16 This library is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 Lesser General Public License for more details.
21 You should have received a copy of the GNU Lesser General Public
22 License along with this library; if not, write to the Free Software
23 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 In other words, you are welcome to use, share and improve this program.
26 You are forbidden to forbid anyone else to use, share and improve
27 what you give them. Help stamp out software-hoarding!
28 -------------------------------------------------------------------------*/
30 #ifndef __AT89C51SND1_H__
31 #define __AT89C51SND1_H__
35 __sfr __at (0xE0) ACC ; /* C51 Core SFRs */
37 __sfr __at (0xD0) PSW ;
38 __sfr __at (0x81) SP ;
39 __sfr __at (0x82) DPL ;
40 __sfr __at (0x83) DPH ;
41 __sfr __at (0x87) PCON ; /* System Management SFRs */
42 __sfr __at (0x8E) AUXR0 ;
43 __sfr __at (0xA2) AUXR1 ;
44 __sfr __at (0xFB) NVERS ;
45 __sfr __at (0x8F) CKCON ; /* PLL and System Clock SFRs */
46 __sfr __at (0xE9) PLLCON ;
47 __sfr __at (0xEE) PLLNDIV ;
48 __sfr __at (0xEF) PLLRDIV ;
49 __sfr __at (0xA8) IEN0 ; /* Interrupt SFRs */
50 __sfr __at (0xB1) IEN1 ;
51 __sfr __at (0xB7) IPH0 ;
52 __sfr __at (0xB8) IPL0 ;
53 __sfr __at (0xB3) IPH1 ;
54 __sfr __at (0xB2) IPL1 ;
55 __sfr __at (0x80) P0 ; /* Port SFRs */
56 __sfr __at (0x90) P1 ;
57 __sfr __at (0xA0) P2 ;
58 __sfr __at (0xB0) P3 ;
59 __sfr __at (0xC0) P4 ;
60 __sfr __at (0xD8) P5 ;
61 __sfr __at (0xD1) FCON ; /* Flash Memory SFR */
62 __sfr __at (0x88) TCON ; /* Timer SFRs */
63 __sfr __at (0x89) TMOD ;
64 __sfr __at (0x8A) TL0 ;
65 __sfr __at (0x8C) TH0 ;
66 __sfr __at (0x8B) TL1 ;
67 __sfr __at (0x8D) TH1 ;
68 __sfr __at (0xA6) WDTRST ;
69 __sfr __at (0xA7) WDTPRG ;
70 __sfr __at (0xAA) MP3CON ; /* MP3 Decoder SFRs */
71 __sfr __at (0xC8) MP3STA ;
72 __sfr __at (0xAF) MP3STA1 ;
73 __sfr __at (0xAC) MP3DAT ;
74 __sfr __at (0xAD) MP3ANC ;
75 __sfr __at (0x9E) MP3VOL ;
76 __sfr __at (0x9F) MP3VOR ;
77 __sfr __at (0xB4) MP3BAS ;
78 __sfr __at (0xB5) MP3MED ;
79 __sfr __at (0xB6) MP3TRE ;
80 __sfr __at (0xEB) MP3CLK ;
81 __sfr __at (0xAE) MP3DBG ;
82 __sfr __at (0x9A) AUDCON0 ; /* Audio Interface SFRs */
83 __sfr __at (0x9B) AUDCON1 ;
84 __sfr __at (0x9C) AUDSTA ;
85 __sfr __at (0x9D) AUDDAT ;
86 __sfr __at (0xEC) AUDCLK ;
87 __sfr __at (0xBC) USBCON ; /* USB Controller SFRs */
88 __sfr __at (0xC6) USBADDR ;
89 __sfr __at (0xBD) USBINT ;
90 __sfr __at (0xBE) USBIEN ;
91 __sfr __at (0xC7) UEPNUM ;
92 __sfr __at (0xD4) UEPCONX ;
93 __sfr __at (0xCE) UEPSTAX ;
94 __sfr __at (0xD5) UEPRST ;
95 __sfr __at (0xF8) UEPINT ;
96 __sfr __at (0xC2) UEPIEN ;
97 __sfr __at (0xCF) UEPDATX ;
98 __sfr __at (0xE2) UBYCTX ;
99 __sfr __at (0xBA) UFNUML ;
100 __sfr __at (0xBB) UFNUMH ;
101 __sfr __at (0xEA) USBCLK ;
102 __sfr __at (0xE4) MMCON0 ; /* MMC Controller SFRs */
103 __sfr __at (0xE5) MMCON1 ;
104 __sfr __at (0xE6) MMCON2 ;
105 __sfr __at (0xDE) MMSTA ;
106 __sfr __at (0xE7) MMINT ;
107 __sfr __at (0xDF) MMMSK ;
108 __sfr __at (0xDD) MMCMD ;
109 __sfr __at (0xDC) MMDAT ;
110 __sfr __at (0xED) MMCLK ;
111 __sfr __at (0xF9) DAT16H ; /* IDE Interface SFR */
112 __sfr __at (0x98) SCON ; /* Serial I/O Port SFRs */
113 __sfr __at (0x99) SBUF ;
114 __sfr __at (0xB9) SADEN ;
115 __sfr __at (0xA9) SADDR ;
116 __sfr __at (0x92) BDRCON ;
117 __sfr __at (0x91) BRL ;
118 __sfr __at (0xC3) SPCON ; /* SPI Controller SFRs */
119 __sfr __at (0xC4) SPSTA ;
120 __sfr __at (0xC5) SPDAT ;
121 __sfr __at (0x93) SSCON ; /* Two Wire Controller SFRs */
122 __sfr __at (0x94) SSSTA ;
123 __sfr __at (0x95) SSDAT ;
124 __sfr __at (0x96) SSADR ;
125 __sfr __at (0xA3) KBCON ; /* Keyboard Interface SFRs */
126 __sfr __at (0xA4) KBSTA ;
127 __sfr __at (0xF3) ADCON ; /* A/D Controller SFRs */
128 __sfr __at (0xF4) ADDL ;
129 __sfr __at (0xF5) ADDH ;
130 __sfr __at (0xF2) ADCLK ;
135 __sbit __at (0xD7) CY ;
136 __sbit __at (0xD6) AC ;
137 __sbit __at (0xD5) F0 ;
138 __sbit __at (0xD4) RS1 ;
139 __sbit __at (0xD3) RS0 ;
140 __sbit __at (0xD2) OV ;
141 __sbit __at (0xD1) F1 ;
142 __sbit __at (0xD0) P ;
145 __sbit __at (0xAF) EA ;
146 __sbit __at (0xAE) EAUD ;
147 __sbit __at (0xAD) EMP3 ;
148 __sbit __at (0xAC) ES ;
149 __sbit __at (0xAB) ET1 ;
150 __sbit __at (0xAA) EX1 ;
151 __sbit __at (0xA9) ET0 ;
152 __sbit __at (0xA8) EX0 ;
155 __sbit __at (0xBE) IPLAUD ;
156 __sbit __at (0xBD) IPLMP3 ;
157 __sbit __at (0xBC) IPLS ;
158 __sbit __at (0xBB) IPLT1 ;
159 __sbit __at (0xBA) IPLX1 ;
160 __sbit __at (0xB9) IPLT0 ;
161 __sbit __at (0xB8) IPLX0 ;
164 __sbit __at (0x87) P0_7 ;
165 __sbit __at (0x86) P0_6 ;
166 __sbit __at (0x85) P0_5 ;
167 __sbit __at (0x84) P0_4 ;
168 __sbit __at (0x83) P0_3 ;
169 __sbit __at (0x82) P0_2 ;
170 __sbit __at (0x81) P0_1 ;
171 __sbit __at (0x80) P0_0 ;
174 __sbit __at (0x97) P1_7 ;
175 __sbit __at (0x96) P1_6 ;
176 __sbit __at (0x95) P1_5 ;
177 __sbit __at (0x94) P1_4 ;
178 __sbit __at (0x93) P1_3 ;
179 __sbit __at (0x92) P1_2 ;
180 __sbit __at (0x91) P1_1 ;
181 __sbit __at (0x90) P1_0 ;
183 __sbit __at (0x97) SDA ;
184 __sbit __at (0x96) SCL ;
185 __sbit __at (0x93) KIN3 ;
186 __sbit __at (0x92) KIN2 ;
187 __sbit __at (0x91) KIN1 ;
188 __sbit __at (0x90) KIN0 ;
191 __sbit __at (0xA7) P2_7 ;
192 __sbit __at (0xA6) P2_6 ;
193 __sbit __at (0xA5) P2_5 ;
194 __sbit __at (0xA4) P2_4 ;
195 __sbit __at (0xA3) P2_3 ;
196 __sbit __at (0xA2) P2_2 ;
197 __sbit __at (0xA1) P2_1 ;
198 __sbit __at (0xA0) P2_0 ;
201 __sbit __at (0xB7) P3_7 ;
202 __sbit __at (0xB6) P3_6 ;
203 __sbit __at (0xB5) P3_5 ;
204 __sbit __at (0xB4) P3_4 ;
205 __sbit __at (0xB3) P3_3 ;
206 __sbit __at (0xB2) P3_2 ;
207 __sbit __at (0xB1) P3_1 ;
208 __sbit __at (0xB0) P3_0 ;
210 __sbit __at (0xB7) RD ;
211 __sbit __at (0xB6) WR ;
212 __sbit __at (0xB5) T1 ;
213 __sbit __at (0xB4) T0 ;
214 __sbit __at (0xB3) INT1 ;
215 __sbit __at (0xB2) INT0 ;
216 __sbit __at (0xB1) TXD ;
217 __sbit __at (0xB0) RXD ;
220 __sbit __at (0xC7) P4_7 ;
221 __sbit __at (0xC6) P4_6 ;
222 __sbit __at (0xC5) P4_5 ;
223 __sbit __at (0xC4) P4_4 ;
224 __sbit __at (0xC3) P4_3 ;
225 __sbit __at (0xC2) P4_2 ;
226 __sbit __at (0xC1) P4_1 ;
227 __sbit __at (0xC0) P4_0 ;
229 __sbit __at (0xC3) SS_ ;
230 __sbit __at (0xC2) SCK ;
231 __sbit __at (0xC1) MOSI ;
232 __sbit __at (0xC0) MISO ;
235 __sbit __at (0xDB) P5_3 ;
236 __sbit __at (0xDA) P5_2 ;
237 __sbit __at (0xD9) P5_1 ;
238 __sbit __at (0xD8) P5_0 ;
241 __sbit __at (0x8F) TF1 ;
242 __sbit __at (0x8E) TR1 ;
243 __sbit __at (0x8D) TF0 ;
244 __sbit __at (0x8C) TR0 ;
245 __sbit __at (0x8B) IE1 ;
246 __sbit __at (0x8A) IT1 ;
247 __sbit __at (0x89) IE0 ;
248 __sbit __at (0x88) IT0 ;
251 __sbit __at (0xCF) MPANC ;
252 __sbit __at (0xCE) MPREQ ;
253 __sbit __at (0xCD) ERRLAY ;
254 __sbit __at (0xCC) ERRSYN ;
255 __sbit __at (0xCB) ERRCRC ;
256 __sbit __at (0xCA) MPFS1 ;
257 __sbit __at (0xC9) MPFS0 ;
258 __sbit __at (0xC8) MPVER ;
261 __sbit __at (0xFA) EP2INT ;
262 __sbit __at (0xF9) EP1INT ;
263 __sbit __at (0xF8) EP0INT ;
266 __sbit __at (0x9F) SM0 ;
267 __sbit __at (0x9F) FE ;
268 __sbit __at (0x9E) SM1 ;
269 __sbit __at (0x9D) SM2 ;
270 __sbit __at (0x9C) REN ;
271 __sbit __at (0x9B) TB8 ;
272 __sbit __at (0x9A) RB8 ;
273 __sbit __at (0x99) TI ;
274 __sbit __at (0x98) RI ;
277 /* BIT definitions for bits that are not directly accessible */
279 #define MSK_SMOD1 0x80
280 #define MSK_SMOD0 0x40
287 #define MSK_EXT16 0x40
289 #define MSK_DPHDIS 0x10
291 #define MSK_EXTRAM 0x02
295 #define MSK_ENBOOT 0x20
303 #define MSK_PLL_R 0xC0
304 #define MSK_PLLRES 0x08
305 #define MSK_PLLEN 0x02
306 #define MSK_PLOCK 0x01
309 #define MSK_PLL_N 0x7F
312 #define MSK_EUSB 0x40
314 #define MSK_EADC 0x08
315 #define MSK_ESPI 0x04
316 #define MSK_EI2C 0x02
317 #define MSK_EMMC 0x01
320 #define MSK_IPHAUD 0x40
321 #define MSK_IPHMP3 0x20
322 #define MSK_IPHS 0x10
323 #define MSK_IPHT1 0x08
324 #define MSK_IPHX1 0x04
325 #define MSK_IPHT0 0x02
326 #define MSK_IPHX0 0x01
329 #define MSK_IPHUSB 0x40
330 #define MSK_IPHKB 0x10
331 #define MSK_IPHADC 0x08
332 #define MSK_IPHSPI 0x04
333 #define MSK_IPHI2C 0x02
334 #define MSK_IPHMMC 0x01
337 #define MSK_IPLUSB 0x40
338 #define MSK_IPLKB 0x10
339 #define MSK_IPLADC 0x08
340 #define MSK_IPLSPI 0x04
341 #define MSK_IPLI2C 0x02
342 #define MSK_IPLMMC 0x01
345 #define MSK_GATE1 0x80
346 #define MSK_C_T1 0x40
348 #define MSK_GATE0 0x08
349 #define MSK_C_T0 0x04
353 #define MSK_MPEN 0x80
354 #define MSK_MPBBST 0x40
355 #define MSK_CRCEN 0x20
356 #define MSK_MSKANC 0x10
357 #define MSK_MSKREQ 0x08
358 #define MSK_MSKLAY 0x04
359 #define MSK_MSKSYN 0x02
360 #define MSK_MSKCRC 0x01
363 #define MSK_MPFREQ 0x10
364 #define MSK_MPBREQ 0x08
382 #define MSK_MPCD 0x1F
385 #define MSK_MPFULL 0x08
388 #define MSK_JUST 0xF8
390 #define MSK_DSIZ 0x02
395 #define MSK_DRQEN 0x40
396 #define MSK_MSREQ 0x20
397 #define MSK_MUDRN 0x10
399 #define MSK_AUDEN 0x01
402 #define MSK_SREQ 0x80
403 #define MSK_UDRN 0x40
404 #define MSK_AUBUSY 0x20
407 #define MSK_AUCD 0x1F
410 #define MSK_USBE 0x80
411 #define MSK_SUSPCLK 0x40
412 #define MSK_SDRMWUP 0x20
413 #define MSK_UPRSM 0x08
414 #define MSK_RMWUPE 0x04
415 #define MSK_CONFG 0x02
416 #define MSK_FADDEN 0x01
420 #define MSK_UADD 0x7F
423 #define MSK_WUPCPU 0x20
424 #define MSK_EORINT 0x10
425 #define MSK_SOFINT 0x08
426 #define MSK_SPINT 0x01
429 #define MSK_EWUPCPU 0x20
430 #define MSK_EEORINT 0x10
431 #define MSK_ESOFINT 0x08
432 #define MSK_ESPINT 0x01
435 #define MSK_EPNUM 0x03
438 #define MSK_EPEN 0x80
439 #define MSK_NAKIEN 0x40
440 #define MSK_NAKOUT 0x20
441 #define MSK_NAKIN 0x10
442 #define MSK_DTGL 0x08
443 #define MSK_EPDIR 0x04
444 #define MSK_EPTYPE 0x03
448 #define MSK_RXOUTB1 0x40
449 #define MSK_STALLRQ 0x20
450 #define MSK_TXRDY 0x10
451 #define MSK_STLCRC 0x08
452 #define MSK_RXSETUP 0x04
453 #define MSK_RXOUTB0 0x02
454 #define MSK_TXCMP 0x01
457 #define MSK_EPRST 0x07
458 #define MSK_EP2RST 0x04
459 #define MSK_EP1RST 0x02
460 #define MSK_EP0RST 0x01
462 #define MSK_EPINT 0x07
463 #define MSK_EP2INT 0x04
464 #define MSK_EP1INT 0x02
465 #define MSK_EP0INT 0x01
468 #define MSK_EPINTE 0x07
469 #define MSK_EP2INTE 0x04
470 #define MSK_EP1INTE 0x02
471 #define MSK_EP0INTE 0x01
474 #define MSK_BYCT 0x7F
477 #define MSK_CRCOK 0x20
478 #define MSK_CRCERR 0x10
479 #define MSK_FNUM 0x07
482 #define MSK_USBCD 0x03
485 #define MSK_DRPTR 0x80
486 #define MSK_DTPTR 0x40
487 #define MSK_CRPTR 0x20
488 #define MSK_CTPTR 0x10
489 #define MSK_MBLOCK 0x08
490 #define MSK_DFMT 0x04
491 #define MSK_RFMT 0x02
492 #define MSK_CRCDIS 0x01
495 #define MSK_BLEN 0xf0
496 #define MSK_DATDIR 0x08
497 #define MSK_DATEN 0x04
498 #define MSK_RESPEN 0x02
499 #define MSK_CMDEN 0x01
502 #define MSK_MMCEN 0x80
505 #define MSK_DATD 0x06
506 #define MSK_FLOWC 0x01
509 #define MSK_CBUSY 0x20
510 #define MSK_CRC16S 0x10
511 #define MSK_DATFS 0x08
512 #define MSK_CRC7S 0x04
513 #define MSK_RESPFS 0x02
514 #define MSK_CFLCK 0x01
517 #define MSK_MCBI 0x80
518 #define MSK_EORI 0x40
519 #define MSK_EOCI 0x20
520 #define MSK_EOFI 0x10
521 #define MSK_F2FI 0x08
522 #define MSK_F1FI 0x04
523 #define MSK_F2EI 0x02
524 #define MSK_F1EI 0x01
527 #define MSK_MCBM 0x80
528 #define MSK_EORM 0x40
529 #define MSK_EOCM 0x20
530 #define MSK_EOFM 0x10
531 #define MSK_F2FM 0x08
532 #define MSK_F1FM 0x04
533 #define MSK_F2EM 0x02
534 #define MSK_F1EM 0x01
538 #define MSK_TBCK 0x08
539 #define MSK_RBCK 0x04
541 #define MSK_M0SRC 0x01
545 #define MSK_SPEN 0x40
546 #define MSK_SSDIS 0x20
547 #define MSK_MSTR 0x10
548 #define MSK_MODE 0x0C
549 #define MSK_CPOL 0x08
550 #define MSK_CPHA 0x04
553 #define MSK_SPIF 0x80
554 #define MSK_WCOL 0x40
555 #define MSK_MODF 0x10
558 #define MSK_SSCR 0x83
559 #define MSK_SSPE 0x40
560 #define MSK_SSSTA 0x20
561 #define MSK_SSSTO 0x10
563 #define MSK_SSAA 0x04
570 #define MSK_SSGC 0x01
573 #define MSK_KINL 0xf0
574 #define MSK_KINM 0x0f
577 #define MSK_KPDE 0x80
578 #define MSK_KINF 0x0f
581 #define MSK_ADIDL 0x40
582 #define MSK_ADEN 0x20
583 #define MSK_ADEOC 0x10
584 #define MSK_ADSST 0x80
585 #define MSK_ADCS 0x01
588 #define MSK_ADCD 0x1f
591 #define MSK_ADAT 0x03
593 /* Interrupt numbers: address = (number * 8) + 3 */
594 #define IE0_VECTOR 0 /* 0x03 External Interrupt 0 */
595 #define TF0_VECTOR 1 /* 0x0b Timer 0 */
596 #define IE1_VECTOR 2 /* 0x13 External Interrupt 1 */
597 #define TF1_VECTOR 3 /* 0x1b Timer 1 */
598 #define SIO_VECTOR 4 /* 0x23 Serial port */
599 #define MP3_VECTOR 5 /* 0x2b MP3 Decoder */
600 #define AUDIO_VECTOR 6 /* 0x33 Audio Interface */
601 #define MMC_VECTOR 7 /* 0x3b MMC Interface */
602 #define TWI_VECTOR 8 /* 0x43 Two Wire Controller */
603 #define SPI_VECTOR 9 /* 0x4b SPI Controller */
604 #define ADC_VECTOR 10 /* 0x53 A to D Contverter */
605 #define KBD_VECTOR 11 /* 0x5b Keyboard */
607 #define USB_VECTOR 13 /* 0x6b USB */